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1; RUN: llvm-dis < %s.bc| FileCheck %s2; RUN: verify-uselistorder < %s.bc3 4; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.5; The test checks that LLVM does not misread binary integer instructions from6; older bitcode files.7 8define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){9entry:10; CHECK: %res1 = add i1 %x1, %x111 %res1 = add i1 %x1, %x112 13; CHECK-NEXT: %res2 = add i8 %x2, %x214 %res2 = add i8 %x2, %x215 16; CHECK-NEXT: %res3 = add i16 %x3, %x317 %res3 = add i16 %x3, %x318 19; CHECK-NEXT: %res4 = add i32 %x4, %x420 %res4 = add i32 %x4, %x421 22; CHECK-NEXT: %res5 = add i64 %x5, %x523 %res5 = add i64 %x5, %x524 25; CHECK: %res6 = add nuw i1 %x1, %x126 %res6 = add nuw i1 %x1, %x127 28; CHECK: %res7 = add nsw i1 %x1, %x129 %res7 = add nsw i1 %x1, %x130 31; CHECK: %res8 = add nuw nsw i1 %x1, %x132 %res8 = add nuw nsw i1 %x1, %x133 34 ret void35}36 37define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){38entry:39; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x140 %res1 = add nuw nsw <2 x i8> %x1, %x141 42; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x243 %res2 = add nuw nsw <3 x i8> %x2, %x244 45; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x346 %res3 = add nuw nsw <4 x i8> %x3, %x347 48; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x449 %res4 = add nuw nsw <8 x i8> %x4, %x450 51; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x552 %res5 = add nuw nsw <16 x i8> %x5, %x553 54 ret void55}56 57define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){58entry:59; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x160 %res1 = add nuw nsw <2 x i16> %x1, %x161 62; CHECK-NEXT: %res2 = add nuw nsw <3 x i16> %x2, %x263 %res2 = add nuw nsw <3 x i16> %x2, %x264 65; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x366 %res3 = add nuw nsw <4 x i16> %x3, %x367 68; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x469 %res4 = add nuw nsw <8 x i16> %x4, %x470 71; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x572 %res5 = add nuw nsw <16 x i16> %x5, %x573 74 ret void75}76 77define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){78entry:79; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x180 %res1 = add nuw nsw <2 x i32> %x1, %x181 82; CHECK-NEXT: %res2 = add nuw nsw <3 x i32> %x2, %x283 %res2 = add nuw nsw <3 x i32> %x2, %x284 85; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x386 %res3 = add nuw nsw <4 x i32> %x3, %x387 88; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x489 %res4 = add nuw nsw <8 x i32> %x4, %x490 91; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x592 %res5 = add nuw nsw <16 x i32> %x5, %x593 94 ret void95}96 97define void @addvec64NuwNsw(<2 x i64> %x1, <3 x i64> %x2 ,<4 x i64> %x3, <8 x i64> %x4, <16 x i64> %x5){98entry:99; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1100 %res1 = add nuw nsw <2 x i64> %x1, %x1101 102; CHECK-NEXT: %res2 = add nuw nsw <3 x i64> %x2, %x2103 %res2 = add nuw nsw <3 x i64> %x2, %x2104 105; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3106 %res3 = add nuw nsw <4 x i64> %x3, %x3107 108; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4109 %res4 = add nuw nsw <8 x i64> %x4, %x4110 111; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5112 %res5 = add nuw nsw <16 x i64> %x5, %x5113 114 ret void115}116 117define void @sub(i8 %x1){118entry:119; CHECK: %res1 = sub i8 %x1, %x1120 %res1 = sub i8 %x1, %x1121 122; CHECK: %res2 = sub nuw i8 %x1, %x1123 %res2 = sub nuw i8 %x1, %x1124 125; CHECK: %res3 = sub nsw i8 %x1, %x1126 %res3 = sub nsw i8 %x1, %x1127 128; CHECK: %res4 = sub nuw nsw i8 %x1, %x1129 %res4 = sub nuw nsw i8 %x1, %x1130 131 ret void132}133 134define void @mul(i8 %x1){135entry:136; CHECK: %res1 = mul i8 %x1, %x1137 %res1 = mul i8 %x1, %x1138 139 ret void140}141 142define void @udiv(i8 %x1){143entry:144; CHECK: %res1 = udiv i8 %x1, %x1145 %res1 = udiv i8 %x1, %x1146 147; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1148 %res2 = udiv exact i8 %x1, %x1149 150 ret void151}152 153define void @sdiv(i8 %x1){154entry:155; CHECK: %res1 = sdiv i8 %x1, %x1156 %res1 = sdiv i8 %x1, %x1157 158; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1159 %res2 = sdiv exact i8 %x1, %x1160 161 ret void162}163 164define void @urem(i32 %x1){165entry:166; CHECK: %res1 = urem i32 %x1, %x1167 %res1 = urem i32 %x1, %x1168 169 ret void170}171 172define void @srem(i32 %x1){173entry:174; CHECK: %res1 = srem i32 %x1, %x1175 %res1 = srem i32 %x1, %x1176 177 ret void178}179