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1; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat=false 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CV2; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -use-constant-int-for-fixed-length-splat 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-CI3; RUN: llc -O3 -aarch64-enable-atomic-cfg-tidy=0 -mattr=+lse -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O34 5; This file checks that the translation from llvm IR to generic MachineInstr6; is correct.7target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"8target triple = "aarch64--"9 10; Tests for add.11; CHECK-LABEL: name: addi6412; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x013; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x114; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_ADD [[ARG1]], [[ARG2]]15; CHECK-NEXT: $x0 = COPY [[RES]]16; CHECK-NEXT: RET_ReallyLR implicit $x017define i64 @addi64(i64 %arg1, i64 %arg2) {18 %res = add i64 %arg1, %arg219 ret i64 %res20}21 22; CHECK-LABEL: name: muli6423; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x024; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x125; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_MUL [[ARG1]], [[ARG2]]26; CHECK-NEXT: $x0 = COPY [[RES]]27; CHECK-NEXT: RET_ReallyLR implicit $x028define i64 @muli64(i64 %arg1, i64 %arg2) {29 %res = mul i64 %arg1, %arg230 ret i64 %res31}32 33; Tests for alloca34; CHECK-LABEL: name: allocai6435; CHECK: stack:36; CHECK-NEXT: - { id: 0, name: ptr1, type: default, offset: 0, size: 8, alignment: 8,37; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,38; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }39; CHECK-NEXT: - { id: 1, name: ptr2, type: default, offset: 0, size: 8, alignment: 1,40; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,41; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }42; CHECK-NEXT: - { id: 2, name: ptr3, type: default, offset: 0, size: 128, alignment: 8,43; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,44; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }45; CHECK-NEXT: - { id: 3, name: ptr4, type: default, offset: 0, size: 1, alignment: 8,46; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.0.ptr147; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.1.ptr248; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.2.ptr349; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.3.ptr450define void @allocai64() {51 %ptr1 = alloca i6452 %ptr2 = alloca i64, align 153 %ptr3 = alloca i64, i32 1654 %ptr4 = alloca [0 x i64]55 ret void56}57 58; Tests for br.59; CHECK-LABEL: name: uncondbr60; CHECK: body:61;62; ABI/constant lowering and IR-level entry basic block.63; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:64;65; Make sure we have one successor and only one.66; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+]](0x80000000)67;68; Check that we emit the correct branch.69; CHECK: G_BR %[[BB2]]70;71; Check that end contains the return instruction.72; CHECK: [[END:bb.[0-9]+]].{{[a-zA-Z0-9.]+}}:73; CHECK-NEXT: RET_ReallyLR74;75; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:76; CHECK-NEXT: successors: %[[END]](0x80000000)77; CHECK: G_BR %[[END]]78define void @uncondbr() {79entry:80 br label %bb281end:82 ret void83bb2:84 br label %end85}86 87; CHECK-LABEL: name: uncondbr_fallthrough88; CHECK: body:89; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:90; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)91; CHECK: [[END]].{{[a-zA-Z0-9.]+}}:92; CHECK-NEXT: RET_ReallyLR93define void @uncondbr_fallthrough() {94entry:95 br label %end96end:97 ret void98}99 100; Tests for conditional br.101; CHECK-LABEL: name: condbr102; CHECK: body:103;104; ABI/constant lowering and IR-level entry basic block.105; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):106; Make sure we have two successors107; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),108; CHECK: %[[FALSE:bb.[0-9]+]](0x40000000)109;110; CHECK: [[ADDR:%.*]]:_(p0) = COPY $x0111;112; Check that we emit the correct branch.113; CHECK: [[TST:%.*]]:_(s1) = G_LOAD [[ADDR]](p0)114; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]115; CHECK: G_BR %[[FALSE]]116;117; Check that each successor contains the return instruction.118; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:119; CHECK-NEXT: RET_ReallyLR120; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:121; CHECK-NEXT: RET_ReallyLR122define void @condbr(ptr %tstaddr) {123 %tst = load i1, ptr %tstaddr124 br i1 %tst, label %true, label %false125true:126 ret void127false:128 ret void129}130 131; Tests for indirect br.132; CHECK-LABEL: name: indirectbr133; CHECK: body:134;135; ABI/constant lowering and IR-level entry basic block.136; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}:137; Make sure we have one successor138; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+]](0x80000000)139;140; Check basic block L1 has 2 successors: BBL1 and BBL2141; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (ir-block-address-taken %ir-block.{{[a-zA-Z0-9.]+}}):142; CHECK-NEXT: successors: %[[BB_L1]](0x40000000),143; CHECK: %[[BB_L2:bb.[0-9]+]](0x40000000)144; CHECK: G_BRINDIRECT %{{[0-9]+}}(p0)145;146; Check basic block L2 is the return basic block147; CHECK: [[BB_L2]].{{[a-zA-Z0-9.]+}} (ir-block-address-taken %ir-block.{{[a-zA-Z0-9.]+}}):148; CHECK-NEXT: RET_ReallyLR149 150@indirectbr.L = internal unnamed_addr constant [3 x ptr] [ptr blockaddress(@indirectbr, %L1), ptr blockaddress(@indirectbr, %L2), ptr null], align 8151 152define void @indirectbr() {153entry:154 br label %L1155L1: ; preds = %entry, %L1156 %i = phi i32 [ 0, %entry ], [ %inc, %L1 ]157 %inc = add i32 %i, 1158 %idxprom = zext i32 %i to i64159 %arrayidx = getelementptr inbounds [3 x ptr], ptr @indirectbr.L, i64 0, i64 %idxprom160 %brtarget = load ptr, ptr %arrayidx, align 8161 indirectbr ptr %brtarget, [label %L1, label %L2]162L2: ; preds = %L1163 ret void164}165 166; Tests for or.167; CHECK-LABEL: name: ori64168; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0169; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1170; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_OR [[ARG1]], [[ARG2]]171; CHECK-NEXT: $x0 = COPY [[RES]]172; CHECK-NEXT: RET_ReallyLR implicit $x0173define i64 @ori64(i64 %arg1, i64 %arg2) {174 %res = or i64 %arg1, %arg2175 ret i64 %res176}177 178; CHECK-LABEL: name: ori32179; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0180; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1181; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_OR [[ARG1]], [[ARG2]]182; CHECK-NEXT: $w0 = COPY [[RES]]183; CHECK-NEXT: RET_ReallyLR implicit $w0184define i32 @ori32(i32 %arg1, i32 %arg2) {185 %res = or i32 %arg1, %arg2186 ret i32 %res187}188 189; Tests for xor.190; CHECK-LABEL: name: xori64191; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0192; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1193; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_XOR [[ARG1]], [[ARG2]]194; CHECK-NEXT: $x0 = COPY [[RES]]195; CHECK-NEXT: RET_ReallyLR implicit $x0196define i64 @xori64(i64 %arg1, i64 %arg2) {197 %res = xor i64 %arg1, %arg2198 ret i64 %res199}200 201; CHECK-LABEL: name: xori32202; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0203; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1204; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_XOR [[ARG1]], [[ARG2]]205; CHECK-NEXT: $w0 = COPY [[RES]]206; CHECK-NEXT: RET_ReallyLR implicit $w0207define i32 @xori32(i32 %arg1, i32 %arg2) {208 %res = xor i32 %arg1, %arg2209 ret i32 %res210}211 212; Tests for and.213; CHECK-LABEL: name: andi64214; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0215; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1216; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_AND [[ARG1]], [[ARG2]]217; CHECK-NEXT: $x0 = COPY [[RES]]218; CHECK-NEXT: RET_ReallyLR implicit $x0219define i64 @andi64(i64 %arg1, i64 %arg2) {220 %res = and i64 %arg1, %arg2221 ret i64 %res222}223 224; CHECK-LABEL: name: andi32225; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0226; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1227; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_AND [[ARG1]], [[ARG2]]228; CHECK-NEXT: $w0 = COPY [[RES]]229; CHECK-NEXT: RET_ReallyLR implicit $w0230define i32 @andi32(i32 %arg1, i32 %arg2) {231 %res = and i32 %arg1, %arg2232 ret i32 %res233}234 235; Tests for sub.236; CHECK-LABEL: name: subi64237; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0238; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1239; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_SUB [[ARG1]], [[ARG2]]240; CHECK-NEXT: $x0 = COPY [[RES]]241; CHECK-NEXT: RET_ReallyLR implicit $x0242define i64 @subi64(i64 %arg1, i64 %arg2) {243 %res = sub i64 %arg1, %arg2244 ret i64 %res245}246 247; CHECK-LABEL: name: subi32248; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0249; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1250; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SUB [[ARG1]], [[ARG2]]251; CHECK-NEXT: $w0 = COPY [[RES]]252; CHECK-NEXT: RET_ReallyLR implicit $w0253define i32 @subi32(i32 %arg1, i32 %arg2) {254 %res = sub i32 %arg1, %arg2255 ret i32 %res256}257 258; CHECK-LABEL: name: ptrtoint259; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY $x0260; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[ARG1]]261; CHECK: $x0 = COPY [[RES]]262; CHECK: RET_ReallyLR implicit $x0263define i64 @ptrtoint(ptr %a) {264 %val = ptrtoint ptr %a to i64265 ret i64 %val266}267 268; CHECK-LABEL: name: inttoptr269; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0270; CHECK: [[RES:%[0-9]+]]:_(p0) = G_INTTOPTR [[ARG1]]271; CHECK: $x0 = COPY [[RES]]272; CHECK: RET_ReallyLR implicit $x0273define ptr @inttoptr(i64 %a) {274 %val = inttoptr i64 %a to ptr275 ret ptr %val276}277 278; CHECK-LABEL: name: trivial_bitcast279; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY $x0280; CHECK: $x0 = COPY [[ARG1]]281; CHECK: RET_ReallyLR implicit $x0282define ptr @trivial_bitcast(ptr %a) {283 ret ptr %a284}285 286; CHECK-LABEL: name: trivial_bitcast_with_copy287; CHECK: [[A:%[0-9]+]]:_(s64) = COPY $d0288; CHECK: G_BR %[[CAST:bb\.[0-9]+]]289 290; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}:291; CHECK: $x0 = COPY [[A]]292 293; CHECK: [[CAST]].{{[a-zA-Z0-9.]+}}:294; CHECK: G_BR %[[END]]295define i64 @trivial_bitcast_with_copy(double %a) {296 br label %cast297 298end:299 ret i64 %val300 301cast:302 %val = bitcast double %a to i64303 br label %end304}305 306; CHECK-LABEL: name: bitcast307; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0308; CHECK: [[RES1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[ARG1]]309; CHECK: [[RES2:%[0-9]+]]:_(s64) = G_BITCAST [[RES1]]310; CHECK: $x0 = COPY [[RES2]]311; CHECK: RET_ReallyLR implicit $x0312define i64 @bitcast(i64 %a) {313 %res1 = bitcast i64 %a to <2 x i32>314 %res2 = bitcast <2 x i32> %res1 to i64315 ret i64 %res2316}317 318; CHECK-LABEL: name: addrspacecast319; CHECK: [[ARG1:%[0-9]+]]:_(p1) = COPY $x0320; CHECK: [[RES1:%[0-9]+]]:_(p2) = G_ADDRSPACE_CAST [[ARG1]]321; CHECK: [[RES2:%[0-9]+]]:_(p0) = G_ADDRSPACE_CAST [[RES1]]322; CHECK: $x0 = COPY [[RES2]]323; CHECK: RET_ReallyLR implicit $x0324define ptr @addrspacecast(ptr addrspace(1) %a) {325 %res1 = addrspacecast ptr addrspace(1) %a to ptr addrspace(2)326 %res2 = addrspacecast ptr addrspace(2) %res1 to ptr327 ret ptr %res2328}329 330; CHECK-LABEL: name: trunc331; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0332; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_LOAD333; CHECK: [[RES1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1]]334; CHECK: [[RES2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[VEC]]335define void @trunc(i64 %a) {336 %vecptr = alloca <4 x i32>337 %vec = load <4 x i32>, ptr %vecptr338 %res1 = trunc i64 %a to i8339 %res2 = trunc <4 x i32> %vec to <4 x i16>340 ret void341}342 343; CHECK-LABEL: name: load344; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0345; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY $x1346; CHECK: [[VAL1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load (s64) from %ir.addr, align 16)347; CHECK: [[VAL2:%[0-9]+]]:_(s64) = G_LOAD [[ADDR42]](p42) :: (load (s64) from %ir.addr42, addrspace 42)348; CHECK: [[SUM2:%.*]]:_(s64) = G_ADD [[VAL1]], [[VAL2]]349; CHECK: [[VAL3:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (volatile load (s64) from %ir.addr)350; CHECK: [[SUM3:%[0-9]+]]:_(s64) = G_ADD [[SUM2]], [[VAL3]]351; CHECK: [[VAL4:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load (s64) from %ir.addr, !range !0)352; CHECK: [[SUM4:%[0-9]+]]:_(s64) = G_ADD [[SUM3]], [[VAL4]]353; CHECK: $x0 = COPY [[SUM4]]354; CHECK: RET_ReallyLR implicit $x0355define i64 @load(ptr %addr, ptr addrspace(42) %addr42) {356 %val1 = load i64, ptr %addr, align 16357 358 %val2 = load i64, ptr addrspace(42) %addr42359 %sum2 = add i64 %val1, %val2360 361 %val3 = load volatile i64, ptr %addr362 %sum3 = add i64 %sum2, %val3363 364 %val4 = load i64, ptr %addr, !range !0365 %sum4 = add i64 %sum3, %val4366 ret i64 %sum4367}368 369; CHECK-LABEL: name: store370; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0371; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY $x1372; CHECK: [[VAL1:%[0-9]+]]:_(s64) = COPY $x2373; CHECK: [[VAL2:%[0-9]+]]:_(s64) = COPY $x3374; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (store (s64) into %ir.addr, align 16)375; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store (s64) into %ir.addr42, addrspace 42)376; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (volatile store (s64) into %ir.addr)377; CHECK: RET_ReallyLR378define void @store(ptr %addr, ptr addrspace(42) %addr42, i64 %val1, i64 %val2) {379 store i64 %val1, ptr %addr, align 16380 store i64 %val2, ptr addrspace(42) %addr42381 store volatile i64 %val1, ptr %addr382 %sum = add i64 %val1, %val2383 ret void384}385 386; CHECK-LABEL: name: intrinsics387; CHECK: [[CUR:%[0-9]+]]:_(s32) = COPY $w0388; CHECK: [[BITS:%[0-9]+]]:_(s32) = COPY $w1389; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0390; CHECK: [[PTR_VEC:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr.vec391; CHECK: [[VEC:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[PTR_VEC]]392; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x s8>), [[VEC]](<8 x s8>), [[PTR]](p0)393; CHECK: RET_ReallyLR394declare ptr @llvm.returnaddress(i32)395declare void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8>, <8 x i8>, ptr)396declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0(ptr)397define void @intrinsics(i32 %cur, i32 %bits) {398 %ptr = call ptr @llvm.returnaddress(i32 0)399 %ptr.vec = alloca <8 x i8>400 %vec = load <8 x i8>, ptr %ptr.vec401 call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %vec, <8 x i8> %vec, ptr %ptr)402 ret void403}404 405; CHECK-LABEL: name: test_phi406; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+]]407; CHECK: G_BR %[[FALSE:bb\.[0-9]+]]408 409; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:410; CHECK: [[RES1:%[0-9]+]]:_(s32) = G_LOAD411 412; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:413; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_LOAD414 415; CHECK: [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]416; CHECK: $w0 = COPY [[RES]]417define i32 @test_phi(ptr %addr1, ptr %addr2, i1 %tst) {418 br i1 %tst, label %true, label %false419 420true:421 %res1 = load i32, ptr %addr1422 br label %end423 424false:425 %res2 = load i32, ptr %addr2426 br label %end427 428end:429 %res = phi i32 [%res1, %true], [%res2, %false]430 ret i32 %res431}432 433; CHECK-LABEL: name: unreachable434; CHECK: G_ADD435; CHECK-NEXT: ...436define void @unreachable(i32 %a) {437 %sum = add i32 %a, %a438 unreachable439}440 441 ; It's important that constants are after argument passing, but before the442 ; rest of the entry block.443; CHECK-LABEL: name: constant_int444; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0445; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1446 447; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:448; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]449; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]450; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]]451; CHECK: $w0 = COPY [[RES]]452 453define i32 @constant_int(i32 %in) {454 br label %next455 456next:457 %sum1 = add i32 %in, 1458 %sum2 = add i32 %in, 1459 %res = add i32 %sum1, %sum2460 ret i32 %res461}462 463; CHECK-LABEL: name: constant_int_start464; CHECK: [[TWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 2465; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42466; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CONSTANT i32 44467define i32 @constant_int_start() {468 %res = add i32 2, 42469 ret i32 %res470}471 472; CHECK-LABEL: name: test_undef473; CHECK: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF474; CHECK: $w0 = COPY [[UNDEF]]475define i32 @test_undef() {476 ret i32 undef477}478 479; CHECK-LABEL: name: test_constant_inttoptr480; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1481; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ONE]]482; CHECK: $x0 = COPY [[PTR]]483define ptr @test_constant_inttoptr() {484 ret ptr inttoptr(i64 1 to ptr)485}486 487 ; This failed purely because the Constant -> VReg map was kept across488 ; functions, so reuse the "i64 1" from above.489; CHECK-LABEL: name: test_reused_constant490; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1491; CHECK: $x0 = COPY [[ONE]]492define i64 @test_reused_constant() {493 ret i64 1494}495 496; CHECK-LABEL: name: test_sext497; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0498; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SEXT [[IN]]499; CHECK: $x0 = COPY [[RES]]500define i64 @test_sext(i32 %in) {501 %res = sext i32 %in to i64502 ret i64 %res503}504 505; CHECK-LABEL: name: test_zext506; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0507; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ZEXT [[IN]]508; CHECK: $x0 = COPY [[RES]]509define i64 @test_zext(i32 %in) {510 %res = zext i32 %in to i64511 ret i64 %res512}513 514; CHECK-LABEL: name: test_shl515; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0516; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1517; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SHL [[ARG1]], [[ARG2]]518; CHECK-NEXT: $w0 = COPY [[RES]]519; CHECK-NEXT: RET_ReallyLR implicit $w0520define i32 @test_shl(i32 %arg1, i32 %arg2) {521 %res = shl i32 %arg1, %arg2522 ret i32 %res523}524 525 526; CHECK-LABEL: name: test_lshr527; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0528; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1529; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_LSHR [[ARG1]], [[ARG2]]530; CHECK-NEXT: $w0 = COPY [[RES]]531; CHECK-NEXT: RET_ReallyLR implicit $w0532define i32 @test_lshr(i32 %arg1, i32 %arg2) {533 %res = lshr i32 %arg1, %arg2534 ret i32 %res535}536 537; CHECK-LABEL: name: test_ashr538; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0539; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1540; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_ASHR [[ARG1]], [[ARG2]]541; CHECK-NEXT: $w0 = COPY [[RES]]542; CHECK-NEXT: RET_ReallyLR implicit $w0543define i32 @test_ashr(i32 %arg1, i32 %arg2) {544 %res = ashr i32 %arg1, %arg2545 ret i32 %res546}547 548; CHECK-LABEL: name: test_sdiv549; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0550; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1551; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SDIV [[ARG1]], [[ARG2]]552; CHECK-NEXT: $w0 = COPY [[RES]]553; CHECK-NEXT: RET_ReallyLR implicit $w0554define i32 @test_sdiv(i32 %arg1, i32 %arg2) {555 %res = sdiv i32 %arg1, %arg2556 ret i32 %res557}558 559; CHECK-LABEL: name: test_udiv560; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0561; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1562; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UDIV [[ARG1]], [[ARG2]]563; CHECK-NEXT: $w0 = COPY [[RES]]564; CHECK-NEXT: RET_ReallyLR implicit $w0565define i32 @test_udiv(i32 %arg1, i32 %arg2) {566 %res = udiv i32 %arg1, %arg2567 ret i32 %res568}569 570; CHECK-LABEL: name: test_srem571; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0572; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1573; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SREM [[ARG1]], [[ARG2]]574; CHECK-NEXT: $w0 = COPY [[RES]]575; CHECK-NEXT: RET_ReallyLR implicit $w0576define i32 @test_srem(i32 %arg1, i32 %arg2) {577 %res = srem i32 %arg1, %arg2578 ret i32 %res579}580 581; CHECK-LABEL: name: test_urem582; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0583; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1584; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UREM [[ARG1]], [[ARG2]]585; CHECK-NEXT: $w0 = COPY [[RES]]586; CHECK-NEXT: RET_ReallyLR implicit $w0587define i32 @test_urem(i32 %arg1, i32 %arg2) {588 %res = urem i32 %arg1, %arg2589 ret i32 %res590}591 592; CHECK-LABEL: name: test_constant_null593; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0594; CHECK: $x0 = COPY [[NULL]]595define ptr @test_constant_null() {596 ret ptr null597}598 599; CHECK-LABEL: name: test_struct_memops600; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0601; CHECK: [[VAL1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)602; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4603; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)604; CHECK: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load (s32) from %ir.addr + 4)605; CHECK: G_STORE [[VAL1]](s8), [[ADDR]](p0) :: (store (s8) into %ir.addr, align 4)606; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST1]](s64)607; CHECK: G_STORE [[VAL2]](s32), [[GEP2]](p0) :: (store (s32) into %ir.addr + 4)608define void @test_struct_memops(ptr %addr) {609 %val = load { i8, i32 }, ptr %addr610 store { i8, i32 } %val, ptr %addr611 ret void612}613 614; CHECK-LABEL: name: test_i1_memops615; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0616; CHECK: [[VAL:%[0-9]+]]:_(s1) = G_LOAD [[ADDR]](p0) :: (load (s1) from %ir.addr)617; CHECK: G_STORE [[VAL]](s1), [[ADDR]](p0) :: (store (s1) into %ir.addr)618define void @test_i1_memops(ptr %addr) {619 %val = load i1, ptr %addr620 store i1 %val, ptr %addr621 ret void622}623 624; CHECK-LABEL: name: int_comparison625; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0626; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1627; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2628; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]629; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)630define void @int_comparison(i32 %a, i32 %b, ptr %addr) {631 %res = icmp ne i32 %a, %b632 store i1 %res, ptr %addr633 ret void634}635 636; CHECK-LABEL: name: ptr_comparison637; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY $x0638; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY $x1639; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2640; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]641; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)642define void @ptr_comparison(ptr %a, ptr %b, ptr %addr) {643 %res = icmp eq ptr %a, %b644 store i1 %res, ptr %addr645 ret void646}647 648; CHECK-LABEL: name: test_fadd649; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0650; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1651; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FADD [[ARG1]], [[ARG2]]652; CHECK-NEXT: $s0 = COPY [[RES]]653; CHECK-NEXT: RET_ReallyLR implicit $s0654define float @test_fadd(float %arg1, float %arg2) {655 %res = fadd float %arg1, %arg2656 ret float %res657}658 659; CHECK-LABEL: name: test_fsub660; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0661; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1662; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FSUB [[ARG1]], [[ARG2]]663; CHECK-NEXT: $s0 = COPY [[RES]]664; CHECK-NEXT: RET_ReallyLR implicit $s0665define float @test_fsub(float %arg1, float %arg2) {666 %res = fsub float %arg1, %arg2667 ret float %res668}669 670; CHECK-LABEL: name: test_fmul671; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0672; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1673; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FMUL [[ARG1]], [[ARG2]]674; CHECK-NEXT: $s0 = COPY [[RES]]675; CHECK-NEXT: RET_ReallyLR implicit $s0676define float @test_fmul(float %arg1, float %arg2) {677 %res = fmul float %arg1, %arg2678 ret float %res679}680 681; CHECK-LABEL: name: test_fdiv682; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0683; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1684; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FDIV [[ARG1]], [[ARG2]]685; CHECK-NEXT: $s0 = COPY [[RES]]686; CHECK-NEXT: RET_ReallyLR implicit $s0687define float @test_fdiv(float %arg1, float %arg2) {688 %res = fdiv float %arg1, %arg2689 ret float %res690}691 692; CHECK-LABEL: name: test_frem693; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0694; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1695; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FREM [[ARG1]], [[ARG2]]696; CHECK-NEXT: $s0 = COPY [[RES]]697; CHECK-NEXT: RET_ReallyLR implicit $s0698define float @test_frem(float %arg1, float %arg2) {699 %res = frem float %arg1, %arg2700 ret float %res701}702 703; CHECK-LABEL: name: test_sadd_overflow704; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0705; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1706; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2707; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SADDO [[LHS]], [[RHS]]708; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)709; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4710; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)711; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)712declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)713define void @test_sadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {714 %res = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %lhs, i32 %rhs)715 store { i32, i1 } %res, ptr %addr716 ret void717}718 719; CHECK-LABEL: name: test_uadd_overflow720; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0721; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1722; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2723; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UADDO [[LHS]], [[RHS]]724; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)725; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4726; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)727; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)728declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)729define void @test_uadd_overflow(i32 %lhs, i32 %rhs, ptr %addr) {730 %res = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lhs, i32 %rhs)731 store { i32, i1 } %res, ptr %addr732 ret void733}734 735; CHECK-LABEL: name: test_ssub_overflow736; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0737; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1738; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2739; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SSUBO [[LHS]], [[RHS]]740; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.subr)741; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4742; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)743; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.subr + 4, align 4)744declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32)745define void @test_ssub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {746 %res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %lhs, i32 %rhs)747 store { i32, i1 } %res, ptr %subr748 ret void749}750 751; CHECK-LABEL: name: test_usub_overflow752; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0753; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1754; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2755; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_USUBO [[LHS]], [[RHS]]756; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.subr)757; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4758; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)759; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.subr + 4, align 4)760declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32)761define void @test_usub_overflow(i32 %lhs, i32 %rhs, ptr %subr) {762 %res = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %lhs, i32 %rhs)763 store { i32, i1 } %res, ptr %subr764 ret void765}766 767; CHECK-LABEL: name: test_smul_overflow768; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0769; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1770; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2771; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SMULO [[LHS]], [[RHS]]772; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)773; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4774; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)775; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)776declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)777define void @test_smul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {778 %res = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %lhs, i32 %rhs)779 store { i32, i1 } %res, ptr %addr780 ret void781}782 783; CHECK-LABEL: name: test_umul_overflow784; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0785; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1786; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2787; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UMULO [[LHS]], [[RHS]]788; CHECK: G_STORE [[VAL]](s32), [[ADDR]](p0) :: (store (s32) into %ir.addr)789; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4790; CHECK: [[GEP:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ADDR]], [[CST]](s64)791; CHECK: G_STORE [[OVERFLOW]](s1), [[GEP]](p0) :: (store (s1) into %ir.addr + 4, align 4)792declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)793define void @test_umul_overflow(i32 %lhs, i32 %rhs, ptr %addr) {794 %res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)795 store { i32, i1 } %res, ptr %addr796 ret void797}798 799; CHECK-LABEL: name: test_extractvalue800; CHECK: %0:_(p0) = COPY $x0801; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)802; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4803; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)804; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4)805; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8806; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)807; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8)808; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12809; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)810; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12)811; CHECK: $w0 = COPY [[LD3]](s32)812%struct.nested = type {i8, { i8, i32 }, i32}813define i32 @test_extractvalue(ptr %addr) {814 %struct = load %struct.nested, ptr %addr815 %res = extractvalue %struct.nested %struct, 1, 1816 ret i32 %res817}818 819; CHECK-LABEL: name: test_extractvalue_agg820; CHECK: %0:_(p0) = COPY $x0821; CHECK: %1:_(p0) = COPY $x1822; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)823; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4824; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)825; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4)826; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8827; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)828; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8)829; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12830; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)831; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12)832; CHECK: G_STORE [[LD2]](s8), %1(p0) :: (store (s8) into %ir.addr2, align 4)833; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](s64)834; CHECK: G_STORE [[LD3]](s32), [[GEP4]](p0) :: (store (s32) into %ir.addr2 + 4)835define void @test_extractvalue_agg(ptr %addr, ptr %addr2) {836 %struct = load %struct.nested, ptr %addr837 %res = extractvalue %struct.nested %struct, 1838 store {i8, i32} %res, ptr %addr2839 ret void840}841 842; CHECK-LABEL: name: test_trivial_extract_ptr843; CHECK: [[STRUCT:%[0-9]+]]:_(p0) = COPY $x0844; CHECK: [[VAL32:%[0-9]+]]:_(s32) = COPY $w1845; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_TRUNC [[VAL32]]846; CHECK: G_STORE [[VAL]](s8), [[STRUCT]](p0)847define void @test_trivial_extract_ptr([1 x ptr] %s, i8 %val) {848 %addr = extractvalue [1 x ptr] %s, 0849 store i8 %val, ptr %addr850 ret void851}852 853; CHECK-LABEL: name: test_insertvalue854; CHECK: %0:_(p0) = COPY $x0855; CHECK: %1:_(s32) = COPY $w1856; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)857; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4858; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)859; CHECK: [[LD2:%[0-9]+]]:_(s8) = G_LOAD [[GEP1]](p0) :: (load (s8) from %ir.addr + 4, align 4)860; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8861; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)862; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.addr + 8)863; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 12864; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)865; CHECK: [[LD4:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 12)866; CHECK: G_STORE [[LD1]](s8), %0(p0) :: (store (s8) into %ir.addr, align 4)867; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)868; CHECK: G_STORE [[LD2]](s8), [[GEP4]](p0) :: (store (s8) into %ir.addr + 4, align 4)869; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST2]](s64)870; CHECK: G_STORE %1(s32), [[GEP5]](p0) :: (store (s32) into %ir.addr + 8)871; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)872; CHECK: G_STORE [[LD4]](s32), [[GEP6]](p0) :: (store (s32) into %ir.addr + 12)873define void @test_insertvalue(ptr %addr, i32 %val) {874 %struct = load %struct.nested, ptr %addr875 %newstruct = insertvalue %struct.nested %struct, i32 %val, 1, 1876 store %struct.nested %newstruct, ptr %addr877 ret void878}879 880define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) {881; CHECK-LABEL: name: test_trivial_insert882; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY $x0883; CHECK: [[VAL:%[0-9]+]]:_(s64) = COPY $x1884; CHECK: $x0 = COPY [[VAL]]885 %res = insertvalue [1 x i64] %s, i64 %val, 0886 ret [1 x i64] %res887}888 889define [1 x ptr] @test_trivial_insert_ptr([1 x ptr] %s, ptr %val) {890; CHECK-LABEL: name: test_trivial_insert_ptr891; CHECK: [[STRUCT:%[0-9]+]]:_(p0) = COPY $x0892; CHECK: [[VAL:%[0-9]+]]:_(p0) = COPY $x1893; CHECK: $x0 = COPY [[VAL]]894 %res = insertvalue [1 x ptr] %s, ptr %val, 0895 ret [1 x ptr] %res896}897 898; CHECK-LABEL: name: test_insertvalue_agg899; CHECK: %0:_(p0) = COPY $x0900; CHECK: %1:_(p0) = COPY $x1901; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD %1(p0) :: (load (s8) from %ir.addr2, align 4)902; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4903; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %1, [[CST1]](s64)904; CHECK: [[LD2:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load (s32) from %ir.addr2 + 4)905; CHECK: [[LD3:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.addr, align 4)906; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)907; CHECK: [[LD4:%[0-9]+]]:_(s8) = G_LOAD [[GEP2]](p0) :: (load (s8) from %ir.addr + 4, align 4)908; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8909; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)910; CHECK: [[LD5:%[0-9]+]]:_(s32) = G_LOAD [[GEP3]](p0) :: (load (s32) from %ir.addr + 8)911; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 12912; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](s64)913; CHECK: [[LD6:%[0-9]+]]:_(s32) = G_LOAD [[GEP4]](p0) :: (load (s32) from %ir.addr + 12)914; CHECK: G_STORE [[LD3]](s8), %0(p0) :: (store (s8) into %ir.addr, align 4)915; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST1]](s64)916; CHECK: G_STORE [[LD1]](s8), [[GEP5]](p0) :: (store (s8) into %ir.addr + 4, align 4)917; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST3]](s64)918; CHECK: G_STORE [[LD2]](s32), [[GEP6]](p0) :: (store (s32) into %ir.addr + 8)919; CHECK: [[GEP7:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD %0, [[CST4]](s64)920; CHECK: G_STORE [[LD6]](s32), [[GEP7]](p0) :: (store (s32) into %ir.addr + 12)921define void @test_insertvalue_agg(ptr %addr, ptr %addr2) {922 %smallstruct = load {i8, i32}, ptr %addr2923 %struct = load %struct.nested, ptr %addr924 %res = insertvalue %struct.nested %struct, {i8, i32} %smallstruct, 1925 store %struct.nested %res, ptr %addr926 ret void927}928 929; CHECK-LABEL: name: test_select930; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0931; CHECK: [[TSTEXT:%[0-9]+]]:_(s8) = G_TRUNC [[TST_C]]932; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w1933; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w2934; CHECK: [[TSTASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TSTEXT]], 1935; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TSTASSERT]]936; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]937; CHECK: $w0 = COPY [[RES]]938define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {939 %res = select i1 %tst, i32 %lhs, i32 %rhs940 ret i32 %res941}942 943; CHECK-LABEL: name: test_select_flags944; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0945; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]]946; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0947; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s1948; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC8]], 1949; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNCASSERT]]950; CHECK: [[SELECT:%[0-9]+]]:_(s32) = nnan G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]951define float @test_select_flags(i1 %tst, float %lhs, float %rhs) {952 %res = select nnan i1 %tst, float %lhs, float %rhs953 ret float %res954}955 956; Don't take the flags from the compare condition957; CHECK-LABEL: name: test_select_cmp_flags958; CHECK: [[COPY0:%[0-9]+]]:_(s32) = COPY $s0959; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s1960; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2961; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s3962; CHECK: [[CMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(oeq), [[COPY0]](s32), [[COPY1]]963; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[CMP]](s1), [[COPY2]], [[COPY3]]964define float @test_select_cmp_flags(float %cmp0, float %cmp1, float %lhs, float %rhs) {965 %tst = fcmp nsz oeq float %cmp0, %cmp1966 %res = select i1 %tst, float %lhs, float %rhs967 ret float %res968}969 970; CHECK-LABEL: name: test_select_ptr971; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0972; CHECK: [[TSTEXT:%[0-9]+]]:_(s8) = G_TRUNC [[TST_C]]973; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY $x1974; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY $x2975; CHECK: [[TSTASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TSTEXT]], 1976; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TSTASSERT]]977; CHECK: [[RES:%[0-9]+]]:_(p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]978; CHECK: $x0 = COPY [[RES]]979define ptr @test_select_ptr(i1 %tst, ptr %lhs, ptr %rhs) {980 %res = select i1 %tst, ptr %lhs, ptr %rhs981 ret ptr %res982}983 984; CHECK-LABEL: name: test_select_vec985; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0986; CHECK: [[TSTEXT:%[0-9]+]]:_(s8) = G_TRUNC [[TST_C]]987; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY $q0988; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY $q1989; CHECK: [[TSTASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TSTEXT]], 1990; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TSTASSERT]]991; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]992; CHECK: $q0 = COPY [[RES]]993define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {994 %res = select i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs995 ret <4 x i32> %res996}997 998; CHECK-LABEL: name: test_vselect_vec999; CHECK: [[TST32:%[0-9]+]]:_(<4 x s32>) = COPY $q01000; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY $q11001; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY $q21002; CHECK: [[TST:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)1003; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]1004; CHECK: $q0 = COPY [[RES]]1005define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %rhs) {1006 %tst = trunc <4 x i32> %tst32 to <4 x i1>1007 %res = select <4 x i1> %tst, <4 x i32> %lhs, <4 x i32> %rhs1008 ret <4 x i32> %res1009}1010 1011; CHECK-LABEL: name: test_fptosi1012; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY $x01013; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)1014; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOSI [[FP]](s32)1015; CHECK: $x0 = COPY [[RES]]1016define i64 @test_fptosi(ptr %fp.addr) {1017 %fp = load float, ptr %fp.addr1018 %res = fptosi float %fp to i641019 ret i64 %res1020}1021 1022; CHECK-LABEL: name: test_fptoui1023; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY $x01024; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)1025; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOUI [[FP]](s32)1026; CHECK: $x0 = COPY [[RES]]1027define i64 @test_fptoui(ptr %fp.addr) {1028 %fp = load float, ptr %fp.addr1029 %res = fptoui float %fp to i641030 ret i64 %res1031}1032 1033; CHECK-LABEL: name: test_sitofp1034; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x01035; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w11036; CHECK: [[FP:%[0-9]+]]:_(s64) = G_SITOFP [[IN]](s32)1037; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)1038define void @test_sitofp(ptr %addr, i32 %in) {1039 %fp = sitofp i32 %in to double1040 store double %fp, ptr %addr1041 ret void1042}1043 1044; CHECK-LABEL: name: test_uitofp1045; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x01046; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w11047; CHECK: [[FP:%[0-9]+]]:_(s64) = G_UITOFP [[IN]](s32)1048; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)1049define void @test_uitofp(ptr %addr, i32 %in) {1050 %fp = uitofp i32 %in to double1051 store double %fp, ptr %addr1052 ret void1053}1054 1055; CHECK-LABEL: name: test_fpext1056; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $s01057; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPEXT [[IN]](s32)1058; CHECK: $d0 = COPY [[RES]]1059define double @test_fpext(float %in) {1060 %res = fpext float %in to double1061 ret double %res1062}1063 1064; CHECK-LABEL: name: test_fptrunc1065; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY $d01066; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPTRUNC [[IN]](s64)1067; CHECK: $s0 = COPY [[RES]]1068define float @test_fptrunc(double %in) {1069 %res = fptrunc double %in to float1070 ret float %res1071}1072 1073; CHECK-LABEL: name: test_constant_float1074; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x01075; CHECK: [[TMP:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+001076; CHECK: G_STORE [[TMP]](s32), [[ADDR]](p0)1077define void @test_constant_float(ptr %addr) {1078 store float 1.5, ptr %addr1079 ret void1080}1081 1082; CHECK-LABEL: name: float_comparison1083; CHECK: [[LHSADDR:%[0-9]+]]:_(p0) = COPY $x01084; CHECK: [[RHSADDR:%[0-9]+]]:_(p0) = COPY $x11085; CHECK: [[BOOLADDR:%[0-9]+]]:_(p0) = COPY $x21086; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_LOAD [[LHSADDR]](p0)1087; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_LOAD [[RHSADDR]](p0)1088; CHECK: [[TST:%[0-9]+]]:_(s1) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]1089; CHECK: G_STORE [[TST]](s1), [[BOOLADDR]](p0)1090define void @float_comparison(ptr %a.addr, ptr %b.addr, ptr %bool.addr) {1091 %a = load float, ptr %a.addr1092 %b = load float, ptr %b.addr1093 %res = fcmp nnan ninf nsz arcp contract afn reassoc oge float %a, %b1094 store i1 %res, ptr %bool.addr1095 ret void1096}1097 1098; CHECK-LABEL: name: trivial_float_comparison1099; CHECK: [[ENTRY_R1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false1100; CHECK: [[ENTRY_R2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true1101; CHECK: [[R1:%[0-9]+]]:_(s1) = COPY [[ENTRY_R1]](s1)1102; CHECK: [[R2:%[0-9]+]]:_(s1) = COPY [[ENTRY_R2]](s1)1103; CHECK: G_ADD [[R1]], [[R2]]1104define i1 @trivial_float_comparison(double %a, double %b) {1105 %r1 = fcmp false double %a, %b1106 %r2 = fcmp true double %a, %b1107 %sum = add i1 %r1, %r21108 ret i1 %sum1109}1110 1111@var = global i32 01112 1113define ptr @test_global() {1114; CHECK-LABEL: name: test_global1115; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var{{$}}1116; CHECK: $x0 = COPY [[TMP]](p0)1117 1118 ret ptr @var1119}1120 1121@var1 = addrspace(42) global i32 01122define ptr addrspace(42) @test_global_addrspace() {1123; CHECK-LABEL: name: test_global1124; CHECK: [[TMP:%[0-9]+]]:_(p42) = G_GLOBAL_VALUE @var1{{$}}1125; CHECK: $x0 = COPY [[TMP]](p42)1126 1127 ret ptr addrspace(42) @var11128}1129 1130 1131define ptr @test_global_func() {1132; CHECK-LABEL: name: test_global_func1133; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @allocai64{{$}}1134; CHECK: $x0 = COPY [[TMP]](p0)1135 1136 ret ptr @allocai641137}1138 1139declare void @llvm.memcpy.p0.p0.i64(ptr, ptr, i64, i1)1140define void @test_memcpy(ptr %dst, ptr %src, i64 %size) {1141; CHECK-LABEL: name: test_memcpy1142; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x01143; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x11144; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x21145; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)1146 call void @llvm.memcpy.p0.p0.i64(ptr %dst, ptr %src, i64 %size, i1 0)1147 ret void1148}1149 1150define void @test_memcpy_tail(ptr %dst, ptr %src, i64 %size) {1151; CHECK-LABEL: name: test_memcpy_tail1152; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x01153; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x11154; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x21155; CHECK: G_MEMCPY [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)1156 tail call void @llvm.memcpy.p0.p0.i64(ptr %dst, ptr %src, i64 %size, i1 0)1157 ret void1158}1159 1160declare void @llvm.memcpy.p1.p1.i64(ptr addrspace(1), ptr addrspace(1), i64, i1)1161define void @test_memcpy_nonzero_as(ptr addrspace(1) %dst, ptr addrspace(1) %src, i64 %size) {1162; CHECK-LABEL: name: test_memcpy_nonzero_as1163; CHECK: [[DST:%[0-9]+]]:_(p1) = COPY $x01164; CHECK: [[SRC:%[0-9]+]]:_(p1) = COPY $x11165; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x21166; CHECK: G_MEMCPY [[DST]](p1), [[SRC]](p1), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst, addrspace 1), (load (s8) from %ir.src, addrspace 1)1167 call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) %dst, ptr addrspace(1) %src, i64 %size, i1 0)1168 ret void1169}1170 1171declare void @llvm.memmove.p0.p0.i64(ptr, ptr, i64, i1)1172define void @test_memmove(ptr %dst, ptr %src, i64 %size) {1173; CHECK-LABEL: name: test_memmove1174; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x01175; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x11176; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x21177; CHECK: G_MEMMOVE [[DST]](p0), [[SRC]](p0), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)1178 call void @llvm.memmove.p0.p0.i64(ptr %dst, ptr %src, i64 %size, i1 0)1179 ret void1180}1181 1182declare void @llvm.memset.p0.i64(ptr, i8, i64, i1)1183define void @test_memset(ptr %dst, i8 %val, i64 %size) {1184; CHECK-LABEL: name: test_memset1185; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x01186; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY $w11187; CHECK: [[SRC:%[0-9]+]]:_(s8) = G_TRUNC [[SRC_C]]1188; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x21189; CHECK: G_MEMSET [[DST]](p0), [[SRC]](s8), [[SIZE]](s64), 0 :: (store (s8) into %ir.dst)1190 call void @llvm.memset.p0.i64(ptr %dst, i8 %val, i64 %size, i1 0)1191 ret void1192}1193 1194define void @test_large_const(ptr %addr) {1195; CHECK-LABEL: name: test_large_const1196; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x01197; CHECK: [[VAL:%[0-9]+]]:_(s128) = G_CONSTANT i128 421198; CHECK: G_STORE [[VAL]](s128), [[ADDR]](p0)1199 store i128 42, ptr %addr1200 ret void1201}1202 1203; When there was no formal argument handling (so the first BB was empty) we used1204; to insert the constants at the end of the block, even if they were encountered1205; after the block's terminators had been emitted. Also make sure the order is1206; correct.1207define ptr @test_const_placement() {1208; CHECK-LABEL: name: test_const_placement1209; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):1210; CHECK: [[VAL_INT:%[0-9]+]]:_(s32) = G_CONSTANT i32 421211; CHECK: [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](s32)1212; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:1213 br label %next1214 1215next:1216 ret ptr inttoptr(i32 42 to ptr)1217}1218 1219declare void @llvm.va_end(ptr)1220define void @test_va_end(ptr %list) {1221; CHECK-LABEL: name: test_va_end1222; CHECK-NOT: va_end1223; CHECK-NOT: INTRINSIC1224; CHECK: RET_ReallyLR1225 call void @llvm.va_end(ptr %list)1226 ret void1227}1228 1229define void @test_va_arg(ptr %list) {1230; CHECK-LABEL: test_va_arg1231; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY $x01232; CHECK: G_VAARG [[LIST]](p0), 81233; CHECK: G_VAARG [[LIST]](p0), 11234; CHECK: G_VAARG [[LIST]](p0), 161235 1236 %v0 = va_arg ptr %list, i641237 %v1 = va_arg ptr %list, i81238 %v2 = va_arg ptr %list, i1281239 ret void1240}1241 1242declare float @llvm.pow.f32(float, float)1243define float @test_pow_intrin(float %l, float %r) {1244; CHECK-LABEL: name: test_pow_intrin1245; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s01246; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $s11247; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOW [[LHS]], [[RHS]]1248; CHECK: $s0 = COPY [[RES]]1249 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.pow.f32(float %l, float %r)1250 ret float %res1251}1252 1253declare float @llvm.powi.f32.i32(float, i32)1254define float @test_powi_intrin(float %l, i32 %r) {1255; CHECK-LABEL: name: test_powi_intrin1256; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s01257; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w01258; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOWI [[LHS]], [[RHS]]1259; CHECK: $s0 = COPY [[RES]]1260 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.powi.f32.i32(float %l, i32 %r)1261 ret float %res1262}1263 1264declare float @llvm.fma.f32(float, float, float)1265define float @test_fma_intrin(float %a, float %b, float %c) {1266; CHECK-LABEL: name: test_fma_intrin1267; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01268; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $s11269; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $s21270; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[A]], [[B]], [[C]]1271; CHECK: $s0 = COPY [[RES]]1272 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.fma.f32(float %a, float %b, float %c)1273 ret float %res1274}1275 1276declare float @llvm.exp.f32(float)1277define float @test_exp_intrin(float %a) {1278; CHECK-LABEL: name: test_exp_intrin1279; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01280; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FEXP [[A]]1281; CHECK: $s0 = COPY [[RES]]1282 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.exp.f32(float %a)1283 ret float %res1284}1285 1286declare float @llvm.exp2.f32(float)1287define float @test_exp2_intrin(float %a) {1288; CHECK-LABEL: name: test_exp2_intrin1289; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01290; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FEXP2 [[A]]1291; CHECK: $s0 = COPY [[RES]]1292 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.exp2.f32(float %a)1293 ret float %res1294}1295 1296declare float @llvm.log.f32(float)1297define float @test_log_intrin(float %a) {1298; CHECK-LABEL: name: test_log_intrin1299; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01300; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FLOG [[A]]1301; CHECK: $s0 = COPY [[RES]]1302 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.log.f32(float %a)1303 ret float %res1304}1305 1306declare float @llvm.log2.f32(float)1307define float @test_log2_intrin(float %a) {1308; CHECK-LABEL: name: test_log2_intrin1309; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01310; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG2 [[A]]1311; CHECK: $s0 = COPY [[RES]]1312 %res = call float @llvm.log2.f32(float %a)1313 ret float %res1314}1315 1316declare float @llvm.log10.f32(float)1317define float @test_log10_intrin(float %a) {1318; CHECK-LABEL: name: test_log10_intrin1319; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01320; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FLOG10 [[A]]1321; CHECK: $s0 = COPY [[RES]]1322 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.log10.f32(float %a)1323 ret float %res1324}1325 1326declare float @llvm.fabs.f32(float)1327define float @test_fabs_intrin(float %a) {1328; CHECK-LABEL: name: test_fabs_intrin1329; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01330; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FABS [[A]]1331; CHECK: $s0 = COPY [[RES]]1332 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.fabs.f32(float %a)1333 ret float %res1334}1335 1336declare float @llvm.copysign.f32(float, float)1337define float @test_fcopysign_intrin(float %a, float %b) {1338; CHECK-LABEL: name: test_fcopysign_intrin1339; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01340; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $s11341; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FCOPYSIGN [[A]], [[B]]1342; CHECK: $s0 = COPY [[RES]]1343 1344 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.copysign.f32(float %a, float %b)1345 ret float %res1346}1347 1348declare float @llvm.canonicalize.f32(float)1349define float @test_fcanonicalize_intrin(float %a) {1350; CHECK-LABEL: name: test_fcanonicalize_intrin1351; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01352; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FCANONICALIZE [[A]]1353; CHECK: $s0 = COPY [[RES]]1354 %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.canonicalize.f32(float %a)1355 ret float %res1356}1357 1358declare float @llvm.trunc.f32(float)1359define float @test_intrinsic_trunc(float %a) {1360; CHECK-LABEL: name: test_intrinsic_trunc1361; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01362; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]]1363; CHECK: $s0 = COPY [[RES]]1364 %res = call float @llvm.trunc.f32(float %a)1365 ret float %res1366}1367 1368declare float @llvm.round.f32(float)1369define float @test_intrinsic_round(float %a) {1370; CHECK-LABEL: name: test_intrinsic_round1371; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01372; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]]1373; CHECK: $s0 = COPY [[RES]]1374 %res = call float @llvm.round.f32(float %a)1375 ret float %res1376}1377 1378declare i32 @llvm.lrint.i32.f32(float)1379define i32 @test_intrinsic_lrint(float %a) {1380; CHECK-LABEL: name: test_intrinsic_lrint1381; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01382; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_LRINT [[A]]1383; CHECK: $w0 = COPY [[RES]]1384 %res = call i32 @llvm.lrint.i32.f32(float %a)1385 ret i32 %res1386}1387 1388declare i32 @llvm.llrint.i32.f32(float)1389define i32 @test_intrinsic_llrint(float %a) {1390; CHECK-LABEL: name: test_intrinsic_llrint1391; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s01392; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_LLRINT [[A]]1393; CHECK: $w0 = COPY [[RES]]1394 %res = call i32 @llvm.llrint.i32.f32(float %a)1395 ret i32 %res1396}1397 1398declare i32 @llvm.ctlz.i32(i32, i1)1399define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {1400; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef1401; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w01402; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTLZ [[A]]1403; CHECK: $w0 = COPY [[RES]]1404 %res = call i32 @llvm.ctlz.i32(i32 %a, i1 0)1405 ret i32 %res1406}1407 1408declare i32 @llvm.cttz.i32(i32, i1)1409define i32 @test_cttz_intrinsic_zero_undef(i32 %a) {1410; CHECK-LABEL: name: test_cttz_intrinsic_zero_undef1411; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w01412; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[A]]1413; CHECK: $w0 = COPY [[RES]]1414 %res = call i32 @llvm.cttz.i32(i32 %a, i1 1)1415 ret i32 %res1416}1417 1418declare i32 @llvm.ctpop.i32(i32)1419define i32 @test_ctpop_intrinsic(i32 %a) {1420; CHECK-LABEL: name: test_ctpop1421; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w01422; CHECK: [[RES:%[0-9]+]]:_(s32) = G_CTPOP [[A]]1423; CHECK: $w0 = COPY [[RES]]1424 %res = call i32 @llvm.ctpop.i32(i32 %a)1425 ret i32 %res1426}1427 1428declare i32 @llvm.bitreverse.i32(i32)1429define i32 @test_bitreverse_intrinsic(i32 %a) {1430; CHECK-LABEL: name: test_bitreverse1431; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w01432; CHECK: [[RES:%[0-9]+]]:_(s32) = G_BITREVERSE [[A]]1433; CHECK: $w0 = COPY [[RES]]1434 %res = call i32 @llvm.bitreverse.i32(i32 %a)1435 ret i32 %res1436}1437 1438declare i32 @llvm.fshl.i32(i32, i32, i32)1439define i32 @test_fshl_intrinsic(i32 %a, i32 %b, i32 %c) {1440; CHECK-LABEL: name: test_fshl_intrinsic1441; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w01442; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $w11443; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $w21444; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FSHL [[A]], [[B]], [[C]]1445; CHECK: $w0 = COPY [[RES]]1446 %res = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)1447 ret i32 %res1448}1449 1450declare i32 @llvm.fshr.i32(i32, i32, i32)1451define i32 @test_fshr_intrinsic(i32 %a, i32 %b, i32 %c) {1452; CHECK-LABEL: name: test_fshr_intrinsic1453; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $w01454; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $w11455; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $w21456; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FSHR [[A]], [[B]], [[C]]1457; CHECK: $w0 = COPY [[RES]]1458 %res = call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)1459 ret i32 %res1460}1461 1462declare void @llvm.lifetime.start.p0(i64, ptr)1463declare void @llvm.lifetime.end.p0(i64, ptr)1464define void @test_lifetime_intrin() {1465; CHECK-LABEL: name: test_lifetime_intrin1466; CHECK: RET_ReallyLR1467; O3-LABEL: name: test_lifetime_intrin1468; O3: {{%[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.0.slot1469; O3-NEXT: LIFETIME_START %stack.0.slot1470; O3-NEXT: G_STORE1471; O3-NEXT: LIFETIME_END %stack.0.slot1472; O3-NEXT: RET_ReallyLR1473 %slot = alloca i8, i32 41474 call void @llvm.lifetime.start.p0(i64 0, ptr %slot)1475 store volatile i8 10, ptr %slot1476 call void @llvm.lifetime.end.p0(i64 0, ptr %slot)1477 ret void1478}1479 1480define void @test_lifetime_intrin_optnone() optnone noinline {1481; CHECK-LABEL: name: test_lifetime_intrin_optnone1482; CHECK: RET_ReallyLR1483; O3-LABEL: name: test_lifetime_intrin_optnone1484; O3: {{%[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.0.slot1485; O3-NEXT: G_STORE1486; O3-NEXT: RET_ReallyLR1487 %slot = alloca i8, i32 41488 call void @llvm.lifetime.start.p0(i64 0, ptr %slot)1489 store volatile i8 10, ptr %slot1490 call void @llvm.lifetime.end.p0(i64 0, ptr %slot)1491 ret void1492}1493 1494define void @test_load_store_atomics(ptr %addr) {1495; CHECK-LABEL: name: test_load_store_atomics1496; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x01497; CHECK: [[V0:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load unordered (s8) from %ir.addr)1498; CHECK: G_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic (s8) into %ir.addr)1499; CHECK: [[V1:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load acquire (s8) from %ir.addr)1500; CHECK: G_STORE [[V1]](s8), [[ADDR]](p0) :: (store release (s8) into %ir.addr)1501; CHECK: [[V2:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst (s8) from %ir.addr)1502; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic (s8) into %ir.addr)1503 %v0 = load atomic i8, ptr %addr unordered, align 11504 store atomic i8 %v0, ptr %addr monotonic, align 11505 1506 %v1 = load atomic i8, ptr %addr acquire, align 11507 store atomic i8 %v1, ptr %addr release, align 11508 1509 %v2 = load atomic i8, ptr %addr syncscope("singlethread") seq_cst, align 11510 store atomic i8 %v2, ptr %addr syncscope("singlethread") monotonic, align 11511 1512 ret void1513}1514 1515define float @test_fneg_f32(float %x) {1516; CHECK-LABEL: name: test_fneg_f321517; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s01518; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]1519; CHECK: $s0 = COPY [[RES]](s32)1520 %neg = fneg float %x1521 ret float %neg1522}1523 1524define float @test_fneg_f32_fmf(float %x) {1525; CHECK-LABEL: name: test_fneg_f321526; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s01527; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]1528; CHECK: $s0 = COPY [[RES]](s32)1529 %neg = fneg fast float %x1530 ret float %neg1531}1532 1533define double @test_fneg_f64(double %x) {1534; CHECK-LABEL: name: test_fneg_f641535; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d01536; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]1537; CHECK: $d0 = COPY [[RES]](s64)1538 %neg = fneg double %x1539 ret double %neg1540}1541 1542define double @test_fneg_f64_fmf(double %x) {1543; CHECK-LABEL: name: test_fneg_f641544; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d01545; CHECK: [[RES:%[0-9]+]]:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]1546; CHECK: $d0 = COPY [[RES]](s64)1547 %neg = fneg fast double %x1548 ret double %neg1549}1550 1551define void @test_trivial_inlineasm() {1552; CHECK-LABEL: name: test_trivial_inlineasm1553; CHECK: INLINEASM &wibble, 11554; CHECK: INLINEASM &wibble, 01555 call void asm sideeffect "wibble", ""()1556 call void asm "wibble", ""()1557 ret void1558}1559 1560define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){1561; CHECK-LABEL: name: test_insertelement1562; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d01563; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w01564; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w11565; CHECK: [[IDX2:%[0-9]+]]:_(s64) = G_ZEXT [[IDX]]1566; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX2]](s64)1567; CHECK: $d0 = COPY [[RES]](<2 x s32>)1568 %res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx1569 ret <2 x i32> %res1570}1571 1572define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {1573; CHECK-LABEL: name: test_extractelement1574; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d01575; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w01576; CHECK: [[IDXEXT:%[0-9]+]]:_(s64) = G_ZEXT [[IDX]]1577; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDXEXT]](s64)1578; CHECK: $w0 = COPY [[RES]](s32)1579 %res = extractelement <2 x i32> %vec, i32 %idx1580 ret i32 %res1581}1582 1583define i32 @test_extractelement_const_idx(<2 x i32> %vec) {1584; CHECK-LABEL: name: test_extractelement1585; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d01586; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 11587; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)1588; CHECK: $w0 = COPY [[RES]](s32)1589 %res = extractelement <2 x i32> %vec, i32 11590 ret i32 %res1591}1592 1593define i32 @test_extractelement_const_idx_zext_i1(<2 x i32> %vec) {1594; CHECK-LABEL: name: test_extractelement1595; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d01596; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 11597; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)1598; CHECK: $w0 = COPY [[RES]](s32)1599 %res = extractelement <2 x i32> %vec, i1 true1600 ret i32 %res1601}1602 1603define i32 @test_extractelement_const_idx_zext_i8(<2 x i32> %vec) {1604; CHECK-LABEL: name: test_extractelement1605; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d01606; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 2551607; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s64)1608; CHECK: $w0 = COPY [[RES]](s32)1609 %res = extractelement <2 x i32> %vec, i8 2551610 ret i32 %res1611}1612 1613 1614define i32 @test_singleelementvector(i32 %elt){1615; CHECK-LABEL: name: test_singleelementvector1616; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w01617; CHECK-NOT: G_INSERT_VECTOR_ELT1618; CHECK-NOT: G_EXTRACT_VECTOR_ELT1619; CHECK: $w0 = COPY [[ELT]](s32)1620 %vec = insertelement <1 x i32> undef, i32 %elt, i32 01621 %res = extractelement <1 x i32> %vec, i32 01622 ret i32 %res1623}1624 1625define <2 x i32> @test_constantaggzerovector_v2i32() {1626; CHECK-LABEL: name: test_constantaggzerovector_v2i321627; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 01628; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ZERO]](s32), [[ZERO]](s32)1629; CHECK: $d0 = COPY [[VEC]](<2 x s32>)1630 ret <2 x i32> zeroinitializer1631}1632 1633define <2 x float> @test_constantaggzerovector_v2f32() {1634; CHECK-LABEL: name: test_constantaggzerovector_v2f321635; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+001636; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ZERO]](s32), [[ZERO]](s32)1637; CHECK: $d0 = COPY [[VEC]](<2 x s32>)1638 ret <2 x float> zeroinitializer1639}1640 1641define i32 @test_constantaggzerovector_v3i32() {1642; CHECK-LABEL: name: test_constantaggzerovector_v3i321643; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 01644; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32)1645; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)1646 %elt = extractelement <3 x i32> zeroinitializer, i32 11647 ret i32 %elt1648}1649 1650define <2 x i32> @test_constantdatavector_v2i32() {1651; CHECK-LABEL: name: test_constantdatavector_v2i321652; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11653; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 21654; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32)1655; CHECK: $d0 = COPY [[VEC]](<2 x s32>)1656 ret <2 x i32> <i32 1, i32 2>1657}1658 1659define i32 @test_constantdatavector_v3i32() {1660; CHECK-LABEL: name: test_constantdatavector_v3i321661; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11662; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 21663; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 31664; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32), [[C3]](s32)1665; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)1666 %elt = extractelement <3 x i32> <i32 1, i32 2, i32 3>, i32 11667 ret i32 %elt1668}1669 1670define <4 x i32> @test_constantdatavector_v4i32() {1671; CHECK-LABEL: name: test_constantdatavector_v4i321672; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11673; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 21674; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 31675; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 41676; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)1677; CHECK: $q0 = COPY [[VEC]](<4 x s32>)1678 ret <4 x i32> <i32 1, i32 2, i32 3, i32 4>1679}1680 1681define <2 x double> @test_constantdatavector_v2f64() {1682; CHECK-LABEL: name: test_constantdatavector_v2f641683; CHECK: [[FC1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+001684; CHECK: [[FC2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+001685; CHECK: [[VEC:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FC1]](s64), [[FC2]](s64)1686; CHECK: $q0 = COPY [[VEC]](<2 x s64>)1687 ret <2 x double> <double 1.0, double 2.0>1688}1689 1690define i32 @test_constantaggzerovector_v1s32(i32 %arg){1691; CHECK-LABEL: name: test_constantaggzerovector_v1s321692; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w01693; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 01694; CHECK-NOT: G_MERGE_VALUES1695; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C0]]1696; CHECK-NOT: G_MERGE_VALUES1697; CHECK: G_ADD [[ARG]], [[COPY]]1698 %vec = insertelement <1 x i32> undef, i32 %arg, i32 01699 %add = add <1 x i32> %vec, zeroinitializer1700 %res = extractelement <1 x i32> %add, i32 01701 ret i32 %res1702}1703 1704define i32 @test_constantdatavector_v1s32(i32 %arg){1705; CHECK-CV-LABEL: name: test_constantdatavector_v1s321706; CHECK-CV: [[ARG:%[0-9]+]]:_(s32) = COPY $w01707; CHECK-CV: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 11708; CHECK-CV-NOT: G_MERGE_VALUES1709; CHECK-CV: [[COPY:%[0-9]+]]:_(s32) = COPY [[C0]]1710; CHECK-CV-NOT: G_MERGE_VALUES1711; CHECK-CV: G_ADD [[ARG]], [[COPY]]1712;1713; CHECK-CI-LABEL: name: test_constantdatavector_v1s321714; CHECK-CI: [[ARG:%[0-9]+]]:_(s32) = COPY $w01715; CHECK-CI: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 11716; CHECK-CI-NOT: G_MERGE_VALUES1717; CHECK-CI: G_ADD [[ARG]], [[C0]]1718 %vec = insertelement <1 x i32> undef, i32 %arg, i32 01719 %add = add <1 x i32> %vec, <i32 1>1720 %res = extractelement <1 x i32> %add, i32 01721 ret i32 %res1722}1723 1724declare ghccc float @different_call_conv_target(float %x)1725define float @test_different_call_conv_target(float %x) {1726; CHECK-LABEL: name: test_different_call_conv1727; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s01728; CHECK: $s8 = COPY [[X]]1729; CHECK: BL @different_call_conv_target, csr_aarch64_noregs, implicit-def $lr, implicit $sp, implicit $s8, implicit-def $s01730 %res = call ghccc float @different_call_conv_target(float %x)1731 ret float %res1732}1733 1734define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {1735; CHECK-LABEL: name: test_shufflevector_s32_v2s321736; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w01737; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ARG]](s32), [[ARG]](s32)1738; CHECK: $d0 = COPY [[VEC]](<2 x s32>)1739 %vec = insertelement <1 x i32> undef, i32 %arg, i32 01740 %res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer1741 ret <2 x i32> %res1742}1743 1744define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {1745; CHECK-LABEL: name: test_shufflevector_v2s32_s321746; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d01747; CHECK: [[IDX:%[0-9]+]]:_(s64) = G_CONSTANT i64 11748; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ARG]](<2 x s32>), [[IDX]](s64)1749; CHECK: $w0 = COPY [[RES]](s32)1750 %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32> <i32 1>1751 %res = extractelement <1 x i32> %vec, i32 01752 ret i32 %res1753}1754 1755define <2 x i32> @test_shufflevector_v2s32_v2s32_undef(<2 x i32> %arg) {1756; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef1757; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d01758; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF1759; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(undef, undef)1760; CHECK: $d0 = COPY [[VEC]](<2 x s32>)1761 %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> undef1762 ret <2 x i32> %res1763}1764 1765define <2 x i32> @test_shufflevector_v2s32_v2s32_undef_0(<2 x i32> %arg) {1766; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef_01767; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d01768; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF1769; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(undef, 0)1770; CHECK: $d0 = COPY [[VEC]](<2 x s32>)1771 %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 undef, i32 0>1772 ret <2 x i32> %res1773}1774 1775define <2 x i32> @test_shufflevector_v2s32_v2s32_0_undef(<2 x i32> %arg) {1776; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_0_undef1777; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d01778; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF1779; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(0, undef)1780; CHECK: $d0 = COPY [[VEC]](<2 x s32>)1781 %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 0, i32 undef>1782 ret <2 x i32> %res1783}1784 1785define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {1786; CHECK-LABEL: name: test_shufflevector_v2s32_v3s321787; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d01788; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF1789; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(1, 0, 1)1790; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)1791 %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>1792 %res = extractelement <3 x i32> %vec, i32 01793 ret i32 %res1794}1795 1796define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {1797; CHECK-LABEL: name: test_shufflevector_v2s32_v4s321798; CHECK: [[ARG1:%[0-9]+]]:_(<2 x s32>) = COPY $d01799; CHECK: [[ARG2:%[0-9]+]]:_(<2 x s32>) = COPY $d11800; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], shufflemask(0, 1, 2, 3)1801; CHECK: $q0 = COPY [[VEC]](<4 x s32>)1802 %res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1803 ret <4 x i32> %res1804}1805 1806define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {1807; CHECK-LABEL: name: test_shufflevector_v4s32_v2s321808; CHECK: [[ARG:%[0-9]+]]:_(<4 x s32>) = COPY $q01809; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF1810; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], shufflemask(1, 3)1811; CHECK: $d0 = COPY [[VEC]](<2 x s32>)1812 %res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32> <i32 1, i32 3>1813 ret <2 x i32> %res1814}1815 1816 1817define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {1818; CHECK-LABEL: name: test_shufflevector_v8s8_v16s81819; CHECK: [[ARG1:%[0-9]+]]:_(<8 x s8>) = COPY $d01820; CHECK: [[ARG2:%[0-9]+]]:_(<8 x s8>) = COPY $d11821; CHECK: [[VEC:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], shufflemask(0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15)1822; CHECK: $q0 = COPY [[VEC]](<16 x s8>)1823 %res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>1824 ret <16 x i8> %res1825}1826 1827; CHECK-LABEL: test_constant_vector1828; CHECK: [[UNDEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF1829; CHECK: [[F:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C001830; CHECK: [[M:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)1831; CHECK: $d0 = COPY [[M]](<4 x s16>)1832define <4 x half> @test_constant_vector() {1833 ret <4 x half> <half undef, half undef, half undef, half 0xH3C00>1834}1835 1836define i32 @test_target_mem_intrinsic(ptr %addr) {1837; CHECK-LABEL: name: test_target_mem_intrinsic1838; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x01839; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load (s32) from %ir.addr)1840; CHECK: G_TRUNC [[VAL]](s64)1841 %val = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) %addr)1842 %trunc = trunc i64 %val to i321843 ret i32 %trunc1844}1845 1846declare i64 @llvm.aarch64.ldxr.p0(ptr) nounwind1847 1848%zerosize_type = type {}1849 1850define %zerosize_type @test_empty_load_store(ptr %ptr, %zerosize_type %in) noinline optnone {1851; CHECK-LABEL: name: test_empty_load_store1852; CHECK-NOT: G_STORE1853; CHECK-NOT: G_LOAD1854; CHECK: RET_ReallyLR1855entry:1856 store %zerosize_type undef, ptr undef, align 41857 %val = load %zerosize_type, ptr %ptr, align 41858 ret %zerosize_type %in1859}1860 1861 1862define i64 @test_phi_loop(i32 %n) {1863; CHECK-LABEL: name: test_phi_loop1864; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w01865; CHECK: [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11866; CHECK: [[CST2:%[0-9]+]]:_(s32) = G_CONSTANT i32 01867; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 01868; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 11869 1870; CHECK: [[PN1:%[0-9]+]]:_(s32) = G_PHI [[ARG1]](s32), %bb.1, [[SUB:%[0-9]+]](s32), %bb.21871; CHECK: [[PN2:%[0-9]+]]:_(s64) = G_PHI [[CST3]](s64), %bb.1, [[PN3:%[0-9]+]](s64), %bb.21872; CHECK: [[PN3]]:_(s64) = G_PHI [[CST4]](s64), %bb.1, [[ADD:%[0-9]+]](s64), %bb.21873; CHECK: [[ADD]]:_(s64) = G_ADD [[PN2]], [[PN3]]1874; CHECK: [[SUB]]:_(s32) = G_SUB [[PN1]], [[CST1]]1875; CHECK: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[PN1]](s32), [[CST2]]1876; CHECK: G_BRCOND [[CMP]](s1), %bb.31877; CHECK: G_BR %bb.21878 1879; CHECK: $x0 = COPY [[PN2]](s64)1880; CHECK: RET_ReallyLR implicit $x01881entry:1882 br label %loop1883 1884loop:1885 %counter = phi i32 [ %n, %entry ], [ %counter.dec, %loop ]1886 %elem = phi { i64, i64 } [ { i64 0, i64 1 }, %entry ], [ %updated, %loop ]1887 %prev = extractvalue { i64, i64 } %elem, 01888 %curr = extractvalue { i64, i64 } %elem, 11889 %next = add i64 %prev, %curr1890 %shifted = insertvalue { i64, i64 } %elem, i64 %curr, 01891 %updated = insertvalue { i64, i64 } %shifted, i64 %next, 11892 %counter.dec = sub i32 %counter, 11893 %cond = icmp sle i32 %counter, 01894 br i1 %cond, label %exit, label %loop1895 1896exit:1897 %res = extractvalue { i64, i64 } %elem, 01898 ret i64 %res1899}1900 1901define void @test_phi_diamond(ptr %a.ptr, ptr %b.ptr, i1 %selector, ptr %dst) {1902; CHECK-LABEL: name: test_phi_diamond1903; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY $x01904; CHECK: [[ARG2:%[0-9]+]]:_(p0) = COPY $x11905; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY $w21906; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[ARG3]]1907; CHECK: [[ARG4:%[0-9]+]]:_(p0) = COPY $x31908; CHECK: [[TRUNCASSERT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[TRUNC8]], 11909; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNCASSERT]]1910; CHECK: G_BRCOND [[TRUNC]](s1), %bb.21911; CHECK: G_BR %bb.31912 1913; CHECK: [[LD1:%[0-9]+]]:_(s8) = G_LOAD [[ARG1]](p0) :: (load (s8) from %ir.a.ptr, align 4)1914; CHECK: [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 21915; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST1]](s64)1916; CHECK: [[LD2:%[0-9]+]]:_(s16) = G_LOAD [[GEP1]](p0) :: (load (s16) from %ir.a.ptr + 2)1917; CHECK: [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 41918; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG1]], [[CST2]](s64)1919; CHECK: [[LD3:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load (s32) from %ir.a.ptr + 4)1920; CHECK: G_BR %bb.41921 1922; CHECK: [[LD4:%[0-9]+]]:_(s8) = G_LOAD [[ARG2]](p0) :: (load (s8) from %ir.b.ptr, align 4)1923; CHECK: [[CST3:%[0-9]+]]:_(s64) = G_CONSTANT i64 21924; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST3]](s64)1925; CHECK: [[LD5:%[0-9]+]]:_(s16) = G_LOAD [[GEP3]](p0) :: (load (s16) from %ir.b.ptr + 2)1926; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 41927; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG2]], [[CST4]](s64)1928; CHECK: [[LD6:%[0-9]+]]:_(s32) = G_LOAD [[GEP4]](p0) :: (load (s32) from %ir.b.ptr + 4)1929 1930; CHECK: [[PN1:%[0-9]+]]:_(s8) = G_PHI [[LD1]](s8), %bb.2, [[LD4]](s8), %bb.31931; CHECK: [[PN2:%[0-9]+]]:_(s16) = G_PHI [[LD2]](s16), %bb.2, [[LD5]](s16), %bb.31932; CHECK: [[PN3:%[0-9]+]]:_(s32) = G_PHI [[LD3]](s32), %bb.2, [[LD6]](s32), %bb.31933; CHECK: G_STORE [[PN1]](s8), [[ARG4]](p0) :: (store (s8) into %ir.dst, align 4)1934; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 21935; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST5]](s64)1936; CHECK: G_STORE [[PN2]](s16), [[GEP5]](p0) :: (store (s16) into %ir.dst + 2)1937; CHECK: [[CST6:%[0-9]+]]:_(s64) = G_CONSTANT i64 41938; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[ARG4]], [[CST6]](s64)1939; CHECK: G_STORE [[PN3]](s32), [[GEP6]](p0) :: (store (s32) into %ir.dst + 4)1940; CHECK: RET_ReallyLR1941 1942entry:1943 br i1 %selector, label %store.a, label %store.b1944 1945store.a:1946 %a = load { i8, i16, i32 }, ptr %a.ptr1947 br label %join1948 1949store.b:1950 %b = load { i8, i16, i32 }, ptr %b.ptr1951 br label %join1952 1953join:1954 %v = phi { i8, i16, i32 } [ %a, %store.a ], [ %b, %store.b ]1955 store { i8, i16, i32 } %v, ptr %dst1956 ret void1957}1958 1959%agg.inner.inner = type {i64, i64}1960%agg.inner = type {i16, i8, %agg.inner.inner }1961%agg.nested = type {i32, i32, %agg.inner, i32}1962 1963define void @test_nested_aggregate_const(ptr %ptr) {1964; CHECK-LABEL: name: test_nested_aggregate_const1965; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY $x01966; CHECK: [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11967; CHECK: [[CST2:%[0-9]+]]:_(s16) = G_CONSTANT i16 21968; CHECK: [[CST3:%[0-9]+]]:_(s8) = G_CONSTANT i8 31969; CHECK: [[CST4:%[0-9]+]]:_(s64) = G_CONSTANT i64 51970; CHECK: [[CST5:%[0-9]+]]:_(s64) = G_CONSTANT i64 81971; CHECK: [[CST6:%[0-9]+]]:_(s32) = G_CONSTANT i32 131972; CHECK: G_STORE [[CST1]](s32), [[BASE]](p0) :: (store (s32) into %ir.ptr, align 8)1973; CHECK: [[CST7:%[0-9]+]]:_(s64) = G_CONSTANT i64 41974; CHECK: [[GEP1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST7]](s64)1975; CHECK: G_STORE [[CST1]](s32), [[GEP1]](p0) :: (store (s32) into %ir.ptr + 4)1976; CHECK: [[CST8:%[0-9]+]]:_(s64) = G_CONSTANT i64 81977; CHECK: [[GEP2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST8]](s64)1978; CHECK: G_STORE [[CST2]](s16), [[GEP2]](p0) :: (store (s16) into %ir.ptr + 8, align 8)1979; CHECK: [[CST9:%[0-9]+]]:_(s64) = G_CONSTANT i64 101980; CHECK: [[GEP3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST9]](s64)1981; CHECK: G_STORE [[CST3]](s8), [[GEP3]](p0) :: (store (s8) into %ir.ptr + 10, align 2)1982; CHECK: [[CST10:%[0-9]+]]:_(s64) = G_CONSTANT i64 161983; CHECK: [[GEP4:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST10]](s64)1984; CHECK: G_STORE [[CST4]](s64), [[GEP4]](p0) :: (store (s64) into %ir.ptr + 16)1985; CHECK: [[CST11:%[0-9]+]]:_(s64) = G_CONSTANT i64 241986; CHECK: [[GEP5:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST11]](s64)1987; CHECK: G_STORE [[CST5]](s64), [[GEP5]](p0) :: (store (s64) into %ir.ptr + 24)1988; CHECK: [[CST12:%[0-9]+]]:_(s64) = G_CONSTANT i64 321989; CHECK: [[GEP6:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[BASE]], [[CST12]](s64)1990; CHECK: G_STORE [[CST6]](s32), [[GEP6]](p0) :: (store (s32) into %ir.ptr + 32, align 8)1991 store %agg.nested { i32 1, i32 1, %agg.inner { i16 2, i8 3, %agg.inner.inner {i64 5, i64 8} }, i32 13}, ptr %ptr1992 ret void1993}1994 1995define i1 @return_i1_zext() {1996; AAPCS ABI says that booleans can only be 1 or 0, so we need to zero-extend.1997; CHECK-LABEL: name: return_i1_zext1998; CHECK: [[CST:%[0-9]+]]:_(s1) = G_CONSTANT i1 true1999; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[CST]](s1)2000; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)2001; CHECK: $w0 = COPY [[ANYEXT]](s32)2002; CHECK: RET_ReallyLR implicit $w02003 ret i1 true2004}2005 2006; Try one cmpxchg2007define i32 @test_atomic_cmpxchg_1(ptr %addr) {2008; CHECK-LABEL: name: test_atomic_cmpxchg_12009; CHECK: bb.1.entry:2010; CHECK-NEXT: successors: %bb.{{[^)]+}}2011; CHECK-NEXT: liveins: $x02012; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02013; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 02014; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12015; CHECK: bb.2.repeat:2016; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})2017; CHECK: [[OLDVALRES:%[0-9]+]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (s32) on %ir.addr)2018; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.32019; CHECK-NEXT: G_BR %bb.22020; CHECK: bb.3.done:2021entry:2022 br label %repeat2023repeat:2024 %val_success = cmpxchg ptr %addr, i32 0, i32 1 monotonic monotonic2025 %value_loaded = extractvalue { i32, i1 } %val_success, 02026 %success = extractvalue { i32, i1 } %val_success, 12027 br i1 %success, label %done, label %repeat2028done:2029 ret i32 %value_loaded2030}2031 2032; Try one cmpxchg2033define i32 @test_weak_atomic_cmpxchg_1(ptr %addr) {2034; CHECK-LABEL: name: test_weak_atomic_cmpxchg_12035; CHECK: bb.1.entry:2036; CHECK-NEXT: successors: %bb.{{[^)]+}}2037; CHECK-NEXT: liveins: $x02038; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02039; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 02040; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12041; CHECK: bb.2.repeat:2042; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})2043; CHECK: [[OLDVALRES:%[0-9]+]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store monotonic monotonic (s32) on %ir.addr)2044; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.32045; CHECK-NEXT: G_BR %bb.22046; CHECK: bb.3.done:2047entry:2048 br label %repeat2049repeat:2050 %val_success = cmpxchg weak ptr %addr, i32 0, i32 1 monotonic monotonic2051 %value_loaded = extractvalue { i32, i1 } %val_success, 02052 %success = extractvalue { i32, i1 } %val_success, 12053 br i1 %success, label %done, label %repeat2054done:2055 ret i32 %value_loaded2056}2057 2058; Try one cmpxchg with a small type and high atomic ordering.2059define i16 @test_atomic_cmpxchg_2(ptr %addr) {2060; CHECK-LABEL: name: test_atomic_cmpxchg_22061; CHECK: bb.1.entry:2062; CHECK-NEXT: successors: %bb.2({{[^)]+}})2063; CHECK-NEXT: liveins: $x02064; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02065; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s16) = G_CONSTANT i16 02066; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s16) = G_CONSTANT i16 12067; CHECK: bb.2.repeat:2068; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})2069; CHECK: [[OLDVALRES:%[0-9]+]]:_(s16), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (s16) on %ir.addr)2070; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.32071; CHECK-NEXT: G_BR %bb.22072; CHECK: bb.3.done:2073entry:2074 br label %repeat2075repeat:2076 %val_success = cmpxchg ptr %addr, i16 0, i16 1 seq_cst seq_cst2077 %value_loaded = extractvalue { i16, i1 } %val_success, 02078 %success = extractvalue { i16, i1 } %val_success, 12079 br i1 %success, label %done, label %repeat2080done:2081 ret i16 %value_loaded2082}2083 2084; Try one cmpxchg where the success order and failure order differ.2085define i64 @test_atomic_cmpxchg_3(ptr %addr) {2086; CHECK-LABEL: name: test_atomic_cmpxchg_32087; CHECK: bb.1.entry:2088; CHECK-NEXT: successors: %bb.2({{[^)]+}})2089; CHECK-NEXT: liveins: $x02090; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02091; CHECK-NEXT: [[OLDVAL:%[0-9]+]]:_(s64) = G_CONSTANT i64 02092; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s64) = G_CONSTANT i64 12093; CHECK: bb.2.repeat:2094; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})2095; CHECK: [[OLDVALRES:%[0-9]+]]:_(s64), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst acquire (s64) on %ir.addr)2096; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.32097; CHECK-NEXT: G_BR %bb.22098; CHECK: bb.3.done:2099entry:2100 br label %repeat2101repeat:2102 %val_success = cmpxchg ptr %addr, i64 0, i64 1 seq_cst acquire2103 %value_loaded = extractvalue { i64, i1 } %val_success, 02104 %success = extractvalue { i64, i1 } %val_success, 12105 br i1 %success, label %done, label %repeat2106done:2107 ret i64 %value_loaded2108}2109 2110; Try a monotonic atomicrmw xchg2111define i32 @test_atomicrmw_xchg(ptr %addr) {2112; CHECK-LABEL: name: test_atomicrmw_xchg2113; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2114; CHECK-NEXT: liveins: $x02115; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02116; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12117; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_XCHG [[ADDR]](p0), [[VAL]] :: (load store monotonic (s32) on %ir.addr)2118 %oldval = atomicrmw xchg ptr %addr, i32 1 monotonic2119 ret i32 %oldval2120}2121 2122; Try an acquire atomicrmw add2123define i32 @test_atomicrmw_add(ptr %addr) {2124; CHECK-LABEL: name: test_atomicrmw_add2125; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2126; CHECK-NEXT: liveins: $x02127; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02128; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12129; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[ADDR]](p0), [[VAL]] :: (load store acquire (s32) on %ir.addr)2130 %oldval = atomicrmw add ptr %addr, i32 1 acquire2131 ret i32 %oldval2132}2133 2134; Try a release atomicrmw sub2135define i32 @test_atomicrmw_sub(ptr %addr) {2136; CHECK-LABEL: name: test_atomicrmw_sub2137; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2138; CHECK-NEXT: liveins: $x02139; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02140; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12141; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_SUB [[ADDR]](p0), [[VAL]] :: (load store release (s32) on %ir.addr)2142 %oldval = atomicrmw sub ptr %addr, i32 1 release2143 ret i32 %oldval2144}2145 2146; Try an acq_rel atomicrmw and2147define i32 @test_atomicrmw_and(ptr %addr) {2148; CHECK-LABEL: name: test_atomicrmw_and2149; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2150; CHECK-NEXT: liveins: $x02151; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02152; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12153; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_AND [[ADDR]](p0), [[VAL]] :: (load store acq_rel (s32) on %ir.addr)2154 %oldval = atomicrmw and ptr %addr, i32 1 acq_rel2155 ret i32 %oldval2156}2157 2158; Try an seq_cst atomicrmw nand. NAND isn't supported by LSE, so it2159; expands to G_ATOMIC_CMPXCHG_WITH_SUCCESS.2160define i32 @test_atomicrmw_nand(ptr %addr) {2161; CHECK-LABEL: name: test_atomicrmw_nand2162; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2163; CHECK-NEXT: successors: %bb.2(0x80000000)2164; CHECK-NEXT: liveins: $x02165; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02166; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12167; CHECK-NEXT: [[NEG1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -12168; CHECK-NEXT: [[OLDVALSTART:%[0-9]+]]:_(s32) = G_LOAD [[ADDR]](p0) :: (load (s32) from %ir.addr)2169; CHECK: bb.2.atomicrmw.start:2170; CHECK-NEXT: successors: %bb.3({{[^)]+}}), %bb.2({{[^)]+}})2171; CHECK: [[OLDVAL:%[0-9]+]]:_(s32) = G_PHI [[OLDVALSTART]](s32), %bb.1, [[OLDVALRES:%[0-9]+]](s32), %bb.22172; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[OLDVAL]], [[VAL]]2173; CHECK-NEXT: [[NEWVAL:%[0-9]+]]:_(s32) = G_XOR [[AND]], [[NEG1]]2174; CHECK: [[OLDVALRES]]:_(s32), [[SUCCESS:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[ADDR]](p0), [[OLDVAL]], [[NEWVAL]] :: (load store seq_cst seq_cst (s32) on %ir.addr)2175; CHECK-NEXT: G_BRCOND [[SUCCESS]](s1), %bb.32176; CHECK-NEXT: G_BR %bb.22177; CHECK: bb.3.atomicrmw.end:2178 %oldval = atomicrmw nand ptr %addr, i32 1 seq_cst2179 ret i32 %oldval2180}2181 2182; Try an seq_cst atomicrmw or2183define i32 @test_atomicrmw_or(ptr %addr) {2184; CHECK-LABEL: name: test_atomicrmw_or2185; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2186; CHECK-NEXT: liveins: $x02187; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02188; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12189; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_OR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)2190 %oldval = atomicrmw or ptr %addr, i32 1 seq_cst2191 ret i32 %oldval2192}2193 2194; Try an seq_cst atomicrmw xor2195define i32 @test_atomicrmw_xor(ptr %addr) {2196; CHECK-LABEL: name: test_atomicrmw_xor2197; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2198; CHECK-NEXT: liveins: $x02199; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02200; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12201; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_XOR [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)2202 %oldval = atomicrmw xor ptr %addr, i32 1 seq_cst2203 ret i32 %oldval2204}2205 2206; Try an seq_cst atomicrmw min2207define i32 @test_atomicrmw_min(ptr %addr) {2208; CHECK-LABEL: name: test_atomicrmw_min2209; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2210; CHECK-NEXT: liveins: $x02211; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02212; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12213; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_MIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)2214 %oldval = atomicrmw min ptr %addr, i32 1 seq_cst2215 ret i32 %oldval2216}2217 2218; Try an seq_cst atomicrmw max2219define i32 @test_atomicrmw_max(ptr %addr) {2220; CHECK-LABEL: name: test_atomicrmw_max2221; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2222; CHECK-NEXT: liveins: $x02223; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02224; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12225; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_MAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)2226 %oldval = atomicrmw max ptr %addr, i32 1 seq_cst2227 ret i32 %oldval2228}2229 2230; Try an seq_cst atomicrmw unsigned min2231define i32 @test_atomicrmw_umin(ptr %addr) {2232; CHECK-LABEL: name: test_atomicrmw_umin2233; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2234; CHECK-NEXT: liveins: $x02235; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02236; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12237; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_UMIN [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)2238 %oldval = atomicrmw umin ptr %addr, i32 1 seq_cst2239 ret i32 %oldval2240}2241 2242; Try an seq_cst atomicrmw unsigned max2243define i32 @test_atomicrmw_umax(ptr %addr) {2244; CHECK-LABEL: name: test_atomicrmw_umax2245; CHECK: bb.1 (%ir-block.{{[0-9]+}}):2246; CHECK-NEXT: liveins: $x02247; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x02248; CHECK-NEXT: [[VAL:%[0-9]+]]:_(s32) = G_CONSTANT i32 12249; CHECK-NEXT: [[OLDVALRES:%[0-9]+]]:_(s32) = G_ATOMICRMW_UMAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst (s32) on %ir.addr)2250 %oldval = atomicrmw umax ptr %addr, i32 1 seq_cst2251 ret i32 %oldval2252}2253 2254@addr = global ptr null2255 2256define void @test_blockaddress() {2257; CHECK-LABEL: name: test_blockaddress2258; CHECK: [[BADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)2259; CHECK: G_STORE [[BADDR]](p0)2260 store ptr blockaddress(@test_blockaddress, %block), ptr @addr2261 indirectbr ptr blockaddress(@test_blockaddress, %block), [label %block]2262block:2263 ret void2264}2265 2266%t = type { i32 }2267declare ptr @llvm.invariant.start.p0(i64, ptr nocapture) readonly nounwind2268declare void @llvm.invariant.end.p0(ptr, i64, ptr nocapture) nounwind2269define void @test_invariant_intrin() {2270; CHECK-LABEL: name: test_invariant_intrin2271; CHECK: %{{[0-9]+}}:_(p0) = G_IMPLICIT_DEF2272; CHECK-NEXT: RET_ReallyLR2273 %x = alloca %t2274 %inv = call ptr @llvm.invariant.start.p0(i64 8, ptr %x)2275 call void @llvm.invariant.end.p0(ptr %inv, i64 8, ptr %x)2276 ret void2277}2278 2279declare float @llvm.ceil.f32(float)2280define float @test_ceil_f32(float %x) {2281 ; CHECK-LABEL: name: test_ceil_f322282 ; CHECK: %{{[0-9]+}}:_(s32) = G_FCEIL %{{[0-9]+}}2283 %y = call float @llvm.ceil.f32(float %x)2284 ret float %y2285}2286 2287declare double @llvm.ceil.f64(double)2288define double @test_ceil_f64(double %x) {2289 ; CHECK-LABEL: name: test_ceil_f642290 ; CHECK: %{{[0-9]+}}:_(s64) = G_FCEIL %{{[0-9]+}}2291 %y = call double @llvm.ceil.f64(double %x)2292 ret double %y2293}2294 2295declare <2 x float> @llvm.ceil.v2f32(<2 x float>)2296define <2 x float> @test_ceil_v2f32(<2 x float> %x) {2297 ; CHECK-LABEL: name: test_ceil_v2f322298 ; CHECK: %{{[0-9]+}}:_(<2 x s32>) = G_FCEIL %{{[0-9]+}}2299 %y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x)2300 ret <2 x float> %y2301}2302 2303declare <4 x float> @llvm.ceil.v4f32(<4 x float>)2304define <4 x float> @test_ceil_v4f32(<4 x float> %x) {2305 ; CHECK-LABEL: name: test_ceil_v4f322306 ; CHECK: %{{[0-9]+}}:_(<4 x s32>) = G_FCEIL %{{[0-9]+}}2307 ; SELECT: %{{[0-9]+}}:fpr128 = FRINTPv4f32 %{{[0-9]+}}2308 %y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x)2309 ret <4 x float> %y2310}2311 2312declare <2 x double> @llvm.ceil.v2f64(<2 x double>)2313define <2 x double> @test_ceil_v2f64(<2 x double> %x) {2314 ; CHECK-LABEL: name: test_ceil_v2f642315 ; CHECK: %{{[0-9]+}}:_(<2 x s64>) = G_FCEIL %{{[0-9]+}}2316 %y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x)2317 ret <2 x double> %y2318}2319 2320declare float @llvm.cos.f32(float)2321define float @test_cos_f32(float %x) {2322 ; CHECK-LABEL: name: test_cos_f322323 ; CHECK: %{{[0-9]+}}:_(s32) = G_FCOS %{{[0-9]+}}2324 %y = call float @llvm.cos.f32(float %x)2325 ret float %y2326}2327 2328declare float @llvm.sin.f32(float)2329define float @test_sin_f32(float %x) {2330 ; CHECK-LABEL: name: test_sin_f322331 ; CHECK: %{{[0-9]+}}:_(s32) = G_FSIN %{{[0-9]+}}2332 %y = call float @llvm.sin.f32(float %x)2333 ret float %y2334}2335 2336declare float @llvm.tan.f32(float)2337define float @test_tan_f32(float %x) {2338 ; CHECK-LABEL: name: test_tan_f322339 ; CHECK: %{{[0-9]+}}:_(s32) = G_FTAN %{{[0-9]+}}2340 %y = call float @llvm.tan.f32(float %x)2341 ret float %y2342}2343 2344declare float @llvm.acos.f32(float)2345define float @test_acos_f32(float %x) {2346 ; CHECK-LABEL: name: test_acos_f322347 ; CHECK: %{{[0-9]+}}:_(s32) = G_FACOS %{{[0-9]+}}2348 %y = call float @llvm.acos.f32(float %x)2349 ret float %y2350}2351 2352declare float @llvm.asin.f32(float)2353define float @test_asin_f32(float %x) {2354 ; CHECK-LABEL: name: test_asin_f322355 ; CHECK: %{{[0-9]+}}:_(s32) = G_FASIN %{{[0-9]+}}2356 %y = call float @llvm.asin.f32(float %x)2357 ret float %y2358}2359 2360declare float @llvm.atan.f32(float)2361define float @test_atan_f32(float %x) {2362 ; CHECK-LABEL: name: test_atan_f322363 ; CHECK: %{{[0-9]+}}:_(s32) = G_FATAN %{{[0-9]+}}2364 %y = call float @llvm.atan.f32(float %x)2365 ret float %y2366}2367 2368declare float @llvm.atan2.f32(float, float)2369define float @test_atan2_f32(float %x, float %y) {2370 ; CHECK-LABEL: name: test_atan2_f322371 ; CHECK: %{{[0-9]+}}:_(s32) = G_FATAN2 %{{[0-9]+}}2372 %z = call float @llvm.atan2.f32(float %x, float %y)2373 ret float %z2374}2375 2376declare float @llvm.cosh.f32(float)2377define float @test_cosh_f32(float %x) {2378 ; CHECK-LABEL: name: test_cosh_f322379 ; CHECK: %{{[0-9]+}}:_(s32) = G_FCOSH %{{[0-9]+}}2380 %y = call float @llvm.cosh.f32(float %x)2381 ret float %y2382}2383 2384declare float @llvm.sinh.f32(float)2385define float @test_sinh_f32(float %x) {2386 ; CHECK-LABEL: name: test_sinh_f322387 ; CHECK: %{{[0-9]+}}:_(s32) = G_FSINH %{{[0-9]+}}2388 %y = call float @llvm.sinh.f32(float %x)2389 ret float %y2390}2391 2392declare float @llvm.tanh.f32(float)2393define float @test_tanh_f32(float %x) {2394 ; CHECK-LABEL: name: test_tanh_f322395 ; CHECK: %{{[0-9]+}}:_(s32) = G_FTANH %{{[0-9]+}}2396 %y = call float @llvm.tanh.f32(float %x)2397 ret float %y2398}2399 2400declare float @llvm.sqrt.f32(float)2401define float @test_sqrt_f32(float %x) {2402 ; CHECK-LABEL: name: test_sqrt_f322403 ; CHECK: %{{[0-9]+}}:_(s32) = G_FSQRT %{{[0-9]+}}2404 %y = call float @llvm.sqrt.f32(float %x)2405 ret float %y2406}2407 2408declare float @llvm.floor.f32(float)2409define float @test_floor_f32(float %x) {2410 ; CHECK-LABEL: name: test_floor_f322411 ; CHECK: %{{[0-9]+}}:_(s32) = G_FFLOOR %{{[0-9]+}}2412 %y = call float @llvm.floor.f32(float %x)2413 ret float %y2414}2415 2416declare float @llvm.nearbyint.f32(float)2417define float @test_nearbyint_f32(float %x) {2418 ; CHECK-LABEL: name: test_nearbyint_f322419 ; CHECK: %{{[0-9]+}}:_(s32) = G_FNEARBYINT %{{[0-9]+}}2420 %y = call float @llvm.nearbyint.f32(float %x)2421 ret float %y2422}2423 2424; CHECK-LABEL: name: test_llvm.aarch64.neon.ld3.v4i32.p0i322425; CHECK: %1:_(<4 x s32>), %2:_(<4 x s32>), %3:_(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld3), %0(p0) :: (load (s384) from %ir.ptr, align 64)2426define void @test_llvm.aarch64.neon.ld3.v4i32.p0i32(ptr %ptr) {2427 %arst = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %ptr)2428 ret void2429}2430 2431declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr) #32432 2433define void @test_i1_arg_zext(ptr %f) {2434; CHECK-LABEL: name: test_i1_arg_zext2435; CHECK: [[I1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true2436; CHECK: [[ZEXT0:%[0-9]+]]:_(s8) = G_ZEXT [[I1]](s1)2437; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT0]](s8)2438; CHECK: $w0 = COPY [[ZEXT1]](s32)2439 call void %f(i1 true)2440 ret void2441}2442 2443declare ptr @llvm.stacksave()2444declare void @llvm.stackrestore(ptr)2445define void @test_stacksaverestore() {2446 ; CHECK-LABEL: name: test_stacksaverestore2447 ; CHECK: [[SAVE:%[0-9]+]]:_(p0) = G_STACKSAVE2448 ; CHECK-NEXT: G_STACKRESTORE [[SAVE]]2449 ; CHECK-NEXT: RET_ReallyLR2450 %sp = call ptr @llvm.stacksave()2451 call void @llvm.stackrestore(ptr %sp)2452 ret void2453}2454 2455declare float @llvm.rint.f32(float)2456define float @test_rint_f32(float %x) {2457 ; CHECK-LABEL: name: test_rint_f322458 ; CHECK: %{{[0-9]+}}:_(s32) = G_FRINT %{{[0-9]+}}2459 %y = call float @llvm.rint.f32(float %x)2460 ret float %y2461}2462 2463declare void @llvm.assume(i1)2464define void @test_assume(i1 %x) {2465 ; CHECK-LABEL: name: test_assume2466 ; CHECK-NOT: llvm.assume2467 ; CHECK: RET_ReallyLR2468 call void @llvm.assume(i1 %x)2469 ret void2470}2471 2472declare void @llvm.experimental.noalias.scope.decl(metadata)2473define void @test.llvm.noalias.scope.decl(ptr %P, ptr %Q) nounwind ssp {2474 tail call void @llvm.experimental.noalias.scope.decl(metadata !3)2475 ; CHECK-LABEL: name: test.llvm.noalias.scope.decl2476 ; CHECK-NOT: llvm.experimental.noalias.scope.decl2477 ; CHECK: RET_ReallyLR2478 ret void2479}2480 2481!3 = !{ !4 }2482!4 = distinct !{ !4, !5, !"test1: var" }2483!5 = distinct !{ !5, !"test1" }2484 2485 2486declare void @llvm.sideeffect()2487define void @test_sideeffect() {2488 ; CHECK-LABEL: name: test_sideeffect2489 ; CHECK-NOT: llvm.sideeffect2490 ; CHECK: RET_ReallyLR2491 call void @llvm.sideeffect()2492 ret void2493}2494 2495declare void @llvm.var.annotation(ptr, ptr, ptr, i32, ptr)2496define void @test_var_annotation(ptr, ptr, ptr, i32) {2497 ; CHECK-LABEL: name: test_var_annotation2498 ; CHECK-NOT: llvm.var.annotation2499 ; CHECK: RET_ReallyLR2500 call void @llvm.var.annotation(ptr %0, ptr %1, ptr %2, i32 %3, ptr null)2501 ret void2502}2503 2504declare i64 @llvm.readcyclecounter()2505define i64 @test_readcyclecounter() {2506 ; CHECK-LABEL: name: test_readcyclecounter2507 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_READCYCLECOUNTER{{$}}2508 ; CHECK-NEXT: $x0 = COPY [[RES]]2509 ; CHECK-NEXT: RET_ReallyLR implicit $x02510 %res = call i64 @llvm.readcyclecounter()2511 ret i64 %res2512}2513 2514define i64 @test_freeze(i64 %a) {2515 ; CHECK-LABEL: name: test_freeze2516 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x02517 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]2518 ; CHECK-NEXT: $x0 = COPY [[RES]]2519 ; CHECK-NEXT: RET_ReallyLR implicit $x02520 %res = freeze i64 %a2521 ret i64 %res2522}2523 2524define {i8, i32} @test_freeze_struct(ptr %addr) {2525 ; CHECK-LABEL: name: test_freeze_struct2526 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x02527 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0)2528 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42529 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]]2530 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0)2531 ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[LOAD]]2532 ; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(s32) = G_FREEZE [[LOAD1]]2533 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE]]2534 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]]2535 ; CHECK-NEXT: $w1 = COPY [[FREEZE1]]2536 ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w12537 %load = load { i8, i32 }, ptr %addr2538 %res = freeze {i8, i32} %load2539 ret {i8, i32} %res2540}2541 2542!0 = !{ i64 0, i64 2 }2543 2544declare i64 @llvm.lround.i64.f32(float) nounwind readnone2545define i64 @lround(float %x) {2546 ; CHECK-LABEL: name: lround2547 ; CHECK: bb.1 (%ir-block.0):2548 ; CHECK: liveins: $s02549 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s02550 ; CHECK: [[LROUND:%[0-9]+]]:_(s64) = G_LROUND [[COPY]](s32)2551 ; CHECK: $x0 = COPY [[LROUND]](s64)2552 ; CHECK: RET_ReallyLR implicit $x02553 %lround = tail call i64 @llvm.lround.i64.f32(float %x)2554 ret i64 %lround2555}2556 2557declare i64 @llvm.llround.i64.f32(float) nounwind readnone2558define i64 @llround(float %x) {2559 ; CHECK-LABEL: name: llround2560 ; CHECK: bb.1 (%ir-block.0):2561 ; CHECK: liveins: $s02562 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s02563 ; CHECK: [[LLROUND:%[0-9]+]]:_(s64) = G_LLROUND [[COPY]](s32)2564 ; CHECK: $x0 = COPY [[LLROUND]](s64)2565 ; CHECK: RET_ReallyLR implicit $x02566 %lround = tail call i64 @llvm.llround.i64.f32(float %x)2567 ret i64 %lround2568}2569