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1# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=regbankselect %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=FAST2# RUN: llc -O0 -debugify-and-strip-all-safe -run-pass=regbankselect %s -regbankselect-greedy -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY3 4--- |5 ; ModuleID = 'generic-virtual-registers-type-error.mir'6 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"7 target triple = "aarch64--"8 define void @defaultMapping() {9 entry:10 ret void11 }12 define void @defaultMappingVector() {13 entry:14 ret void15 }16 define void @defaultMapping1Repair() {17 entry:18 ret void19 }20 define void @defaultMapping2Repairs() {21 entry:22 ret void23 }24 define void @defaultMappingDefRepair() {25 entry:26 ret void27 }28 define void @phiPropagation(ptr %src, ptr %dst, i1 %cond) {29 entry:30 %srcVal = load i32, ptr %src31 br i1 %cond, label %end, label %then32 then:33 %res = add i32 %srcVal, 3634 br label %end35 end:36 %toStore = phi i32 [ %srcVal, %entry ], [ %res, %then ]37 store i32 %toStore, ptr %dst38 ret void39 }40 define void @defaultMappingUseRepairPhysReg() {41 entry:42 ret void43 }44 define void @defaultMappingDefRepairPhysReg() {45 entry:46 ret void47 }48 define void @greedyMappingOr() {49 entry:50 ret void51 }52 define void @greedyMappingOrWithConstraints() {53 entry:54 ret void55 }56 57 define void @ignoreTargetSpecificInst() { ret void }58 59 define void @regBankSelected_property() { ret void }60 61 define void @bitcast_s32_gpr() { ret void }62 define void @bitcast_s32_fpr() { ret void }63 define void @bitcast_s32_gpr_fpr() { ret void }64 define void @bitcast_s32_fpr_gpr() { ret void }65 define void @bitcast_s64_gpr() { ret void }66 define void @bitcast_s64_fpr() { ret void }67 define void @bitcast_s64_gpr_fpr() { ret void }68 define void @bitcast_s64_fpr_gpr() { ret void }69 define void @bitcast_s128() { ret void }70 define void @copy_s128() { ret void }71 define void @copy_s128_from_load() { ret void }72 define void @copy_fp16() { ret void }73 74 define i64 @greedyWithChainOfComputation(i64 %arg1, ptr %addr) {75 %varg1 = bitcast i64 %arg1 to <2 x i32>76 %varg2 = load <2 x i32>, ptr %addr77 %vres = or <2 x i32> %varg1, %varg278 %res = bitcast <2 x i32> %vres to i6479 ret i64 %res80 }81 82 define i64 @floatingPointLoad(i64 %arg1, ptr %addr) {83 %varg1 = bitcast i64 %arg1 to double84 %varg2 = load double, ptr %addr85 %vres = fadd double %varg1, %varg286 %res = bitcast double %vres to i6487 ret i64 %res88 }89 90 define void @floatingPointStore(i64 %arg1, ptr %addr) {91 %varg1 = bitcast i64 %arg1 to double92 %vres = fadd double %varg1, %varg193 store double %vres, ptr %addr94 ret void95 }96 97 define void @fp16Ext32() { ret void }98 define void @fp16Ext64() { ret void }99 define void @fp32Ext64() { ret void }100 101 define half @passFp16(half %p) {102 entry:103 ret half %p104 }105 106 define half @passFp16ViaAllocas(half %p) {107 entry:108 %p.addr = alloca half, align 2109 store half %p, ptr %p.addr, align 2110 %0 = load half, ptr %p.addr, align 2111 ret half %0112 }113...114 115---116# Check that we assign a relevant register bank for %0.117# Based on the type i32, this should be gpr.118name: defaultMapping119legalized: true120registers:121 - { id: 0, class: _ }122 - { id: 1, class: _ }123body: |124 bb.0.entry:125 liveins: $x0126 ; CHECK-LABEL: name: defaultMapping127 ; CHECK: %1:gpr(s32) = G_ADD %0128 %0(s32) = COPY $w0129 %1(s32) = G_ADD %0, %0130...131 132---133# Check that we assign a relevant register bank for %0.134# Based on the type <2 x i32>, this should be fpr.135# FPR is used for both floating point and vector registers.136name: defaultMappingVector137legalized: true138registers:139 - { id: 0, class: _ }140 - { id: 1, class: _ }141body: |142 bb.0.entry:143 liveins: $d0144 ; CHECK-LABEL: name: defaultMappingVector145 ; CHECK: %0:fpr(<2 x s32>) = COPY $d0146 ; CHECK: %1:fpr(<2 x s32>) = G_ADD %0147 %0(<2 x s32>) = COPY $d0148 %1(<2 x s32>) = G_ADD %0, %0149...150 151---152# Check that we repair the assignment for %0.153# Indeed based on the source of the copy it should live154# in FPR, but at the use, it should be GPR.155name: defaultMapping1Repair156legalized: true157registers:158 - { id: 0, class: _ }159 - { id: 1, class: _ }160 - { id: 2, class: _ }161body: |162 bb.0.entry:163 liveins: $s0, $x0164 ; CHECK-LABEL: name: defaultMapping1Repair165 ; CHECK: %0:fpr(s32) = COPY $s0166 ; CHECK-NEXT: %1:gpr(s32) = COPY $w0167 ; CHECK-NEXT: %3:gpr(s32) = COPY %0168 ; CHECK-NEXT: %2:gpr(s32) = G_ADD %3, %1169 %0(s32) = COPY $s0170 %1(s32) = COPY $w0171 %2(s32) = G_ADD %0, %1172...173 174# Check that we repair the assignment for %0 differently for both uses.175name: defaultMapping2Repairs176legalized: true177registers:178 - { id: 0, class: _ }179 - { id: 1, class: _ }180body: |181 bb.0.entry:182 liveins: $s0, $x0183 ; CHECK-LABEL: name: defaultMapping2Repairs184 ; CHECK: %0:fpr(s32) = COPY $s0185 ; CHECK-NEXT: %2:gpr(s32) = COPY %0186 ; CHECK-NEXT: %3:gpr(s32) = COPY %0187 ; CHECK-NEXT: %1:gpr(s32) = G_ADD %2, %3188 %0(s32) = COPY $s0189 %1(s32) = G_ADD %0, %0190...191 192---193# Check that we repair the definition of %1.194# %1 is forced to be into FPR, but its definition actually195# requires that it lives in GPR. Make sure regbankselect196# fixes that.197name: defaultMappingDefRepair198legalized: true199registers:200 - { id: 0, class: _ }201 - { id: 1, class: fpr }202body: |203 bb.0.entry:204 liveins: $w0205 ; CHECK-LABEL: name: defaultMappingDefRepair206 ; CHECK: %0:gpr(s32) = COPY $w0207 ; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %0208 ; CHECK-NEXT: %1:fpr(s32) = COPY %2209 %0(s32) = COPY $w0210 %1(s32) = G_ADD %0, %0211...212 213---214# Check that we are able to propagate register banks from phis.215name: phiPropagation216legalized: true217tracksRegLiveness: true218# CHECK: registers:219# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '', flags: [ ] }220# CHECK-NEXT: - { id: 1, class: gpr64sp, preferred-register: '', flags: [ ] }221# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '', flags: [ ] }222# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '', flags: [ ] }223# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '', flags: [ ] }224registers:225 - { id: 0, class: gpr32 }226 - { id: 1, class: gpr64sp }227 - { id: 2, class: gpr32 }228 - { id: 3, class: _ }229 - { id: 4, class: _ }230 - { id: 5, class: _ }231body: |232 bb.0.entry:233 successors: %bb.2.end, %bb.1.then234 liveins: $x0, $x1, $w2235 236 %0 = LDRWui killed $x0, 0 :: (load (s32) from %ir.src)237 %5(s32) = COPY %0238 %1(p0) = COPY $x1239 %2 = COPY $w2240 TBNZW killed %2, 0, %bb.2.end241 242 bb.1.then:243 successors: %bb.2.end244 %3(s32) = G_ADD %5, %5245 246 bb.2.end:247 %4(s32) = PHI %0, %bb.0.entry, %3, %bb.1.then248 G_STORE killed %4, killed %1 :: (store (s32) into %ir.dst)249 RET_ReallyLR250...251 252---253# Make sure we can repair physical register uses as well.254name: defaultMappingUseRepairPhysReg255legalized: true256registers:257 - { id: 0, class: _ }258 - { id: 1, class: _ }259 - { id: 2, class: _ }260body: |261 bb.0.entry:262 liveins: $w0, $s0263 ; CHECK-LABEL: name: defaultMappingUseRepairPhysReg264 ; CHECK: %0:gpr(s32) = COPY $w0265 ; CHECK-NEXT: %1:fpr(s32) = COPY $s0266 ; CHECK-NEXT: %3:gpr(s32) = COPY %1267 ; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %3268 %0(s32) = COPY $w0269 %1(s32) = COPY $s0270 %2(s32) = G_ADD %0, %1271...272 273---274# Make sure we can repair physical register defs.275name: defaultMappingDefRepairPhysReg276legalized: true277registers:278 - { id: 0, class: _ }279 - { id: 1, class: _ }280body: |281 bb.0.entry:282 liveins: $w0283 ; CHECK-LABEL: name: defaultMappingDefRepairPhysReg284 ; CHECK: %0:gpr(s32) = COPY $w0285 ; CHECK-NEXT: %1:gpr(s32) = G_ADD %0, %0286 ; CHECK-NEXT: $s0 = COPY %1287 %0(s32) = COPY $w0288 %1(s32) = G_ADD %0, %0289 $s0 = COPY %1290...291 292---293# Check that the greedy mode is able to switch the294# G_OR instruction from fpr to gpr.295name: greedyMappingOr296legalized: true297registers:298 - { id: 0, class: _ }299 - { id: 1, class: _ }300 - { id: 2, class: _ }301body: |302 bb.0.entry:303 liveins: $x0, $x1304 ; CHECK: %0:gpr(<2 x s32>) = COPY $x0305 ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY $x1306 307 ; Fast mode tries to reuse the source of the copy for the destination.308 ; Now, the default mapping says that %0 and %1 need to be in FPR.309 ; The repairing code insert two copies to materialize that.310 ; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0311 ; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1312 ; The mapping of G_OR is on FPR.313 ; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4314 315 ; Greedy mode remapped the instruction on the GPR bank.316 ; GREEDY-NEXT: %2:gpr(<2 x s32>) = G_OR %0, %1317 %0(<2 x s32>) = COPY $x0318 %1(<2 x s32>) = COPY $x1319 %2(<2 x s32>) = G_OR %0, %1320...321 322---323# Check that the greedy mode is able to switch the324# G_OR instruction from fpr to gpr, while still honoring325# %2 constraint.326name: greedyMappingOrWithConstraints327legalized: true328registers:329 - { id: 0, class: _ }330 - { id: 1, class: _ }331 - { id: 2, class: fpr }332body: |333 bb.0.entry:334 liveins: $x0, $x1335 ; CHECK-LABEL: name: greedyMappingOrWithConstraints336 337 ; CHECK: %0:gpr(<2 x s32>) = COPY $x0338 ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY $x1339 340 ; Fast mode tries to reuse the source of the copy for the destination.341 ; Now, the default mapping says that %0 and %1 need to be in FPR.342 ; The repairing code insert two copies to materialize that.343 ; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0344 ; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1345 ; The mapping of G_OR is on FPR.346 ; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4347 348 ; Greedy mode remapped the instruction on the GPR bank.349 ; GREEDY-NEXT: %3:gpr(<2 x s32>) = G_OR %0, %1350 ; We need to keep %2 into FPR because we do not know anything about it.351 ; GREEDY-NEXT: %2:fpr(<2 x s32>) = COPY %3352 %0(<2 x s32>) = COPY $x0353 %1(<2 x s32>) = COPY $x1354 %2(<2 x s32>) = G_OR %0, %1355...356 357---358# CHECK-LABEL: name: ignoreTargetSpecificInst359name: ignoreTargetSpecificInst360legalized: true361# CHECK: registers:362# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '', flags: [ ] }363# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '', flags: [ ] }364registers:365 - { id: 0, class: gpr64 }366 - { id: 1, class: gpr64 }367body: |368 bb.0:369 liveins: $x0370 371 ; CHECK: %0:gpr64 = COPY $x0372 ; CHECK-NEXT: %1:gpr64 = ADDXrr %0, %0373 ; CHECK-NEXT: $x0 = COPY %1374 ; CHECK-NEXT: RET_ReallyLR implicit $x0375 376 %0 = COPY $x0377 %1 = ADDXrr %0, %0378 $x0 = COPY %1379 RET_ReallyLR implicit $x0380...381 382---383# Check that we set the "regBankSelected" property.384# CHECK-LABEL: name: regBankSelected_property385# CHECK: legalized: true386# CHECK: regBankSelected: true387name: regBankSelected_property388legalized: true389regBankSelected: false390body: |391 bb.0:392...393 394---395# CHECK-LABEL: name: bitcast_s32_gpr396name: bitcast_s32_gpr397legalized: true398 399# CHECK: registers:400# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }401# FAST-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }402# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }403registers:404 - { id: 0, class: _ }405 - { id: 1, class: _ }406 407# CHECK: body:408# CHECK: %0:gpr(s32) = COPY $w0409# FAST-NEXT: %1:fpr(<4 x s8>) = G_BITCAST %0410# GREEDY-NEXT: %1:gpr(<4 x s8>) = G_BITCAST %0411# The greedy check is incorrect and should produce fpr.412body: |413 bb.0:414 liveins: $w0415 416 %0(s32) = COPY $w0417 %1(<4 x s8>) = G_BITCAST %0418...419 420---421# CHECK-LABEL: name: bitcast_s32_fpr422name: bitcast_s32_fpr423legalized: true424 425# CHECK: registers:426# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '', flags: [ ] }427# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }428# GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }429registers:430 - { id: 0, class: _ }431 - { id: 1, class: _ }432 433# CHECK: body:434# CHECK: %0:fpr(<2 x s16>) = COPY $s0435# FAST: %1:gpr(s32) = G_BITCAST %0436# GREEDY: %1:fpr(s32) = G_BITCAST %0437body: |438 bb.0:439 liveins: $s0440 441 %0(<2 x s16>) = COPY $s0442 %1(s32) = G_BITCAST %0443...444 445---446# CHECK-LABEL: name: bitcast_s32_gpr_fpr447name: bitcast_s32_gpr_fpr448legalized: true449 450# CHECK: registers:451# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }452# FAST-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }453# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }454registers:455 - { id: 0, class: _ }456 - { id: 1, class: _ }457 458# CHECK: body:459# CHECK: %0:gpr(s32) = COPY $w0460# FAST: %1:fpr(<2 x s16>) = G_BITCAST %0461# GREEDY: %1:gpr(<2 x s16>) = G_BITCAST %0462body: |463 bb.0:464 liveins: $w0465 466 %0(s32) = COPY $w0467 %1(<2 x s16>) = G_BITCAST %0468...469 470---471# CHECK-LABEL: name: bitcast_s32_fpr_gpr472name: bitcast_s32_fpr_gpr473legalized: true474registers:475 - { id: 0, class: _ }476 - { id: 1, class: _ }477# CHECK: body:478# CHECK: %0:fpr(<2 x s16>) = COPY $s0479# FAST: %1:gpr(s32) = G_BITCAST %0480# GREEDY: %1:fpr(s32) = G_BITCAST %0481body: |482 bb.0:483 liveins: $s0484 485 %0(<2 x s16>) = COPY $s0486 %1(s32) = G_BITCAST %0487...488 489---490# CHECK-LABEL: name: bitcast_s64_gpr491name: bitcast_s64_gpr492legalized: true493registers:494 - { id: 0, class: _ }495 - { id: 1, class: _ }496# CHECK: body:497# CHECK: %0:gpr(s64) = COPY $x0498# FAST: %1:fpr(<2 x s32>) = G_BITCAST %0499# GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0500body: |501 bb.0:502 liveins: $x0503 504 %0(s64) = COPY $x0505 %1(<2 x s32>) = G_BITCAST %0506...507 508---509# CHECK-LABEL: name: bitcast_s64_fpr510name: bitcast_s64_fpr511legalized: true512registers:513 - { id: 0, class: _ }514 - { id: 1, class: _ }515# CHECK: body:516# CHECK: %0:fpr(<2 x s32>) = COPY $d0517# FAST: %1:gpr(s64) = G_BITCAST %0518# GREEDY: %1:fpr(s64) = G_BITCAST %0519body: |520 bb.0:521 liveins: $d0522 523 %0(<2 x s32>) = COPY $d0524 %1(s64) = G_BITCAST %0525...526 527---528# CHECK-LABEL: name: bitcast_s64_gpr_fpr529name: bitcast_s64_gpr_fpr530legalized: true531registers:532 - { id: 0, class: _ }533 - { id: 1, class: _ }534# CHECK: body:535# CHECK: %0:gpr(s64) = COPY $x0536# FAST: %1:fpr(<2 x s32>) = G_BITCAST %0537# GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0538body: |539 bb.0:540 liveins: $x0541 542 %0(s64) = COPY $x0543 %1(<2 x s32>) = G_BITCAST %0544...545 546---547# CHECK-LABEL: name: bitcast_s64_fpr_gpr548name: bitcast_s64_fpr_gpr549legalized: true550registers:551 - { id: 0, class: _ }552 - { id: 1, class: _ }553# CHECK: body:554# CHECK: %0:fpr(<2 x s32>) = COPY $d0555# FAST: %1:gpr(s64) = G_BITCAST %0556# GREEDY: %1:fpr(s64) = G_BITCAST %0557body: |558 bb.0:559 liveins: $d0560 561 %0(<2 x s32>) = COPY $d0562 %1(s64) = G_BITCAST %0563...564 565---566# CHECK-LABEL: name: bitcast_s128567name: bitcast_s128568legalized: true569tracksRegLiveness: true570registers:571 - { id: 0, class: _}572 - { id: 1, class: _}573 - { id: 2, class: _}574 - { id: 3, class: _}575# CHECK: %3:fpr(s128) = G_MERGE_VALUES576# CHECK: %2:fpr(<2 x s64>) = G_BITCAST %3(s128)577body: |578 bb.1:579 liveins: $x0, $x1580 %0(s64) = COPY $x0581 %1(s64) = COPY $x1582 %3(s128) = G_MERGE_VALUES %0(s64), %1(s64)583 %2(<2 x s64>) = G_BITCAST %3(s128)584 $q0 = COPY %2(<2 x s64>)585 RET_ReallyLR implicit $q0586 587...588 589---590# CHECK-LABEL: name: copy_s128591# This test checks that we issue the proper mapping592# for copy of size > 64.593# The mapping should be the same as G_BITCAST.594name: copy_s128595legalized: true596tracksRegLiveness: true597registers:598 - { id: 0, class: _}599 - { id: 1, class: _}600 - { id: 2, class: _}601 - { id: 3, class: _}602 - { id: 4, class: _}603# CHECK: %3:fpr(s128) = G_MERGE_VALUES604# CHECK: %4:fpr(s128) = COPY %3(s128)605# CHECK-NEXT: %2:fpr(<2 x s64>) = G_BITCAST %4(s128)606body: |607 bb.1:608 liveins: $x0, $x1609 %0(s64) = COPY $x0610 %1(s64) = COPY $x1611 %3(s128) = G_MERGE_VALUES %0(s64), %1(s64)612 %4(s128) = COPY %3(s128)613 %2(<2 x s64>) = G_BITCAST %4(s128)614 $q0 = COPY %2(<2 x s64>)615 RET_ReallyLR implicit $q0616 617...618 619---620# CHECK-LABEL: name: copy_s128_from_load621# This test checks that we issue the proper mapping622# for copy of size > 64 when the input is neither623# a physcal register nor a generic register.624# This used to crash when we moved to the statically625# computed mapping, because we were assuming non-physregs626# were generic registers and thus have a type, whereas627# it is not necessarily the case.628name: copy_s128_from_load629legalized: true630tracksRegLiveness: true631registers:632 - { id: 0, class: fpr128}633 - { id: 1, class: _}634# CHECK: registers:635# CHECK: - { id: 0, class: fpr128, preferred-register: '', flags: [ ] }636# CHECK: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }637# CHECK: %1:fpr(s128) = COPY %0638body: |639 bb.1:640 liveins: $x0641 %0 = LDRQui killed $x0, 0642 %1(s128) = COPY %0643 $q0 = COPY %1(s128)644 RET_ReallyLR implicit $q0645 646...647 648---649# CHECK-LABEL: name: copy_fp16650# This test checks that we issue the proper mapping651# for copy of size == 16 when the destination is a fpr652# physical register and the source a gpr.653# We used to crash because we thought that mapping couldn't654# exist in a copy.655name: copy_fp16656legalized: true657tracksRegLiveness: true658registers:659 - { id: 0, class: _}660 - { id: 1, class: _}661# CHECK: registers:662# CHECK: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }663# CHECK: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }664# CHECK: %0:gpr(s32) = COPY $w0665# CHECK-NEXT: %1:gpr(s16) = G_TRUNC %0(s32)666body: |667 bb.1:668 liveins: $w0669 %0(s32) = COPY $w0670 %1(s16) = G_TRUNC %0(s32)671 $h0 = COPY %1(s16)672 RET_ReallyLR implicit $h0673 674...675 676 677---678# Make sure the greedy mode is able to take advantage of the679# alternative mappings of G_LOAD to coalesce the whole chain680# of computation on GPR.681# CHECK-LABEL: name: greedyWithChainOfComputation682name: greedyWithChainOfComputation683legalized: true684registers:685 - { id: 0, class: _ }686 - { id: 1, class: _ }687 - { id: 2, class: _ }688 - { id: 3, class: _ }689 - { id: 4, class: _ }690 - { id: 5, class: _ }691# No repairing should be necessary for both modes.692# CHECK: %0:gpr(s64) = COPY $x0693# CHECK-NEXT: %1:gpr(p0) = COPY $x1694# FAST-NEXT: %2:fpr(<2 x s32>) = G_BITCAST %0(s64)695# FAST-NEXT: %3:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>) from %ir.addr)696# FAST-NEXT: %4:fpr(<2 x s32>) = G_OR %2, %3697# GREEDY-NEXT: %2:gpr(<2 x s32>) = G_BITCAST %0(s64)698# GREEDY-NEXT: %3:gpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>) from %ir.addr)699# GREEDY-NEXT: %4:gpr(<2 x s32>) = G_OR %2, %3700# CHECK-NEXT: %5:gpr(s64) = G_BITCAST %4(<2 x s32>)701# CHECK-NEXT: $x0 = COPY %5(s64)702# CHECK-NEXT: RET_ReallyLR implicit $x0703body: |704 bb.0:705 liveins: $x0, $x1706 707 %0(s64) = COPY $x0708 %1(p0) = COPY $x1709 %2(<2 x s32>) = G_BITCAST %0(s64)710 %3(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>) from %ir.addr)711 %4(<2 x s32>) = G_OR %2, %3712 %5(s64) = G_BITCAST %4(<2 x s32>)713 $x0 = COPY %5(s64)714 RET_ReallyLR implicit $x0715 716...717 718---719# Make sure we map what looks like floating point720# loads to floating point register bank.721# CHECK-LABEL: name: floatingPointLoad722name: floatingPointLoad723legalized: true724 725# CHECK: registers:726# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }727# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }728# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '', flags: [ ] }729# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '', flags: [ ] }730# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '', flags: [ ] }731registers:732 - { id: 0, class: _ }733 - { id: 1, class: _ }734 - { id: 2, class: _ }735 - { id: 3, class: _ }736 737# No repairing should be necessary for both modes.738# CHECK: %0:gpr(s64) = COPY $x0739# CHECK-NEXT: %1:gpr(p0) = COPY $x1740# CHECK-NEXT: %2:fpr(s64) = G_LOAD %1(p0) :: (load (s64) from %ir.addr)741# %0 has been mapped to GPR, we need to repair to match FPR.742# CHECK-NEXT: %4:fpr(s64) = COPY %0743# CHECK-NEXT: %3:fpr(s64) = G_FADD %4, %2744# CHECK-NEXT: $x0 = COPY %3(s64)745# CHECK-NEXT: RET_ReallyLR implicit $x0746 747body: |748 bb.0:749 liveins: $x0, $x1750 751 %0(s64) = COPY $x0752 %1(p0) = COPY $x1753 %2(s64) = G_LOAD %1(p0) :: (load (s64) from %ir.addr)754 %3(s64) = G_FADD %0, %2755 $x0 = COPY %3(s64)756 RET_ReallyLR implicit $x0757 758...759 760---761# Make sure we map what looks like floating point762# stores to floating point register bank.763# CHECK-LABEL: name: floatingPointStore764name: floatingPointStore765legalized: true766 767# CHECK: registers:768# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }769# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }770# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '', flags: [ ] }771# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '', flags: [ ] }772# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '', flags: [ ] }773registers:774 - { id: 0, class: _ }775 - { id: 1, class: _ }776 - { id: 2, class: _ }777 778# CHECK: %0:gpr(s64) = COPY $x0779# CHECK-NEXT: %1:gpr(p0) = COPY $x1780# %0 has been mapped to GPR, we need to repair to match FPR.781# CHECK-NEXT: %3:fpr(s64) = COPY %0782# CHECK-NEXT: %4:fpr(s64) = COPY %0783# CHECK-NEXT: %2:fpr(s64) = G_FADD %3, %4784# CHECK-NEXT: G_STORE %2(s64), %1(p0) :: (store (s64) into %ir.addr)785# CHECK-NEXT: RET_ReallyLR786 787body: |788 bb.0:789 liveins: $x0, $x1790 791 %0(s64) = COPY $x0792 %1(p0) = COPY $x1793 %2(s64) = G_FADD %0, %0794 G_STORE %2(s64), %1(p0) :: (store (s64) into %ir.addr)795 RET_ReallyLR796 797...798 799---800# Make sure we map FPEXT on FPR register bank.801# CHECK-LABEL: name: fp16Ext32802name: fp16Ext32803alignment: 4804legalized: true805# CHECK: registers:806# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }807# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }808# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '', flags: [ ] }809# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '', flags: [ ] }810registers:811 - { id: 0, class: _ }812 - { id: 1, class: _ }813 - { id: 2, class: _ }814# CHECK: %1:gpr(s32) = COPY $w0815# CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1816# %0 has been mapped to GPR, we need to repair to match FPR.817# CHECK-NEXT: %3:fpr(s16) = COPY %0818# CHECK-NEXT: %2:fpr(s32) = G_FPEXT %3819# CHECK-NEXT: $s0 = COPY %2820# CHECK-NEXT: RET_ReallyLR821 822body: |823 bb.1:824 liveins: $w0825 826 %1(s32) = COPY $w0827 %0(s16) = G_TRUNC %1(s32)828 %2(s32) = G_FPEXT %0(s16)829 $s0 = COPY %2(s32)830 RET_ReallyLR implicit $s0831 832...833 834---835# Make sure we map FPEXT on FPR register bank.836# CHECK-LABEL: name: fp16Ext64837name: fp16Ext64838alignment: 4839legalized: true840# CHECK: registers:841# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }842# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }843# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '', flags: [ ] }844# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '', flags: [ ] }845registers:846 - { id: 0, class: _ }847 - { id: 1, class: _ }848 - { id: 2, class: _ }849# CHECK: %1:gpr(s32) = COPY $w0850# CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1851# %0 has been mapped to GPR, we need to repair to match FPR.852# CHECK-NEXT: %3:fpr(s16) = COPY %0853# CHECK-NEXT: %2:fpr(s64) = G_FPEXT %3854# CHECK-NEXT: $d0 = COPY %2855# CHECK-NEXT: RET_ReallyLR856 857body: |858 bb.1:859 liveins: $w0860 861 %1(s32) = COPY $w0862 %0(s16) = G_TRUNC %1(s32)863 %2(s64) = G_FPEXT %0(s16)864 $d0 = COPY %2(s64)865 RET_ReallyLR implicit $d0866 867...868 869---870# Make sure we map FPEXT on FPR register bank.871# CHECK-LABEL: name: fp32Ext64872name: fp32Ext64873alignment: 4874legalized: true875# CHECK: registers:876# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }877# CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '', flags: [ ] }878# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '', flags: [ ] }879registers:880 - { id: 0, class: _ }881 - { id: 1, class: _ }882# CHECK: %0:gpr(s32) = COPY $w0883# %0 has been mapped to GPR, we need to repair to match FPR.884# CHECK-NEXT: %2:fpr(s32) = COPY %0885# CHECK-NEXT: %1:fpr(s64) = G_FPEXT %2886# CHECK-NEXT: $d0 = COPY %1887# CHECK-NEXT: RET_ReallyLR888body: |889 bb.1:890 liveins: $w0891 892 %0(s32) = COPY $w0893 %1(s64) = G_FPEXT %0(s32)894 $d0 = COPY %1(s64)895 RET_ReallyLR implicit $d0896 897...898 899---900# Make sure we map FP16 ABI on FPR register bank.901# CHECK-LABEL: name: passFp16902# CHECK: registers:903# CHECK: - { id: 0, class: fpr, preferred-register: '', flags: [ ] }904# CHECK: %0:fpr(s16) = COPY $h0905# CHECK-NEXT: $h0 = COPY %0(s16)906name: passFp16907alignment: 4908legalized: true909registers:910 - { id: 0, class: _ }911body: |912 bb.1.entry:913 liveins: $h0914 915 %0(s16) = COPY $h0916 $h0 = COPY %0(s16)917 RET_ReallyLR implicit $h0918 919...920---921# Make sure we properly detect fp types through copies.922# In that example, the copy comes from an ABI lowering of a fp type.923# CHECK-LABEL: name: passFp16ViaAllocas924# CHECK: registers:925# CHECK: - { id: 0, class: fpr, preferred-register: '', flags: [ ] }926# CHECK: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }927# CHECK: - { id: 2, class: fpr, preferred-register: '', flags: [ ] }928#929# CHECK: %0:fpr(s16) = COPY $h0930# CHECK-NEXT: %1:gpr(p0) = G_FRAME_INDEX %stack.0.p.addr931# If we didn't look through the copy for %0, the default mapping932# would have been on GPR and we would have to insert a copy to move933# the value away from FPR (h0).934# CHECK-NEXT: G_STORE %0(s16), %1(p0) :: (store (s16) into %ir.p.addr)935# If we didn't look through the copy for %2, the default mapping936# would have been on GPR and we would have to insert a copy to move937# the value to FPR (h0).938# CHECK-NEXT: %2:fpr(s16) = G_LOAD %1(p0) :: (load (s16) from %ir.p.addr)939# CHECK-NEXT: $h0 = COPY %2(s16)940name: passFp16ViaAllocas941alignment: 4942legalized: true943tracksRegLiveness: true944registers:945 - { id: 0, class: _ }946 - { id: 1, class: _ }947 - { id: 2, class: _ }948frameInfo:949 maxAlignment: 2950stack:951 - { id: 0, name: p.addr, size: 2, alignment: 2, stack-id: default }952body: |953 bb.1.entry:954 liveins: $h0955 956 %0(s16) = COPY $h0957 %1(p0) = G_FRAME_INDEX %stack.0.p.addr958 G_STORE %0(s16), %1(p0) :: (store (s16) into %ir.p.addr)959 %2(s16) = G_LOAD %1(p0) :: (load (s16) from %ir.p.addr)960 $h0 = COPY %2(s16)961 RET_ReallyLR implicit $h0962 963...964