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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s3 4---5name: add_lhs_sub_reg6alignment: 47tracksRegLiveness: true8frameInfo:9 maxAlignment: 110machineFunctionInfo: {}11body: |12 bb.0:13 liveins: $w0, $w114 ; CHECK-LABEL: name: add_lhs_sub_reg15 ; CHECK: liveins: $w0, $w116 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w018 ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)19 %0:_(s32) = COPY $w020 %1:_(s32) = COPY $w121 %2:_(s32) = G_SUB %0, %122 %3:_(s32) = G_ADD %2, %123 $w0 = COPY %324...25---26name: add_lhs_sub_reg_wide27alignment: 428tracksRegLiveness: true29frameInfo:30 maxAlignment: 131machineFunctionInfo: {}32body: |33 bb.0:34 liveins: $q0, $q135 ; CHECK-LABEL: name: add_lhs_sub_reg_wide36 ; CHECK: liveins: $q0, $q137 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q039 ; CHECK-NEXT: $q0 = COPY [[COPY]](s128)40 %0:_(s128) = COPY $q041 %1:_(s128) = COPY $q142 %2:_(s128) = G_SUB %0, %143 %3:_(s128) = G_ADD %2, %144 $q0 = COPY %345...46---47name: add_lhs_sub_reg_vec48alignment: 449tracksRegLiveness: true50frameInfo:51 maxAlignment: 152machineFunctionInfo: {}53body: |54 bb.0:55 liveins: $x0, $x156 ; CHECK-LABEL: name: add_lhs_sub_reg_vec57 ; CHECK: liveins: $x0, $x158 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x060 ; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)61 %0:_(<4 x s16>) = COPY $x062 %1:_(<4 x s16>) = COPY $x163 %2:_(<4 x s16>) = G_SUB %0, %164 %3:_(<4 x s16>) = G_ADD %2, %165 $x0 = COPY %366...67---68name: add_rhs_sub_reg69alignment: 470tracksRegLiveness: true71frameInfo:72 maxAlignment: 173machineFunctionInfo: {}74body: |75 bb.0:76 liveins: $w0, $w177 ; CHECK-LABEL: name: add_rhs_sub_reg78 ; CHECK: liveins: $w0, $w179 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w081 ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)82 %0:_(s32) = COPY $w083 %1:_(s32) = COPY $w184 %2:_(s32) = G_SUB %0, %185 %3:_(s32) = G_ADD %1, %286 $w0 = COPY %387...88---89name: add_rhs_sub_reg_wide90alignment: 491tracksRegLiveness: true92frameInfo:93 maxAlignment: 194machineFunctionInfo: {}95body: |96 bb.0:97 liveins: $q0, $q198 ; CHECK-LABEL: name: add_rhs_sub_reg_wide99 ; CHECK: liveins: $q0, $q1100 ; CHECK-NEXT: {{ $}}101 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0102 ; CHECK-NEXT: $q0 = COPY [[COPY]](s128)103 %0:_(s128) = COPY $q0104 %1:_(s128) = COPY $q1105 %2:_(s128) = G_SUB %0, %1106 %3:_(s128) = G_ADD %1, %2107 $q0 = COPY %3108...109---110name: add_rhs_sub_reg_vec111alignment: 4112tracksRegLiveness: true113frameInfo:114 maxAlignment: 1115machineFunctionInfo: {}116body: |117 bb.0:118 liveins: $x0, $x1119 ; CHECK-LABEL: name: add_rhs_sub_reg_vec120 ; CHECK: liveins: $x0, $x1121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0123 ; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)124 %0:_(<4 x s16>) = COPY $x0125 %1:_(<4 x s16>) = COPY $x1126 %2:_(<4 x s16>) = G_SUB %0, %1127 %3:_(<4 x s16>) = G_ADD %1, %2128 $x0 = COPY %3129...130---131name: fadd_by_zero132tracksRegLiveness: true133body: |134 bb.0:135 liveins: $d0136 ; CHECK-LABEL: name: fadd_by_zero137 ; CHECK: liveins: $d0138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0140 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00141 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[C]]142 ; CHECK-NEXT: $d0 = COPY [[FADD]](s64)143 %0:_(s64) = COPY $d0144 %1:_(s64) = G_FCONSTANT double 0.000000e+00145 %2:_(s64) = G_FADD %0, %1(s64)146 $d0 = COPY %2(s64)147...148---149name: fadd_vector_by_zero150alignment: 4151tracksRegLiveness: true152frameInfo:153 maxAlignment: 1154machineFunctionInfo: {}155body: |156 bb.0:157 liveins: $q0158 ; CHECK-LABEL: name: fadd_vector_by_zero159 ; CHECK: liveins: $q0160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0162 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00163 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)164 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[COPY]], [[BUILD_VECTOR]]165 ; CHECK-NEXT: $q0 = COPY [[FADD]](<4 x s32>)166 %0:_(<4 x s32>) = COPY $q0167 %1:_(s32) = G_FCONSTANT float 0.0168 %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)169 %3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)170 $q0 = COPY %3(<4 x s32>)171...172 173---174name: fadd_by_neg_zero175tracksRegLiveness: true176body: |177 bb.0:178 liveins: $d0179 ; CHECK-LABEL: name: fadd_by_neg_zero180 ; CHECK: liveins: $d0181 ; CHECK-NEXT: {{ $}}182 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0183 ; CHECK-NEXT: $d0 = COPY [[COPY]](s64)184 %0:_(s64) = COPY $d0185 %1:_(s64) = G_FCONSTANT double -0.000000e+00186 %2:_(s64) = G_FADD %0, %1(s64)187 $d0 = COPY %2(s64)188...189---190name: fadd_vector_by_neg_zero191alignment: 4192tracksRegLiveness: true193frameInfo:194 maxAlignment: 1195machineFunctionInfo: {}196body: |197 bb.0:198 liveins: $q0199 ; CHECK-LABEL: name: fadd_vector_by_neg_zero200 ; CHECK: liveins: $q0201 ; CHECK-NEXT: {{ $}}202 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0203 ; CHECK-NEXT: $q0 = COPY [[COPY]](<4 x s32>)204 %0:_(<4 x s32>) = COPY $q0205 %1:_(s32) = G_FCONSTANT float -0.0206 %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)207 %3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)208 $q0 = COPY %3(<4 x s32>)209...210---211name: saddl_v8i8_v8i32212tracksRegLiveness: true213body: |214 bb.1:215 liveins: $d0, $d1216 217 ; CHECK-LABEL: name: saddl_v8i8_v8i32218 ; CHECK: liveins: $d0, $d1219 ; CHECK-NEXT: {{ $}}220 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0221 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1222 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)223 ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)224 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[SEXT]], [[SEXT1]]225 ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[ADD]](<8 x s16>)226 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT2]](<8 x s32>)227 ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)228 ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)229 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1230 %0:_(<8 x s8>) = COPY $d0231 %1:_(<8 x s8>) = COPY $d1232 %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)233 %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)234 %4:_(<8 x s32>) = G_ADD %2, %3235 %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)236 $q0 = COPY %5(<4 x s32>)237 $q1 = COPY %6(<4 x s32>)238 RET_ReallyLR implicit $q0, implicit $q1239...240 241---242name: uaddl_v8i8_v8i32243tracksRegLiveness: true244body: |245 bb.1:246 liveins: $d0, $d1247 248 ; CHECK-LABEL: name: uaddl_v8i8_v8i32249 ; CHECK: liveins: $d0, $d1250 ; CHECK-NEXT: {{ $}}251 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0252 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1253 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)254 ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)255 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[ZEXT1]]256 ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[ADD]](<8 x s16>)257 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ZEXT2]](<8 x s32>)258 ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)259 ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)260 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1261 %0:_(<8 x s8>) = COPY $d0262 %1:_(<8 x s8>) = COPY $d1263 %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)264 %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)265 %4:_(<8 x s32>) = G_ADD %2, %3266 %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)267 $q0 = COPY %5(<4 x s32>)268 $q1 = COPY %6(<4 x s32>)269 RET_ReallyLR implicit $q0, implicit $q1270...271 272---273name: ssubl_v8i8_v8i32274tracksRegLiveness: true275body: |276 bb.1:277 liveins: $d0, $d1278 279 ; CHECK-LABEL: name: ssubl_v8i8_v8i32280 ; CHECK: liveins: $d0, $d1281 ; CHECK-NEXT: {{ $}}282 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0283 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1284 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)285 ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)286 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[SEXT]], [[SEXT1]]287 ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[SUB]](<8 x s16>)288 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT2]](<8 x s32>)289 ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)290 ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)291 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1292 %0:_(<8 x s8>) = COPY $d0293 %1:_(<8 x s8>) = COPY $d1294 %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)295 %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)296 %4:_(<8 x s32>) = G_SUB %2, %3297 %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)298 $q0 = COPY %5(<4 x s32>)299 $q1 = COPY %6(<4 x s32>)300 RET_ReallyLR implicit $q0, implicit $q1301...302 303---304name: usubl_v8i8_v8i32305tracksRegLiveness: true306body: |307 bb.1:308 liveins: $d0, $d1309 310 ; CHECK-LABEL: name: usubl_v8i8_v8i32311 ; CHECK: liveins: $d0, $d1312 ; CHECK-NEXT: {{ $}}313 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0314 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1315 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)316 ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)317 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[ZEXT]], [[ZEXT1]]318 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[SUB]](<8 x s16>)319 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT]](<8 x s32>)320 ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)321 ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)322 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1323 %0:_(<8 x s8>) = COPY $d0324 %1:_(<8 x s8>) = COPY $d1325 %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)326 %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)327 %4:_(<8 x s32>) = G_SUB %2, %3328 %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)329 $q0 = COPY %5(<4 x s32>)330 $q1 = COPY %6(<4 x s32>)331 RET_ReallyLR implicit $q0, implicit $q1332...333