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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2 3# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="icmp_to_lhs_known_bits" -global-isel -verify-machineinstrs %s -o - | FileCheck %s4# REQUIRES: asserts5 6...7---8name: apply_ne9alignment: 410tracksRegLiveness: true11machineFunctionInfo: {}12body: |13 bb.0:14 liveins: $w015 ; CHECK-LABEL: name: apply_ne16 ; CHECK: liveins: $w017 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: %x:_(s32) = COPY $w019 ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 120 ; CHECK-NEXT: %known_zero_or_one:_(s32) = G_AND %x, %one21 ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC %known_zero_or_one(s32)22 ; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)23 ; CHECK-NEXT: $w0 = COPY %ext(s32)24 ; CHECK-NEXT: RET_ReallyLR implicit $w025 %x:_(s32) = COPY $w026 %one:_(s32) = G_CONSTANT i32 127 %known_zero_or_one:_(s32) = G_AND %x, %one28 %zero:_(s32) = G_CONSTANT i32 029 %cmp:_(s1) = G_ICMP intpred(ne), %known_zero_or_one(s32), %zero30 %ext:_(s32) = G_ZEXT %cmp(s1)31 $w0 = COPY %ext(s32)32 RET_ReallyLR implicit $w033 34...35---36name: apply_eq37alignment: 438tracksRegLiveness: true39machineFunctionInfo: {}40body: |41 bb.0:42 liveins: $w043 ; CHECK-LABEL: name: apply_eq44 ; CHECK: liveins: $w045 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: %x:_(s32) = COPY $w047 ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 148 ; CHECK-NEXT: %known_zero_or_one:_(s32) = G_AND %x, %one49 ; CHECK-NEXT: %cmp:_(s1) = G_TRUNC %known_zero_or_one(s32)50 ; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)51 ; CHECK-NEXT: $w0 = COPY %ext(s32)52 ; CHECK-NEXT: RET_ReallyLR implicit $w053 %x:_(s32) = COPY $w054 %one:_(s32) = G_CONSTANT i32 155 %known_zero_or_one:_(s32) = G_AND %x, %one56 %cmp:_(s1) = G_ICMP intpred(eq), %known_zero_or_one(s32), %one57 %ext:_(s32) = G_ZEXT %cmp(s1)58 $w0 = COPY %ext(s32)59 RET_ReallyLR implicit $w060 61...62---63name: dont_apply_wrong_cst_eq64alignment: 465tracksRegLiveness: true66machineFunctionInfo: {}67body: |68 bb.0:69 liveins: $w070 ; Wrong constant on the RHS of the compare.71 72 ; CHECK-LABEL: name: dont_apply_wrong_cst_eq73 ; CHECK: liveins: $w074 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: %x:_(s32) = COPY $w076 ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 177 ; CHECK-NEXT: %known_zero_or_one:_(s32) = G_AND %x, %one78 ; CHECK-NEXT: %wrong_cst:_(s32) = G_CONSTANT i32 1079 ; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %known_zero_or_one(s32), %wrong_cst80 ; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)81 ; CHECK-NEXT: $w0 = COPY %ext(s32)82 ; CHECK-NEXT: RET_ReallyLR implicit $w083 %x:_(s32) = COPY $w084 %one:_(s32) = G_CONSTANT i32 185 %known_zero_or_one:_(s32) = G_AND %x, %one86 %wrong_cst:_(s32) = G_CONSTANT i32 1087 %cmp:_(s1) = G_ICMP intpred(eq), %known_zero_or_one(s32), %wrong_cst88 %ext:_(s32) = G_ZEXT %cmp(s1)89 $w0 = COPY %ext(s32)90 RET_ReallyLR implicit $w091 92...93---94name: dont_apply_wrong_cst_ne95alignment: 496tracksRegLiveness: true97machineFunctionInfo: {}98body: |99 bb.0:100 liveins: $w0101 ; Wrong constant on the RHS of the compare.102 103 ; CHECK-LABEL: name: dont_apply_wrong_cst_ne104 ; CHECK: liveins: $w0105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: %x:_(s32) = COPY $w0107 ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 1108 ; CHECK-NEXT: %known_zero_or_one:_(s32) = G_AND %x, %one109 ; CHECK-NEXT: %wrong_cst:_(s32) = G_CONSTANT i32 10110 ; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %known_zero_or_one(s32), %wrong_cst111 ; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)112 ; CHECK-NEXT: $w0 = COPY %ext(s32)113 ; CHECK-NEXT: RET_ReallyLR implicit $w0114 %x:_(s32) = COPY $w0115 %one:_(s32) = G_CONSTANT i32 1116 %known_zero_or_one:_(s32) = G_AND %x, %one117 %wrong_cst:_(s32) = G_CONSTANT i32 10118 %cmp:_(s1) = G_ICMP intpred(ne), %known_zero_or_one(s32), %wrong_cst119 %ext:_(s32) = G_ZEXT %cmp(s1)120 $w0 = COPY %ext(s32)121 RET_ReallyLR implicit $w0122 123...124---125name: dont_apply_vector126alignment: 4127tracksRegLiveness: true128machineFunctionInfo: {}129body: |130 bb.0:131 liveins: $x0132 ; True is -1 for vectors on AArch64 so we don't want to combine.133 134 ; CHECK-LABEL: name: dont_apply_vector135 ; CHECK: liveins: $x0136 ; CHECK-NEXT: {{ $}}137 ; CHECK-NEXT: %x:_(<2 x s32>) = COPY $x0138 ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 1139 ; CHECK-NEXT: %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one(s32), %one(s32)140 ; CHECK-NEXT: %vec_and:_(<2 x s32>) = G_AND %x, %one_vec141 ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0142 ; CHECK-NEXT: %zero64:_(s64) = G_CONSTANT i64 0143 ; CHECK-NEXT: %zero_vec:_(<2 x s32>) = G_BUILD_VECTOR %zero(s32), %zero(s32)144 ; CHECK-NEXT: %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %vec_and(<2 x s32>), %zero_vec145 ; CHECK-NEXT: %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %zero64(s64)146 ; CHECK-NEXT: %ext:_(s32) = G_ZEXT %elt(s1)147 ; CHECK-NEXT: $w0 = COPY %ext(s32)148 ; CHECK-NEXT: RET_ReallyLR implicit $w0149 %x:_(<2 x s32>) = COPY $x0150 %one:_(s32) = G_CONSTANT i32 1151 %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one, %one152 %vec_and:_(<2 x s32>) = G_AND %x, %one_vec153 %zero:_(s32) = G_CONSTANT i32 0154 %zero64:_(s64) = G_CONSTANT i64 0155 %zero_vec:_(<2 x s32>) = G_BUILD_VECTOR %zero, %zero156 %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %vec_and(<2 x s32>), %zero_vec157 %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp, %zero64158 %ext:_(s32) = G_ZEXT %elt(s1)159 $w0 = COPY %ext(s32)160 RET_ReallyLR implicit $w0161 162...163---164name: apply_no_zext_or_trunc165alignment: 4166tracksRegLiveness: true167machineFunctionInfo: {}168body: |169 bb.0:170 liveins: $w0171 ; CHECK-LABEL: name: apply_no_zext_or_trunc172 ; CHECK: liveins: $w0173 ; CHECK-NEXT: {{ $}}174 ; CHECK-NEXT: %x:_(s32) = COPY $w0175 ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 1176 ; CHECK-NEXT: %known_zero_or_one:_(s32) = G_AND %x, %one177 ; CHECK-NEXT: %cmp:_(s32) = COPY %known_zero_or_one(s32)178 ; CHECK-NEXT: $w0 = COPY %cmp(s32)179 ; CHECK-NEXT: RET_ReallyLR implicit $w0180 %x:_(s32) = COPY $w0181 %one:_(s32) = G_CONSTANT i32 1182 %known_zero_or_one:_(s32) = G_AND %x, %one183 %zero:_(s32) = G_CONSTANT i32 0184 %cmp:_(s32) = G_ICMP intpred(ne), %known_zero_or_one(s32), %zero185 $w0 = COPY %cmp(s32)186 RET_ReallyLR implicit $w0187 188...189---190name: apply_wide_cmp191alignment: 4192tracksRegLiveness: true193machineFunctionInfo: {}194body: |195 bb.0:196 liveins: $w0197 ; CHECK-LABEL: name: apply_wide_cmp198 ; CHECK: liveins: $w0199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: %x:_(s64) = COPY $x0201 ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1202 ; CHECK-NEXT: %known_zero_or_one:_(s64) = G_AND %x, %one203 ; CHECK-NEXT: %cmp:_(s64) = COPY %known_zero_or_one(s64)204 ; CHECK-NEXT: %trunc:_(s32) = G_TRUNC %cmp(s64)205 ; CHECK-NEXT: $w0 = COPY %trunc(s32)206 ; CHECK-NEXT: RET_ReallyLR implicit $w0207 %x:_(s64) = COPY $x0208 %one:_(s64) = G_CONSTANT i64 1209 %known_zero_or_one:_(s64) = G_AND %x, %one210 %zero:_(s64) = G_CONSTANT i64 0211 %cmp:_(s64) = G_ICMP intpred(ne), %known_zero_or_one(s64), %zero212 %trunc:_(s32) = G_TRUNC %cmp213 $w0 = COPY %trunc(s32)214 RET_ReallyLR implicit $w0215 216...217---218name: apply_narrow_lhs219alignment: 4220tracksRegLiveness: true221machineFunctionInfo: {}222body: |223 bb.0:224 liveins: $w0225 ; CHECK-LABEL: name: apply_narrow_lhs226 ; CHECK: liveins: $w0227 ; CHECK-NEXT: {{ $}}228 ; CHECK-NEXT: %x:_(s32) = COPY $w0229 ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 1230 ; CHECK-NEXT: %known_zero_or_one:_(s32) = G_AND %x, %one231 ; CHECK-NEXT: %cmp:_(s64) = G_ZEXT %known_zero_or_one(s32)232 ; CHECK-NEXT: $x0 = COPY %cmp(s64)233 ; CHECK-NEXT: RET_ReallyLR implicit $x0234 %x:_(s32) = COPY $w0235 %one:_(s32) = G_CONSTANT i32 1236 %known_zero_or_one:_(s32) = G_AND %x, %one237 %zero:_(s32) = G_CONSTANT i32 0238 %cmp:_(s64) = G_ICMP intpred(ne), %known_zero_or_one(s32), %zero239 $x0 = COPY %cmp(s64)240 RET_ReallyLR implicit $x0241