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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s3--- |4 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"5 6 define void @sdiv_exact() { ret void }7 define void @sdiv_noexact() { ret void }8 define void @sdiv_exact_minsize() #0 { ret void }9 define void @div_v4s32() { ret void }10 define void @div_v4s32_splat() { ret void }11 12 attributes #0 = { minsize }13 14...15---16name: sdiv_exact17body: |18 bb.1:19 liveins: $w020 21 ; CHECK-LABEL: name: sdiv_exact22 ; CHECK: liveins: $w023 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w025 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 326 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -99114629927 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = exact G_ASHR [[COPY]], [[C]](s32)28 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ASHR]], [[C1]]29 ; CHECK-NEXT: $w0 = COPY [[MUL]](s32)30 ; CHECK-NEXT: RET_ReallyLR implicit $w031 %0:_(s32) = COPY $w032 %1:_(s32) = G_CONSTANT i32 10433 %2:_(s32) = exact G_SDIV %0, %134 $w0 = COPY %2(s32)35 RET_ReallyLR implicit $w036 37...38---39name: sdiv_noexact40body: |41 bb.1:42 liveins: $w043 44 ; CHECK-LABEL: name: sdiv_noexact45 ; CHECK: liveins: $w046 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w048 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 132152839949 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 550 ; CHECK-NEXT: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH [[COPY]], [[C]]51 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SMULH]], [[C1]](s32)52 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3153 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ASHR]], [[C2]](s32)54 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[LSHR]]55 ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)56 ; CHECK-NEXT: RET_ReallyLR implicit $w057 %0:_(s32) = COPY $w058 %1:_(s32) = G_CONSTANT i32 10459 %2:_(s32) = G_SDIV %0, %160 $w0 = COPY %2(s32)61 RET_ReallyLR implicit $w062 63...64---65name: sdiv_exact_minsize66body: |67 bb.1:68 liveins: $w069 70 ; CHECK-LABEL: name: sdiv_exact_minsize71 ; CHECK: liveins: $w072 ; CHECK-NEXT: {{ $}}73 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w074 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10475 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = exact G_SDIV [[COPY]], [[C]]76 ; CHECK-NEXT: $w0 = COPY [[SDIV]](s32)77 ; CHECK-NEXT: RET_ReallyLR implicit $w078 %0:_(s32) = COPY $w079 %1:_(s32) = G_CONSTANT i32 10480 %2:_(s32) = exact G_SDIV %0, %181 $w0 = COPY %2(s32)82 RET_ReallyLR implicit $w083 84...85---86name: div_v4s3287body: |88 bb.1:89 liveins: $q090 91 ; CHECK-LABEL: name: div_v4s3292 ; CHECK: liveins: $q093 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q095 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 396 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -99114629997 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 95443717798 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)99 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32), [[C1]](s32), [[C2]](s32)100 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<4 x s32>) = exact G_ASHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)101 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[ASHR]], [[BUILD_VECTOR1]]102 ; CHECK-NEXT: $q0 = COPY [[MUL]](<4 x s32>)103 ; CHECK-NEXT: RET_ReallyLR implicit $q0104 %0:_(<4 x s32>) = COPY $q0105 %c1:_(s32) = G_CONSTANT i32 104106 %c2:_(s32) = G_CONSTANT i32 72107 %1:_(<4 x s32>) = G_BUILD_VECTOR %c1(s32), %c2(s32), %c1(s32), %c2(s32)108 %3:_(<4 x s32>) = exact G_SDIV %0, %1109 $q0 = COPY %3(<4 x s32>)110 RET_ReallyLR implicit $q0111 112...113---114name: div_v4s32_splat115body: |116 bb.1:117 liveins: $q0118 119 ; CHECK-LABEL: name: div_v4s32_splat120 ; CHECK: liveins: $q0121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0123 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3124 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -991146299125 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)126 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)127 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<4 x s32>) = exact G_ASHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)128 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[ASHR]], [[BUILD_VECTOR1]]129 ; CHECK-NEXT: $q0 = COPY [[MUL]](<4 x s32>)130 ; CHECK-NEXT: RET_ReallyLR implicit $q0131 %0:_(<4 x s32>) = COPY $q0132 %c1:_(s32) = G_CONSTANT i32 104133 %1:_(<4 x s32>) = G_BUILD_VECTOR %c1(s32), %c1(s32), %c1(s32), %c1(s32)134 %3:_(<4 x s32>) = exact G_SDIV %0, %1135 $q0 = COPY %3(<4 x s32>)136 RET_ReallyLR implicit $q0137 138...139