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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3---4name: shl_by_ge_bw5alignment: 46tracksRegLiveness: true7liveins:8 - { reg: '$w0' }9body: |10 bb.1:11 liveins: $w012 13 ; CHECK-LABEL: name: shl_by_ge_bw14 ; CHECK: liveins: $w015 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF17 ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)18 ; CHECK-NEXT: RET_ReallyLR implicit $w019 %1:_(s32) = COPY $w020 %0:_(s16) = G_TRUNC %1(s32)21 %2:_(s16) = G_CONSTANT i16 2022 %3:_(s16) = G_SHL %0, %2(s16)23 %4:_(s32) = G_ANYEXT %3(s16)24 $w0 = COPY %4(s32)25 RET_ReallyLR implicit $w026 27...28---29name: lshr_by_ge_bw30alignment: 431tracksRegLiveness: true32liveins:33 - { reg: '$w0' }34body: |35 bb.1:36 liveins: $w037 38 ; CHECK-LABEL: name: lshr_by_ge_bw39 ; CHECK: liveins: $w040 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF42 ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)43 ; CHECK-NEXT: RET_ReallyLR implicit $w044 %1:_(s32) = COPY $w045 %0:_(s16) = G_TRUNC %1(s32)46 %2:_(s16) = G_CONSTANT i16 1647 %3:_(s16) = G_LSHR %0, %2(s16)48 %4:_(s32) = G_ANYEXT %3(s16)49 $w0 = COPY %4(s32)50 RET_ReallyLR implicit $w051 52...53---54name: ashr_by_ge_bw55alignment: 456tracksRegLiveness: true57liveins:58 - { reg: '$w0' }59body: |60 bb.1:61 liveins: $w062 63 ; CHECK-LABEL: name: ashr_by_ge_bw64 ; CHECK: liveins: $w065 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF67 ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)68 ; CHECK-NEXT: RET_ReallyLR implicit $w069 %1:_(s32) = COPY $w070 %0:_(s16) = G_TRUNC %1(s32)71 %2:_(s16) = G_CONSTANT i16 2072 %3:_(s16) = G_ASHR %0, %2(s16)73 %4:_(s32) = G_ANYEXT %3(s16)74 $w0 = COPY %4(s32)75 RET_ReallyLR implicit $w076 77...78---79name: shl_by_ge_bw_vector80alignment: 481tracksRegLiveness: true82liveins:83 - { reg: '$q0' }84body: |85 bb.1:86 liveins: $q087 88 ; CHECK-LABEL: name: shl_by_ge_bw_vector89 ; CHECK: liveins: $q090 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: %shl:_(<4 x s32>) = G_IMPLICIT_DEF92 ; CHECK-NEXT: $q0 = COPY %shl(<4 x s32>)93 ; CHECK-NEXT: RET_ReallyLR implicit $q094 %1:_(<4 x s32>) = COPY $q095 %0:_(s32) = G_CONSTANT i32 3296 %bv:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %097 %shl:_(<4 x s32>) = G_SHL %1, %bv(<4 x s32>)98 $q0 = COPY %shl(<4 x s32>)99 RET_ReallyLR implicit $q0100 101...102---103name: shl_by_ge_bw_vector_partial104alignment: 4105tracksRegLiveness: true106liveins:107 - { reg: '$q0' }108body: |109 bb.1:110 liveins: $q0111 112 ; CHECK-LABEL: name: shl_by_ge_bw_vector_partial113 ; CHECK: liveins: $q0114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0116 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32117 ; CHECK-NEXT: %small:_(s32) = G_CONSTANT i32 4118 ; CHECK-NEXT: %bv:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), %small(s32)119 ; CHECK-NEXT: %shl:_(<4 x s32>) = G_SHL [[COPY]], %bv(<4 x s32>)120 ; CHECK-NEXT: $q0 = COPY %shl(<4 x s32>)121 ; CHECK-NEXT: RET_ReallyLR implicit $q0122 %1:_(<4 x s32>) = COPY $q0123 %0:_(s32) = G_CONSTANT i32 32124 %small:_(s32) = G_CONSTANT i32 4125 %bv:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %small126 %shl:_(<4 x s32>) = G_SHL %1, %bv(<4 x s32>)127 $q0 = COPY %shl(<4 x s32>)128 RET_ReallyLR implicit $q0129...130