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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s3---4name: udiv_by_scalar_const5body: |6 bb.1:7 liveins: $w08 ; CHECK-LABEL: name: udiv_by_scalar_const9 ; CHECK: liveins: $w010 ; CHECK-NEXT: {{ $}}11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w012 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 113 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 81808900914 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 215 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)16 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[LSHR]], [[C1]]17 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UMULH]], [[C2]](s32)18 ; CHECK-NEXT: $w0 = COPY [[LSHR1]](s32)19 %0:_(s32) = COPY $w020 %cst:_(s32) = G_CONSTANT i32 4221 %2:_(s32) = G_UDIV %0(s32), %cst(s32)22 $w0 = COPY %2(s32)23...24---25name: combine_vec_udiv_uniform26alignment: 427tracksRegLiveness: true28liveins:29 - { reg: '$q0' }30body: |31 bb.1:32 liveins: $q033 34 ; CHECK-LABEL: name: combine_vec_udiv_uniform35 ; CHECK: liveins: $q036 ; CHECK-NEXT: {{ $}}37 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q038 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2564539 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 440 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)41 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16)42 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[COPY]], [[BUILD_VECTOR]]43 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY]], [[UMULH]]44 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 145 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C2]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16)46 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[SUB]], [[BUILD_VECTOR2]](<8 x s16>)47 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LSHR]], [[UMULH]]48 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[ADD]], [[BUILD_VECTOR1]](<8 x s16>)49 ; CHECK-NEXT: $q0 = COPY [[LSHR1]](<8 x s16>)50 ; CHECK-NEXT: RET_ReallyLR implicit $q051 %0:_(<8 x s16>) = COPY $q052 %2:_(s16) = G_CONSTANT i16 2353 %1:_(<8 x s16>) = G_BUILD_VECTOR %2(s16), %2(s16), %2(s16), %2(s16), %2(s16), %2(s16), %2(s16), %2(s16)54 %3:_(<8 x s16>) = G_UDIV %0, %155 $q0 = COPY %3(<8 x s16>)56 RET_ReallyLR implicit $q057 58...59---60name: combine_vec_udiv_nonuniform61alignment: 462tracksRegLiveness: true63liveins:64 - { reg: '$q0' }65body: |66 bb.1:67 liveins: $q068 69 ; CHECK-LABEL: name: combine_vec_udiv_nonuniform70 ; CHECK: liveins: $q071 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q073 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -3276874 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 075 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2564576 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 477 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -385578 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 579 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 819580 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 1381 ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 382 ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 936383 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 51284 ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 -3276785 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 1586 ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s16) = G_CONSTANT i16 -3263987 ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s16) = G_CONSTANT i16 288 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C8]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16)89 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C2]](s16), [[C4]](s16), [[C6]](s16), [[C9]](s16), [[C10]](s16), [[C11]](s16), [[C13]](s16), [[C14]](s16)90 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16), [[C1]](s16)91 ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C3]](s16), [[C5]](s16), [[C7]](s16), [[C1]](s16), [[C1]](s16), [[C12]](s16), [[C12]](s16), [[C1]](s16)92 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<8 x s16>)93 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[LSHR]], [[BUILD_VECTOR1]]94 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY]], [[UMULH]]95 ; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[SUB]], [[BUILD_VECTOR2]]96 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UMULH1]], [[UMULH]]97 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[ADD]], [[BUILD_VECTOR3]](<8 x s16>)98 ; CHECK-NEXT: $q0 = COPY [[LSHR1]](<8 x s16>)99 ; CHECK-NEXT: RET_ReallyLR implicit $q0100 %0:_(<8 x s16>) = COPY $q0101 %2:_(s16) = G_CONSTANT i16 23102 %3:_(s16) = G_CONSTANT i16 34103 %4:_(s16) = G_CONSTANT i16 -23104 %5:_(s16) = G_CONSTANT i16 56105 %6:_(s16) = G_CONSTANT i16 128106 %7:_(s16) = G_CONSTANT i16 -1107 %8:_(s16) = G_CONSTANT i16 -256108 %9:_(s16) = G_CONSTANT i16 -32768109 %1:_(<8 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16), %4(s16), %5(s16), %6(s16), %7(s16), %8(s16), %9(s16)110 %10:_(<8 x s16>) = G_UDIV %0, %1111 $q0 = COPY %10(<8 x s16>)112 RET_ReallyLR implicit $q0113 114...115---116name: combine_vec_udiv_nonuniform2117alignment: 4118tracksRegLiveness: true119liveins:120 - { reg: '$q0' }121body: |122 bb.1:123 liveins: $q0124 125 ; CHECK-LABEL: name: combine_vec_udiv_nonuniform2126 ; CHECK: liveins: $q0127 ; CHECK-NEXT: {{ $}}128 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0129 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1130 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 16393131 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0132 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 13133 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -5617134 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 5135 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 -7281136 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32749137 ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 15138 ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 -10347139 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 8197140 ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 -13107141 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32747142 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16), [[C2]](s16)143 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C4]](s16), [[C6]](s16), [[C7]](s16), [[C9]](s16), [[C10]](s16), [[C11]](s16), [[C12]](s16)144 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C3]](s16), [[C5]](s16), [[C5]](s16), [[C8]](s16), [[C5]](s16), [[C3]](s16), [[C5]](s16), [[C8]](s16)145 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<8 x s16>)146 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[LSHR]], [[BUILD_VECTOR1]]147 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[UMULH]], [[BUILD_VECTOR2]](<8 x s16>)148 ; CHECK-NEXT: $q0 = COPY [[LSHR1]](<8 x s16>)149 ; CHECK-NEXT: RET_ReallyLR implicit $q0150 %0:_(<8 x s16>) = COPY $q0151 %2:_(s16) = G_CONSTANT i16 -34152 %3:_(s16) = G_CONSTANT i16 35153 %4:_(s16) = G_CONSTANT i16 36154 %5:_(s16) = G_CONSTANT i16 -37155 %6:_(s16) = G_CONSTANT i16 38156 %7:_(s16) = G_CONSTANT i16 -39157 %8:_(s16) = G_CONSTANT i16 40158 %9:_(s16) = G_CONSTANT i16 -41159 %1:_(<8 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16), %4(s16), %5(s16), %6(s16), %7(s16), %8(s16), %9(s16)160 %10:_(<8 x s16>) = G_UDIV %0, %1161 $q0 = COPY %10(<8 x s16>)162 RET_ReallyLR implicit $q0163 164...165---166name: combine_vec_udiv_nonuniform3167alignment: 4168tracksRegLiveness: true169liveins:170 - { reg: '$q0' }171body: |172 bb.1:173 liveins: $q0174 175 ; CHECK-LABEL: name: combine_vec_udiv_nonuniform3176 ; CHECK: liveins: $q0177 ; CHECK-NEXT: {{ $}}178 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0179 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9363180 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 2181 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 25645182 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 4183 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 18351184 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 12137185 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 2115186 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 23705187 ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 5188 ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 1041189 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 517190 ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 6191 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C2]](s16), [[C4]](s16), [[C5]](s16), [[C6]](s16), [[C7]](s16), [[C9]](s16), [[C10]](s16)192 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C3]](s16), [[C3]](s16), [[C3]](s16), [[C3]](s16), [[C8]](s16), [[C8]](s16), [[C11]](s16)193 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[COPY]], [[BUILD_VECTOR]]194 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY]], [[UMULH]]195 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 1196 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C12]](s16), [[C12]](s16), [[C12]](s16), [[C12]](s16), [[C12]](s16), [[C12]](s16), [[C12]](s16), [[C12]](s16)197 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[SUB]], [[BUILD_VECTOR2]](<8 x s16>)198 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LSHR]], [[UMULH]]199 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[ADD]], [[BUILD_VECTOR1]](<8 x s16>)200 ; CHECK-NEXT: $q0 = COPY [[LSHR1]](<8 x s16>)201 ; CHECK-NEXT: RET_ReallyLR implicit $q0202 %0:_(<8 x s16>) = COPY $q0203 %2:_(s16) = G_CONSTANT i16 7204 %3:_(s16) = G_CONSTANT i16 23205 %4:_(s16) = G_CONSTANT i16 25206 %5:_(s16) = G_CONSTANT i16 27207 %6:_(s16) = G_CONSTANT i16 31208 %7:_(s16) = G_CONSTANT i16 47209 %8:_(s16) = G_CONSTANT i16 63210 %9:_(s16) = G_CONSTANT i16 127211 %1:_(<8 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16), %4(s16), %5(s16), %6(s16), %7(s16), %8(s16), %9(s16)212 %10:_(<8 x s16>) = G_UDIV %0, %1213 $q0 = COPY %10(<8 x s16>)214 RET_ReallyLR implicit $q0215 216...217---218name: combine_vec_udiv_nonuniform4219alignment: 4220tracksRegLiveness: true221liveins:222 - { reg: '$q0' }223body: |224 bb.1:225 liveins: $q0226 227 ; CHECK-LABEL: name: combine_vec_udiv_nonuniform4228 ; CHECK: liveins: $q0229 ; CHECK-NEXT: {{ $}}230 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0231 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0232 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 -85233 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 7234 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C1]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)235 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)236 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<16 x s8>) = G_UMULH [[COPY]], [[BUILD_VECTOR]]237 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<16 x s8>) = G_LSHR [[UMULH]], [[BUILD_VECTOR1]](<16 x s8>)238 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 false239 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true240 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s1>) = G_BUILD_VECTOR [[C3]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1), [[C4]](s1)241 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(<16 x s8>) = G_SELECT [[BUILD_VECTOR2]](<16 x s1>), [[COPY]], [[LSHR]]242 ; CHECK-NEXT: $q0 = COPY [[SELECT]](<16 x s8>)243 ; CHECK-NEXT: RET_ReallyLR implicit $q0244 %0:_(<16 x s8>) = COPY $q0245 %2:_(s8) = G_CONSTANT i8 -64246 %3:_(s8) = G_CONSTANT i8 1247 %1:_(<16 x s8>) = G_BUILD_VECTOR %2(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8)248 %4:_(<16 x s8>) = G_UDIV %0, %1249 $q0 = COPY %4(<16 x s8>)250 RET_ReallyLR implicit $q0251 252...253---254name: pr38477255alignment: 4256tracksRegLiveness: true257liveins:258 - { reg: '$q0' }259body: |260 bb.1:261 liveins: $q0262 263 ; CHECK-LABEL: name: pr38477264 ; CHECK: liveins: $q0265 ; CHECK-NEXT: {{ $}}266 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0267 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0268 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 4957269 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768270 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 6271 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -8079272 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 4103273 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 12274 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 16385275 ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 14276 ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 -29991277 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 2048278 ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 2115279 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 4280 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C1]](s16), [[C4]](s16), [[C5]](s16), [[C7]](s16), [[C9]](s16), [[C10]](s16), [[C11]](s16)281 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C2]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C2]](s16)282 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C3]](s16), [[C3]](s16), [[C6]](s16), [[C8]](s16), [[C3]](s16), [[C]](s16), [[C12]](s16)283 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[COPY]], [[BUILD_VECTOR]]284 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY]], [[UMULH]]285 ; CHECK-NEXT: [[UMULH1:%[0-9]+]]:_(<8 x s16>) = G_UMULH [[SUB]], [[BUILD_VECTOR1]]286 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UMULH1]], [[UMULH]]287 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<8 x s16>) = G_LSHR [[ADD]], [[BUILD_VECTOR2]](<8 x s16>)288 ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s1) = G_CONSTANT i1 true289 ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s1) = G_CONSTANT i1 false290 ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<8 x s1>) = G_BUILD_VECTOR [[C13]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1), [[C14]](s1)291 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(<8 x s16>) = G_SELECT [[BUILD_VECTOR3]](<8 x s1>), [[COPY]], [[LSHR]]292 ; CHECK-NEXT: $q0 = COPY [[SELECT]](<8 x s16>)293 ; CHECK-NEXT: RET_ReallyLR implicit $q0294 %0:_(<8 x s16>) = COPY $q0295 %2:_(s16) = G_CONSTANT i16 1296 %3:_(s16) = G_CONSTANT i16 119297 %4:_(s16) = G_CONSTANT i16 73298 %5:_(s16) = G_CONSTANT i16 -111299 %6:_(s16) = G_CONSTANT i16 -3300 %7:_(s16) = G_CONSTANT i16 118301 %8:_(s16) = G_CONSTANT i16 32302 %9:_(s16) = G_CONSTANT i16 31303 %1:_(<8 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16), %4(s16), %5(s16), %6(s16), %7(s16), %8(s16), %9(s16)304 %10:_(<8 x s16>) = G_UDIV %0, %1305 $q0 = COPY %10(<8 x s16>)306 RET_ReallyLR implicit $q0307...308---309name: udiv_exact310body: |311 bb.1:312 liveins: $w0313 314 ; CHECK-LABEL: name: udiv_exact315 ; CHECK: liveins: $w0316 ; CHECK-NEXT: {{ $}}317 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0318 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3319 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -991146299320 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[COPY]], [[C]](s32)321 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]322 ; CHECK-NEXT: $w0 = COPY [[MUL]](s32)323 ; CHECK-NEXT: RET_ReallyLR implicit $w0324 %0:_(s32) = COPY $w0325 %1:_(s32) = G_CONSTANT i32 104326 %2:_(s32) = exact G_UDIV %0, %1327 $w0 = COPY %2(s32)328 RET_ReallyLR implicit $w0329 330...331---332name: udiv_noexact333body: |334 bb.1:335 liveins: $w0336 337 ; CHECK-LABEL: name: udiv_noexact338 ; CHECK: liveins: $w0339 ; CHECK-NEXT: {{ $}}340 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0341 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1321528399342 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5343 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[C]]344 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UMULH]], [[C1]](s32)345 ; CHECK-NEXT: $w0 = COPY [[LSHR]](s32)346 ; CHECK-NEXT: RET_ReallyLR implicit $w0347 %0:_(s32) = COPY $w0348 %1:_(s32) = G_CONSTANT i32 104349 %2:_(s32) = G_UDIV %0, %1350 $w0 = COPY %2(s32)351 RET_ReallyLR implicit $w0352 353...354---355name: udiv_exact_minsize356body: |357 bb.1:358 liveins: $w0359 360 ; CHECK-LABEL: name: udiv_exact_minsize361 ; CHECK: liveins: $w0362 ; CHECK-NEXT: {{ $}}363 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0364 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3365 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -991146299366 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = exact G_LSHR [[COPY]], [[C]](s32)367 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]]368 ; CHECK-NEXT: $w0 = COPY [[MUL]](s32)369 ; CHECK-NEXT: RET_ReallyLR implicit $w0370 %0:_(s32) = COPY $w0371 %1:_(s32) = G_CONSTANT i32 104372 %2:_(s32) = exact G_UDIV %0, %1373 $w0 = COPY %2(s32)374 RET_ReallyLR implicit $w0375 376...377---378name: div_v4s32379body: |380 bb.1:381 liveins: $q0382 383 ; CHECK-LABEL: name: div_v4s32384 ; CHECK: liveins: $q0385 ; CHECK-NEXT: {{ $}}386 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0387 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3388 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -991146299389 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 954437177390 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)391 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32), [[C1]](s32), [[C2]](s32)392 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = exact G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)393 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[LSHR]], [[BUILD_VECTOR1]]394 ; CHECK-NEXT: $q0 = COPY [[MUL]](<4 x s32>)395 ; CHECK-NEXT: RET_ReallyLR implicit $q0396 %0:_(<4 x s32>) = COPY $q0397 %c1:_(s32) = G_CONSTANT i32 104398 %c2:_(s32) = G_CONSTANT i32 72399 %1:_(<4 x s32>) = G_BUILD_VECTOR %c1(s32), %c2(s32), %c1(s32), %c2(s32)400 %3:_(<4 x s32>) = exact G_UDIV %0, %1401 $q0 = COPY %3(<4 x s32>)402 RET_ReallyLR implicit $q0403 404...405---406name: div_v4s32_splat407body: |408 bb.1:409 liveins: $q0410 411 ; CHECK-LABEL: name: div_v4s32_splat412 ; CHECK: liveins: $q0413 ; CHECK-NEXT: {{ $}}414 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0415 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3416 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -991146299417 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)418 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)419 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = exact G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)420 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[LSHR]], [[BUILD_VECTOR1]]421 ; CHECK-NEXT: $q0 = COPY [[MUL]](<4 x s32>)422 ; CHECK-NEXT: RET_ReallyLR implicit $q0423 %0:_(<4 x s32>) = COPY $q0424 %c1:_(s32) = G_CONSTANT i32 104425 %1:_(<4 x s32>) = G_BUILD_VECTOR %c1(s32), %c1(s32), %c1(s32), %c1(s32)426 %3:_(<4 x s32>) = exact G_UDIV %0, %1427 $q0 = COPY %3(<4 x s32>)428 RET_ReallyLR implicit $q0429 430...431