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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s3#4# Verify the following:5#6# - We can fold compares into selects.7# - This only happens when the result of the compare is only used by selects.8#9# Also verify that, for now:10#11# - We only support condition flags that require a single instruction.12#13 14...15---16name: fcmp_more_than_one_user_no_fold17alignment: 418legalized: true19regBankSelected: true20tracksRegLiveness: true21body: |22 bb.0:23 liveins: $s0, $s1, $w124 25 ; CHECK-LABEL: name: fcmp_more_than_one_user_no_fold26 ; CHECK: liveins: $s0, $s1, $w127 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s029 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s130 ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS031 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr32 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv33 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[CSINCWr]], 0, implicit-def $nzcv34 ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv35 ; CHECK-NEXT: $w1 = COPY [[CSINCWr]]36 ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]37 ; CHECK-NEXT: RET_ReallyLR implicit $s038 %0:fpr(s32) = COPY $s039 %1:fpr(s32) = COPY $s140 %2:fpr(s32) = G_FCONSTANT float 0.000000e+0041 %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %242 %4:fpr(s32) = G_SELECT %5, %2, %143 $w1 = COPY %5(s32)44 $s0 = COPY %4(s32)45 RET_ReallyLR implicit $s046 47...48---49name: fcmp_more_than_one_select50alignment: 451legalized: true52regBankSelected: true53tracksRegLiveness: true54body: |55 bb.0:56 liveins: $s0, $s1, $w157 58 ; CHECK-LABEL: name: fcmp_more_than_one_select59 ; CHECK: liveins: $s0, $s1, $w160 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s062 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s163 ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS064 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr65 ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv66 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr67 ; CHECK-NEXT: [[FCSELSrrr1:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv68 ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]69 ; CHECK-NEXT: $s1 = COPY [[FCSELSrrr1]]70 ; CHECK-NEXT: RET_ReallyLR implicit $s071 %0:fpr(s32) = COPY $s072 %1:fpr(s32) = COPY $s173 %2:fpr(s32) = G_FCONSTANT float 0.000000e+0074 %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %275 %4:fpr(s32) = G_SELECT %5, %2, %176 %7:fpr(s32) = G_SELECT %5, %1, %277 $s0 = COPY %4(s32)78 $s1 = COPY %7(s32)79 RET_ReallyLR implicit $s080 81...82---83name: using_icmp84alignment: 485legalized: true86regBankSelected: true87tracksRegLiveness: true88body: |89 bb.0:90 liveins: $s0, $w091 92 ; CHECK-LABEL: name: using_icmp93 ; CHECK: liveins: $s0, $w094 ; CHECK-NEXT: {{ $}}95 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w096 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s097 ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS098 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv99 ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv100 ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]101 ; CHECK-NEXT: RET_ReallyLR implicit $s0102 %0:gpr(s32) = COPY $w0103 %1:fpr(s32) = COPY $s0104 %2:gpr(s32) = G_CONSTANT i32 0105 %5:fpr(s32) = G_FCONSTANT float 0.000000e+00106 %6:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2107 %4:fpr(s32) = G_SELECT %6, %1, %5108 $s0 = COPY %4(s32)109 RET_ReallyLR implicit $s0110 111...112---113name: foeq114alignment: 4115legalized: true116regBankSelected: true117tracksRegLiveness: true118body: |119 bb.0:120 liveins: $s0, $s1121 122 ; CHECK-LABEL: name: foeq123 ; CHECK: liveins: $s0, $s1124 ; CHECK-NEXT: {{ $}}125 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0126 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1127 ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0128 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr129 ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv130 ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]131 ; CHECK-NEXT: RET_ReallyLR implicit $s0132 %0:fpr(s32) = COPY $s0133 %1:fpr(s32) = COPY $s1134 %2:fpr(s32) = G_FCONSTANT float 0.000000e+00135 %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2136 %4:fpr(s32) = G_SELECT %5, %2, %1137 $s0 = COPY %4(s32)138 RET_ReallyLR implicit $s0139 140...141---142name: fueq143alignment: 4144legalized: true145regBankSelected: true146tracksRegLiveness: true147body: |148 bb.0:149 liveins: $s0, $s1150 151 ; CHECK-LABEL: name: fueq152 ; CHECK: liveins: $s0, $s1153 ; CHECK-NEXT: {{ $}}154 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0155 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1156 ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0157 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr158 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv159 ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv160 ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]161 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv162 ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv163 ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]164 ; CHECK-NEXT: RET_ReallyLR implicit $s0165 %0:fpr(s32) = COPY $s0166 %1:fpr(s32) = COPY $s1167 %2:fpr(s32) = G_FCONSTANT float 0.000000e+00168 %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s32), %2169 %4:fpr(s32) = G_SELECT %5, %2, %1170 $s0 = COPY %4(s32)171 RET_ReallyLR implicit $s0172 173...174---175name: fone176alignment: 4177legalized: true178regBankSelected: true179tracksRegLiveness: true180body: |181 bb.0:182 liveins: $s0, $s1183 184 ; CHECK-LABEL: name: fone185 ; CHECK: liveins: $s0, $s1186 ; CHECK-NEXT: {{ $}}187 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0188 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1189 ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0190 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr191 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv192 ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv193 ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]194 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv195 ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv196 ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]197 ; CHECK-NEXT: RET_ReallyLR implicit $s0198 %0:fpr(s32) = COPY $s0199 %1:fpr(s32) = COPY $s1200 %2:fpr(s32) = G_FCONSTANT float 0.000000e+00201 %5:gpr(s32) = G_FCMP floatpred(one), %0(s32), %2202 %4:fpr(s32) = G_SELECT %5, %1, %2203 $s0 = COPY %4(s32)204 RET_ReallyLR implicit $s0205 206...207---208name: fune209alignment: 4210legalized: true211regBankSelected: true212tracksRegLiveness: true213body: |214 bb.0:215 liveins: $s0, $s1216 217 ; CHECK-LABEL: name: fune218 ; CHECK: liveins: $s0, $s1219 ; CHECK-NEXT: {{ $}}220 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0221 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1222 ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0223 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr224 ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv225 ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]226 ; CHECK-NEXT: RET_ReallyLR implicit $s0227 %0:fpr(s32) = COPY $s0228 %1:fpr(s32) = COPY $s1229 %2:fpr(s32) = G_FCONSTANT float 0.000000e+00230 %5:gpr(s32) = G_FCMP floatpred(une), %0(s32), %2231 %4:fpr(s32) = G_SELECT %5, %1, %2232 $s0 = COPY %4(s32)233 RET_ReallyLR implicit $s0234 235...236---237name: doeq238alignment: 4239legalized: true240regBankSelected: true241tracksRegLiveness: true242body: |243 bb.0:244 liveins: $d0, $d1245 246 ; CHECK-LABEL: name: doeq247 ; CHECK: liveins: $d0, $d1248 ; CHECK-NEXT: {{ $}}249 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0250 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1251 ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0252 ; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr253 ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv254 ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]255 ; CHECK-NEXT: RET_ReallyLR implicit $d0256 %0:fpr(s64) = COPY $d0257 %1:fpr(s64) = COPY $d1258 %2:fpr(s64) = G_FCONSTANT double 0.000000e+00259 %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2260 %4:fpr(s64) = G_SELECT %5, %2, %1261 $d0 = COPY %4(s64)262 RET_ReallyLR implicit $d0263 264...265---266name: dueq267alignment: 4268legalized: true269regBankSelected: true270tracksRegLiveness: true271body: |272 bb.0:273 liveins: $d0, $d1274 275 ; CHECK-LABEL: name: dueq276 ; CHECK: liveins: $d0, $d1277 ; CHECK-NEXT: {{ $}}278 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0279 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1280 ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0281 ; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr282 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv283 ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv284 ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]285 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv286 ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv287 ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]288 ; CHECK-NEXT: RET_ReallyLR implicit $d0289 %0:fpr(s64) = COPY $d0290 %1:fpr(s64) = COPY $d1291 %2:fpr(s64) = G_FCONSTANT double 0.000000e+00292 %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s64), %2293 %4:fpr(s64) = G_SELECT %5, %2, %1294 $d0 = COPY %4(s64)295 RET_ReallyLR implicit $d0296 297...298---299name: done300alignment: 4301legalized: true302regBankSelected: true303tracksRegLiveness: true304body: |305 bb.0:306 liveins: $d0, $d1307 308 ; CHECK-LABEL: name: done309 ; CHECK: liveins: $d0, $d1310 ; CHECK-NEXT: {{ $}}311 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0312 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1313 ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0314 ; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr315 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv316 ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv317 ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]318 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[ORRWrr]], 0, implicit-def $nzcv319 ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv320 ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]321 ; CHECK-NEXT: RET_ReallyLR implicit $d0322 %0:fpr(s64) = COPY $d0323 %1:fpr(s64) = COPY $d1324 %2:fpr(s64) = G_FCONSTANT double 0.000000e+00325 %5:gpr(s32) = G_FCMP floatpred(one), %0(s64), %2326 %4:fpr(s64) = G_SELECT %5, %1, %2327 $d0 = COPY %4(s64)328 RET_ReallyLR implicit $d0329 330...331---332name: dune333alignment: 4334legalized: true335regBankSelected: true336tracksRegLiveness: true337body: |338 bb.0:339 liveins: $d0, $d1340 341 ; CHECK-LABEL: name: dune342 ; CHECK: liveins: $d0, $d1343 ; CHECK-NEXT: {{ $}}344 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0345 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1346 ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0347 ; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr348 ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv349 ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]350 ; CHECK-NEXT: RET_ReallyLR implicit $d0351 %0:fpr(s64) = COPY $d0352 %1:fpr(s64) = COPY $d1353 %2:fpr(s64) = G_FCONSTANT double 0.000000e+00354 %5:gpr(s32) = G_FCMP floatpred(une), %0(s64), %2355 %4:fpr(s64) = G_SELECT %5, %1, %2356 $d0 = COPY %4(s64)357 RET_ReallyLR implicit $d0358 359...360---361name: copy_from_physreg362alignment: 4363legalized: true364regBankSelected: true365tracksRegLiveness: true366body: |367 bb.0:368 liveins: $s0, $w0, $w1369 370 ; CHECK-LABEL: name: copy_from_physreg371 ; CHECK: liveins: $s0, $w0, $w1372 ; CHECK-NEXT: {{ $}}373 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0374 ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0375 ; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0376 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[FMOVS0_]]377 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY1]], 0, implicit-def $nzcv378 ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY]], [[FMOVS0_]], 1, implicit $nzcv379 ; CHECK-NEXT: BL @copy_from_physreg, implicit-def $w0380 ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]381 ; CHECK-NEXT: RET_ReallyLR implicit $s0382 %0:gpr(s32) = COPY $w0383 %1:fpr(s32) = COPY $s0384 %5:fpr(s32) = G_FCONSTANT float 0.000000e+00385 BL @copy_from_physreg, implicit-def $w0386 %4:fpr(s32) = G_SELECT %5, %1, %5387 BL @copy_from_physreg, implicit-def $w0388 $s0 = COPY %4(s32)389 RET_ReallyLR implicit $s0390 391...392