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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s3#4# Verify that we can fold compares into integer selects.5#6# This is an integer version of fold-fp-select.mir.7#8 9...10---11name: eq12alignment: 413legalized: true14regBankSelected: true15tracksRegLiveness: true16body: |17 bb.0:18 liveins: $w0, $w119 20 ; CHECK-LABEL: name: eq21 ; CHECK: liveins: $w0, $w122 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w024 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w125 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr26 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv27 ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY1]], 0, implicit $nzcv28 ; CHECK-NEXT: $w0 = COPY [[CSELWr]]29 ; CHECK-NEXT: RET_ReallyLR implicit $w030 %0:gpr(s32) = COPY $w031 %1:gpr(s32) = COPY $w132 %2:gpr(s32) = G_CONSTANT i32 033 %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %234 %4:gpr(s32) = G_SELECT %5, %2, %135 $w0 = COPY %4(s32)36 RET_ReallyLR implicit $w037 38...39---40name: using_fcmp41alignment: 442legalized: true43regBankSelected: true44tracksRegLiveness: true45body: |46 bb.0:47 liveins: $s0, $w0, $w148 49 ; CHECK-LABEL: name: using_fcmp50 ; CHECK: liveins: $s0, $w0, $w151 ; CHECK-NEXT: {{ $}}52 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w153 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s054 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr55 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY1]], implicit-def $nzcv, implicit $fpcr56 ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY]], 0, implicit $nzcv57 ; CHECK-NEXT: $w0 = COPY [[CSELWr]]58 ; CHECK-NEXT: RET_ReallyLR implicit $w059 %1:gpr(s32) = COPY $w160 %2:fpr(s32) = COPY $s061 %3:fpr(s32) = G_FCONSTANT float 0.000000e+0062 %6:gpr(s32) = G_CONSTANT i32 063 %7:gpr(s32) = G_FCMP floatpred(oeq), %2(s32), %364 %5:gpr(s32) = G_SELECT %7, %6, %165 $w0 = COPY %5(s32)66 RET_ReallyLR implicit $w067 68...69---70name: csinc71alignment: 472legalized: true73regBankSelected: true74tracksRegLiveness: true75body: |76 bb.0:77 liveins: $w0, $w178 79 ; CHECK-LABEL: name: csinc80 ; CHECK: liveins: $w0, $w181 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w083 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv84 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY]], $wzr, 0, implicit $nzcv85 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]86 ; CHECK-NEXT: RET_ReallyLR implicit $w087 %0:gpr(s32) = COPY $w088 %1:gpr(s32) = COPY $w189 %2:gpr(s32) = G_CONSTANT i32 190 %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %291 %4:gpr(s32) = G_SELECT %5, %0, %292 $w0 = COPY %4(s32)93 RET_ReallyLR implicit $w094...95