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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s3 4# PR363455--- |6 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7 target triple = "aarch64"8 9 ; Function Attrs: noinline nounwind optnone10 define void @fp16_to_gpr([2 x half], ptr %addr) {11 ret void12 }13 14 define void @gpr_to_fp16() {15 ret void16 }17 18 define void @gpr_to_fp16_physreg() {19 ret void20 }21...22---23name: fp16_to_gpr24alignment: 425legalized: true26regBankSelected: true27tracksRegLiveness: true28registers:29 - { id: 0, class: gpr }30 - { id: 1, class: fpr }31 - { id: 2, class: fpr }32 - { id: 3, class: gpr }33 - { id: 4, class: gpr }34 - { id: 5, class: gpr }35 - { id: 6, class: gpr }36 - { id: 7, class: gpr }37 - { id: 8, class: gpr }38 - { id: 9, class: gpr }39 - { id: 10, class: gpr }40 - { id: 11, class: gpr }41 - { id: 12, class: gpr }42body: |43 bb.1 (%ir-block.1):44 liveins: $h0, $h1, $x045 46 ; CHECK-LABEL: name: fp16_to_gpr47 ; CHECK: liveins: $h0, $h1, $x048 ; CHECK-NEXT: {{ $}}49 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h050 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h151 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF52 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub53 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]54 ; CHECK-NEXT: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY2]], 0, 1555 ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub56 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG1]]57 ; CHECK-NEXT: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY3]], 16, 1558 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64sp = COPY $x059 ; CHECK-NEXT: STRWui [[BFMWri1]], [[COPY4]], 0 :: (store (s32) into %ir.addr, align 2)60 ; CHECK-NEXT: RET_ReallyLR61 %1:fpr(s16) = COPY $h062 %2:fpr(s16) = COPY $h163 %3:gpr(s32) = G_IMPLICIT_DEF64 %11:gpr(s16) = COPY %1(s16)65 %4:gpr(s32) = G_INSERT %3, %11(s16), 066 %12:gpr(s16) = COPY %2(s16)67 %5:gpr(s32) = G_INSERT %4, %12(s16), 1668 %0:gpr(s32) = COPY %5(s32)69 %6:gpr(p0) = COPY $x070 G_STORE %0(s32), %6(p0) :: (store (s32) into %ir.addr, align 2)71 RET_ReallyLR72 73...74 75---76name: gpr_to_fp1677alignment: 478legalized: true79regBankSelected: true80tracksRegLiveness: true81registers:82 - { id: 0, class: gpr }83 - { id: 1, class: gpr }84 - { id: 2, class: fpr }85body: |86 bb.1 (%ir-block.0):87 liveins: $w088 89 ; CHECK-LABEL: name: gpr_to_fp1690 ; CHECK: liveins: $w091 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w093 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]94 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub95 ; CHECK-NEXT: $h0 = COPY [[COPY2]]96 ; CHECK-NEXT: RET_ReallyLR implicit $h097 %0:gpr(s32) = COPY $w098 %1:gpr(s16) = G_TRUNC %0(s32)99 %2:fpr(s16) = COPY %1(s16)100 $h0 = COPY %2(s16)101 RET_ReallyLR implicit $h0102 103...104---105name: gpr_to_fp16_physreg106alignment: 4107legalized: true108regBankSelected: true109tracksRegLiveness: true110registers:111 - { id: 0, class: gpr }112 - { id: 1, class: gpr }113body: |114 bb.1 (%ir-block.0):115 liveins: $w0116 117 ; CHECK-LABEL: name: gpr_to_fp16_physreg118 ; CHECK: liveins: $w0119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0121 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]122 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub123 ; CHECK-NEXT: $h0 = COPY [[COPY2]]124 ; CHECK-NEXT: RET_ReallyLR implicit $h0125 %0:gpr(s32) = COPY $w0126 %1:gpr(s16) = G_TRUNC %0(s32)127 $h0 = COPY %1(s16)128 RET_ReallyLR implicit $h0129 130...131