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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3--- |4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5 target triple = "aarch64"6 7 define void @test_ms1(ptr nocapture %dst, i32 %c, i32 %len) local_unnamed_addr #0 {8 entry:9 %0 = trunc i32 %c to i810 %conv = zext i32 %len to i6411 tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 %0, i64 %conv, i1 false)12 ret void13 }14 15 declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #116 17 define void @test_ms2_const(ptr nocapture %dst, i32 %c) local_unnamed_addr #0 {18 entry:19 %0 = trunc i32 %c to i820 tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 %0, i64 16, i1 false)21 ret void22 }23 24 define void @test_zero_const(ptr nocapture %dst) local_unnamed_addr #0 {25 entry:26 tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 0, i64 64, i1 false)27 ret void28 }29 30 define void @test_ms3_const_both(ptr nocapture %dst) local_unnamed_addr #0 {31 entry:32 tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 64, i64 16, i1 false)33 ret void34 }35 36 define void @test_ms_vector(ptr nocapture %dst, i32 %c) local_unnamed_addr #0 {37 entry:38 %0 = trunc i32 %c to i839 tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 %0, i64 16, i1 false)40 ret void41 }42 43 define void @test_ms4_const_both_unaligned(ptr nocapture %dst) local_unnamed_addr #0 {44 entry:45 tail call void @llvm.memset.p0.i64(ptr align 1 %dst, i8 64, i64 18, i1 false)46 ret void47 }48 49 define void @minsize(ptr nocapture %dst) minsize { unreachable }50 51 declare void @llvm.stackprotector(ptr, ptr) #252 53 attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cyclone" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2" "use-soft-float"="false" }54 attributes #1 = { argmemonly nounwind }55 56...57---58name: test_ms159alignment: 460tracksRegLiveness: true61body: |62 bb.1.entry:63 liveins: $w1, $w2, $x064 65 ; CHECK-LABEL: name: test_ms166 ; CHECK: liveins: $w1, $w2, $x067 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x069 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w170 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w271 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)72 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)73 ; CHECK-NEXT: G_MEMSET [[COPY]](p0), [[TRUNC]](s8), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst)74 ; CHECK-NEXT: RET_ReallyLR75 %0:_(p0) = COPY $x076 %1:_(s32) = COPY $w177 %2:_(s32) = COPY $w278 %3:_(s8) = G_TRUNC %1(s32)79 %4:_(s64) = G_ZEXT %2(s32)80 G_MEMSET %0(p0), %3(s8), %4(s64), 1 :: (store (s8) into %ir.dst)81 RET_ReallyLR82 83...84---85name: test_ms2_const86alignment: 487tracksRegLiveness: true88body: |89 bb.1.entry:90 liveins: $w1, $x091 92 ; CHECK-LABEL: name: test_ms2_const93 ; CHECK: liveins: $w1, $x094 ; CHECK-NEXT: {{ $}}95 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x096 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w197 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)98 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)99 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673100 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]101 ; CHECK-NEXT: G_STORE [[MUL]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)102 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8103 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)104 ; CHECK-NEXT: G_STORE [[MUL]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)105 ; CHECK-NEXT: RET_ReallyLR106 %0:_(p0) = COPY $x0107 %1:_(s32) = COPY $w1108 %3:_(s64) = G_CONSTANT i64 16109 %2:_(s8) = G_TRUNC %1(s32)110 G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)111 RET_ReallyLR112 113...114---115name: test_zero_const116alignment: 4117tracksRegLiveness: true118body: |119 bb.1.entry:120 liveins: $w1, $x0121 122 ; CHECK-LABEL: name: test_zero_const123 ; CHECK: liveins: $w1, $x0124 ; CHECK-NEXT: {{ $}}125 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0126 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0127 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)128 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)129 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16130 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)131 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %ir.dst + 16, align 1)132 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32133 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)134 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into %ir.dst + 32, align 1)135 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 48136 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)137 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into %ir.dst + 48, align 1)138 ; CHECK-NEXT: RET_ReallyLR139 %0:_(p0) = COPY $x0140 %1:_(s32) = G_CONSTANT i32 0141 %3:_(s64) = G_CONSTANT i64 64142 %2:_(s8) = G_TRUNC %1(s32)143 G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)144 RET_ReallyLR145 146...147 148---149name: test_ms3_const_both150alignment: 4151tracksRegLiveness: true152body: |153 bb.1.entry:154 liveins: $x0155 156 ; CHECK-LABEL: name: test_ms3_const_both157 ; CHECK: liveins: $x0158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0160 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4629771061636907072161 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)162 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8163 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)164 ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)165 ; CHECK-NEXT: RET_ReallyLR166 %0:_(p0) = COPY $x0167 %1:_(s8) = G_CONSTANT i8 64168 %2:_(s64) = G_CONSTANT i64 16169 G_MEMSET %0(p0), %1(s8), %2(s64), 1 :: (store (s8) into %ir.dst)170 RET_ReallyLR171 172...173---174name: test_ms_vector175alignment: 4176tracksRegLiveness: true177body: |178 bb.1.entry:179 liveins: $w1, $x0180 181 ; CHECK-LABEL: name: test_ms_vector182 ; CHECK: liveins: $w1, $x0183 ; CHECK-NEXT: {{ $}}184 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0185 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1186 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)187 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)188 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673189 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]190 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MUL]](s64), [[MUL]](s64)191 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.dst, align 1)192 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16193 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)194 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %ir.dst + 16, align 1)195 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32196 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C2]](s64)197 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD1]](p0) :: (store (<2 x s64>) into %ir.dst + 32, align 1)198 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 44199 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)200 ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[PTR_ADD2]](p0) :: (store (<2 x s64>) into %ir.dst + 44, align 1)201 ; CHECK-NEXT: RET_ReallyLR202 %0:_(p0) = COPY $x0203 %1:_(s32) = COPY $w1204 %3:_(s64) = G_CONSTANT i64 60205 %2:_(s8) = G_TRUNC %1(s32)206 G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)207 RET_ReallyLR208 209...210---211name: test_ms4_const_both_unaligned212alignment: 4213tracksRegLiveness: true214body: |215 bb.1.entry:216 liveins: $x0217 218 ; CHECK-LABEL: name: test_ms4_const_both_unaligned219 ; CHECK: liveins: $x0220 ; CHECK-NEXT: {{ $}}221 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0222 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4629771061636907072223 ; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)224 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8225 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)226 ; CHECK-NEXT: G_STORE [[C]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)227 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 16448228 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16229 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C3]](s64)230 ; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.dst + 16, align 1)231 ; CHECK-NEXT: RET_ReallyLR232 %0:_(p0) = COPY $x0233 %1:_(s8) = G_CONSTANT i8 64234 %2:_(s64) = G_CONSTANT i64 18235 G_MEMSET %0(p0), %1(s8), %2(s64), 1 :: (store (s8) into %ir.dst)236 RET_ReallyLR237 238...239---240name: minsize241alignment: 4242tracksRegLiveness: true243body: |244 bb.0:245 liveins: $w1, $x0246 ; CHECK-LABEL: name: minsize247 ; CHECK: liveins: $w1, $x0248 ; CHECK-NEXT: {{ $}}249 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0250 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1251 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)252 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s8)253 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 72340172838076673254 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]255 ; CHECK-NEXT: G_STORE [[MUL]](s64), [[COPY]](p0) :: (store (s64) into %ir.dst, align 1)256 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8257 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)258 ; CHECK-NEXT: G_STORE [[MUL]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.dst + 8, align 1)259 ; CHECK-NEXT: RET_ReallyLR260 %0:_(p0) = COPY $x0261 %1:_(s32) = COPY $w1262 %3:_(s64) = G_CONSTANT i64 16263 %2:_(s8) = G_TRUNC %1(s32)264 G_MEMSET %0(p0), %2(s8), %3(s64), 1 :: (store (s8) into %ir.dst)265 RET_ReallyLR266