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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -stop-after=irtranslator -mtriple=aarch64-- -verify-machineinstrs -o - %s | FileCheck %s3 4define i16 @smul_fix(i16 %arg0, i16 %arg1) {5  ; CHECK-LABEL: name: smul_fix6  ; CHECK: bb.1 (%ir-block.0):7  ; CHECK:   liveins: $w0, $w18  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w09  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)10  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w111  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)12  ; CHECK:   [[SMULFIX:%[0-9]+]]:_(s16) = G_SMULFIX [[TRUNC]], [[TRUNC1]], 713  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMULFIX]](s16)14  ; CHECK:   $w0 = COPY [[ANYEXT]](s32)15  ; CHECK:   RET_ReallyLR implicit $w016  %res = call i16 @llvm.smul.fix.i16(i16 %arg0, i16 %arg1, i32 7)17  ret i16 %res18}19 20define i16 @umul_fix(i16 %arg0, i16 %arg1) {21  ; CHECK-LABEL: name: umul_fix22  ; CHECK: bb.1 (%ir-block.0):23  ; CHECK:   liveins: $w0, $w124  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w025  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)26  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w127  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)28  ; CHECK:   [[UMULFIX:%[0-9]+]]:_(s16) = G_UMULFIX [[TRUNC]], [[TRUNC1]], 729  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMULFIX]](s16)30  ; CHECK:   $w0 = COPY [[ANYEXT]](s32)31  ; CHECK:   RET_ReallyLR implicit $w032  %res = call i16 @llvm.umul.fix.i16(i16 %arg0, i16 %arg1, i32 7)33  ret i16 %res34}35 36define i16 @smul_fix_sat(i16 %arg0, i16 %arg1) {37  ; CHECK-LABEL: name: smul_fix_sat38  ; CHECK: bb.1 (%ir-block.0):39  ; CHECK:   liveins: $w0, $w140  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w041  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)42  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w143  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)44  ; CHECK:   [[SMULFIXSAT:%[0-9]+]]:_(s16) = G_SMULFIXSAT [[TRUNC]], [[TRUNC1]], 745  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMULFIXSAT]](s16)46  ; CHECK:   $w0 = COPY [[ANYEXT]](s32)47  ; CHECK:   RET_ReallyLR implicit $w048  %res = call i16 @llvm.smul.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)49  ret i16 %res50}51 52define i16 @umul_fix_sat(i16 %arg0, i16 %arg1) {53  ; CHECK-LABEL: name: umul_fix_sat54  ; CHECK: bb.1 (%ir-block.0):55  ; CHECK:   liveins: $w0, $w156  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w057  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)58  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w159  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)60  ; CHECK:   [[UMULFIXSAT:%[0-9]+]]:_(s16) = G_UMULFIXSAT [[TRUNC]], [[TRUNC1]], 761  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMULFIXSAT]](s16)62  ; CHECK:   $w0 = COPY [[ANYEXT]](s32)63  ; CHECK:   RET_ReallyLR implicit $w064  %res = call i16 @llvm.umul.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)65  ret i16 %res66}67 68define i16 @sdiv_fix(i16 %arg0, i16 %arg1) {69  ; CHECK-LABEL: name: sdiv_fix70  ; CHECK: bb.1 (%ir-block.0):71  ; CHECK:   liveins: $w0, $w172  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w073  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)74  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w175  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)76  ; CHECK:   [[SDIVFIX:%[0-9]+]]:_(s16) = G_SDIVFIX [[TRUNC]], [[TRUNC1]], 777  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SDIVFIX]](s16)78  ; CHECK:   $w0 = COPY [[ANYEXT]](s32)79  ; CHECK:   RET_ReallyLR implicit $w080  %res = call i16 @llvm.sdiv.fix.i16(i16 %arg0, i16 %arg1, i32 7)81  ret i16 %res82}83 84define i16 @udiv_fix(i16 %arg0, i16 %arg1) {85  ; CHECK-LABEL: name: udiv_fix86  ; CHECK: bb.1 (%ir-block.0):87  ; CHECK:   liveins: $w0, $w188  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w089  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)90  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w191  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)92  ; CHECK:   [[UDIVFIX:%[0-9]+]]:_(s16) = G_UDIVFIX [[TRUNC]], [[TRUNC1]], 793  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UDIVFIX]](s16)94  ; CHECK:   $w0 = COPY [[ANYEXT]](s32)95  ; CHECK:   RET_ReallyLR implicit $w096  %res = call i16 @llvm.udiv.fix.i16(i16 %arg0, i16 %arg1, i32 7)97  ret i16 %res98}99 100define i16 @sdiv_fix_sat(i16 %arg0, i16 %arg1) {101  ; CHECK-LABEL: name: sdiv_fix_sat102  ; CHECK: bb.1 (%ir-block.0):103  ; CHECK:   liveins: $w0, $w1104  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0105  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)106  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1107  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)108  ; CHECK:   [[SDIVFIXSAT:%[0-9]+]]:_(s16) = G_SDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7109  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SDIVFIXSAT]](s16)110  ; CHECK:   $w0 = COPY [[ANYEXT]](s32)111  ; CHECK:   RET_ReallyLR implicit $w0112  %res = call i16 @llvm.sdiv.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)113  ret i16 %res114}115 116define i16 @udiv_fix_sat(i16 %arg0, i16 %arg1) {117  ; CHECK-LABEL: name: udiv_fix_sat118  ; CHECK: bb.1 (%ir-block.0):119  ; CHECK:   liveins: $w0, $w1120  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0121  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)122  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1123  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)124  ; CHECK:   [[UDIVFIXSAT:%[0-9]+]]:_(s16) = G_UDIVFIXSAT [[TRUNC]], [[TRUNC1]], 7125  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UDIVFIXSAT]](s16)126  ; CHECK:   $w0 = COPY [[ANYEXT]](s32)127  ; CHECK:   RET_ReallyLR implicit $w0128  %res = call i16 @llvm.udiv.fix.sat.i16(i16 %arg0, i16 %arg1, i32 7)129  ret i16 %res130}131 132declare i16 @llvm.smul.fix.i16(i16, i16, i32 immarg) #0133declare i16 @llvm.umul.fix.i16(i16, i16, i32 immarg) #0134declare i16 @llvm.smul.fix.sat.i16(i16, i16, i32 immarg) #0135declare i16 @llvm.umul.fix.sat.i16(i16, i16, i32 immarg) #0136declare i16 @llvm.sdiv.fix.i16(i16, i16, i32 immarg) #1137declare i16 @llvm.udiv.fix.i16(i16, i16, i32 immarg) #1138declare i16 @llvm.sdiv.fix.sat.i16(i16, i16, i32 immarg) #1139declare i16 @llvm.udiv.fix.sat.i16(i16, i16, i32 immarg) #1140 141attributes #0 = { nounwind readnone speculatable willreturn }142attributes #1 = { nounwind readnone }143