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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=aarch64-darwin-ios13 -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s3 4define void @asm_simple_memory_clobber() {5 ; CHECK-LABEL: name: asm_simple_memory_clobber6 ; CHECK: bb.1 (%ir-block.0):7 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, !08 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, !09 ; CHECK-NEXT: RET_ReallyLR10 call void asm sideeffect "", "~{memory}"(), !srcloc !011 call void asm sideeffect "", ""(), !srcloc !012 ret void13}14 15!0 = !{i32 70}16 17define void @asm_simple_register_clobber() {18 ; CHECK-LABEL: name: asm_simple_register_clobber19 ; CHECK: bb.1 (%ir-block.0):20 ; CHECK-NEXT: INLINEASM &"mov x0, 7", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $x0, !021 ; CHECK-NEXT: RET_ReallyLR22 call void asm sideeffect "mov x0, 7", "~{x0}"(), !srcloc !023 ret void24}25 26define i64 @asm_register_early_clobber() {27 ; CHECK-LABEL: name: asm_register_early_clobber28 ; CHECK: bb.1 (%ir-block.0):29 ; CHECK-NEXT: INLINEASM &"mov $0, 7; mov $1, 7", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %0, {{[0-9]+}} /* regdef-ec:GPR64common */, def early-clobber %1, !030 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY %031 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %132 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]33 ; CHECK-NEXT: $x0 = COPY [[ADD]](s64)34 ; CHECK-NEXT: RET_ReallyLR implicit $x035 call { i64, i64 } asm sideeffect "mov $0, 7; mov $1, 7", "=&r,=&r"(), !srcloc !036 %asmresult = extractvalue { i64, i64 } %1, 037 %asmresult1 = extractvalue { i64, i64 } %1, 138 %add = add i64 %asmresult, %asmresult139 ret i64 %add40}41 42define i32 @test_specific_register_output() nounwind ssp {43 ; CHECK-LABEL: name: test_specific_register_output44 ; CHECK: bb.1.entry:45 ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $w046 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w047 ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)48 ; CHECK-NEXT: RET_ReallyLR implicit $w049entry:50 %0 = tail call i32 asm "mov ${0:w}, 7", "={w0}"() nounwind51 ret i32 %052}53 54define i32 @test_single_register_output() nounwind ssp {55 ; CHECK-LABEL: name: test_single_register_output56 ; CHECK: bb.1.entry:57 ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %058 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %059 ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)60 ; CHECK-NEXT: RET_ReallyLR implicit $w061entry:62 %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind63 ret i32 %064}65 66define i64 @test_single_register_output_s64() nounwind ssp {67 ; CHECK-LABEL: name: test_single_register_output_s6468 ; CHECK: bb.1.entry:69 ; CHECK-NEXT: INLINEASM &"mov $0, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR64common */, def %070 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY %071 ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)72 ; CHECK-NEXT: RET_ReallyLR implicit $x073entry:74 %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind75 ret i64 %076}77 78; Check support for returning several floats79define float @test_multiple_register_outputs_same() #0 {80 ; CHECK-LABEL: name: test_multiple_register_outputs_same81 ; CHECK: bb.1 (%ir-block.0):82 ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:GPR32common */, def %183 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %084 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %185 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]86 ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)87 ; CHECK-NEXT: RET_ReallyLR implicit $s088 %1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"()89 %asmresult = extractvalue { float, float } %1, 090 %asmresult1 = extractvalue { float, float } %1, 191 %add = fadd float %asmresult, %asmresult192 ret float %add93}94 95; Check support for returning several floats96define double @test_multiple_register_outputs_mixed() #0 {97 ; CHECK-LABEL: name: test_multiple_register_outputs_mixed98 ; CHECK: bb.1 (%ir-block.0):99 ; CHECK-NEXT: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %0101 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %1102 ; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)103 ; CHECK-NEXT: RET_ReallyLR implicit $d0104 %1 = call { float, double } asm "mov $0, #0; mov $1, #0", "=r,=w"()105 %asmresult = extractvalue { float, double } %1, 1106 ret double %asmresult107}108 109define i32 @test_specific_register_output_trunc() nounwind ssp {110 ; CHECK-LABEL: name: test_specific_register_output_trunc111 ; CHECK: bb.1.entry:112 ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $x0113 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0114 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)115 ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)116 ; CHECK-NEXT: RET_ReallyLR implicit $w0117entry:118 %0 = tail call i32 asm "mov ${0:w}, 7", "={x0}"() nounwind119 ret i32 %0120}121 122define zeroext i8 @test_register_output_trunc(ptr %src) nounwind {123 ; CHECK-LABEL: name: test_register_output_trunc124 ; CHECK: bb.1.entry:125 ; CHECK-NEXT: liveins: $x0126 ; CHECK-NEXT: {{ $}}127 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0128 ; CHECK-NEXT: INLINEASM &"mov ${0:w}, 32", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1129 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1130 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)131 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)132 ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)133 ; CHECK-NEXT: RET_ReallyLR implicit $w0134entry:135 %0 = tail call i8 asm "mov ${0:w}, 32", "=r"() nounwind136 ret i8 %0137}138 139define float @test_vector_output() nounwind {140 ; CHECK-LABEL: name: test_vector_output141 ; CHECK: bb.1 (%ir-block.0):142 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0143 ; CHECK-NEXT: INLINEASM &"fmov ${0}.2s, #1.0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $d14144 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d14145 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s64)146 ; CHECK-NEXT: $s0 = COPY [[EVEC]](s32)147 ; CHECK-NEXT: RET_ReallyLR implicit $s0148 %1 = tail call <2 x float> asm sideeffect "fmov ${0}.2s, #1.0", "={v14}"() nounwind149 %2 = extractelement <2 x float> %1, i32 0150 ret float %2151}152 153define void @test_input_register_imm() {154 ; CHECK-LABEL: name: test_input_register_imm155 ; CHECK: bb.1 (%ir-block.0):156 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42157 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY [[C]](s64)158 ; CHECK-NEXT: INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, {{[0-9]+}} /* reguse:GPR64common */, [[COPY]]159 ; CHECK-NEXT: RET_ReallyLR160 call void asm sideeffect "mov x0, $0", "r"(i64 42)161 ret void162}163 164; Make sure that boolean immediates are properly (zero) extended.165define i32 @test_boolean_imm_ext() {166 ; CHECK-LABEL: name: test_boolean_imm_ext167 ; CHECK: bb.1.entry:168 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1169 ; CHECK-NEXT: INLINEASM &"#TEST 42 + ${0:c} - .\0A\09", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 1170 ; CHECK-NEXT: $w0 = COPY [[C]](s32)171 ; CHECK-NEXT: RET_ReallyLR implicit $w0172entry:173 tail call void asm sideeffect "#TEST 42 + ${0:c} - .\0A\09", "i"(i1 true)174 ret i32 1175}176 177define void @test_input_imm() {178 ; CHECK-LABEL: name: test_input_imm179 ; CHECK: bb.1 (%ir-block.0):180 ; CHECK-NEXT: INLINEASM &"mov x0, $0", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42181 ; CHECK-NEXT: RET_ReallyLR182 call void asm sideeffect "mov x0, $0", "i"(i64 42)183 ret void184}185 186define zeroext i8 @test_input_register(ptr %src) nounwind {187 ; CHECK-LABEL: name: test_input_register188 ; CHECK: bb.1.entry:189 ; CHECK-NEXT: liveins: $x0190 ; CHECK-NEXT: {{ $}}191 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0192 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]](p0)193 ; CHECK-NEXT: INLINEASM &"ldtrb ${0:w}, [$1]", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, {{[0-9]+}} /* reguse:GPR64common */, [[COPY1]]194 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %1195 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)196 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)197 ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)198 ; CHECK-NEXT: RET_ReallyLR implicit $w0199entry:200 %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(ptr %src) nounwind201 ret i8 %0202}203 204define i32 @test_memory_constraint(ptr %a) nounwind {205 ; CHECK-LABEL: name: test_memory_constraint206 ; CHECK: bb.1 (%ir-block.0):207 ; CHECK-NEXT: liveins: $x0208 ; CHECK-NEXT: {{ $}}209 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0210 ; CHECK-NEXT: INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %1, 262158 /* mem:m */, [[COPY]](p0)211 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %1212 ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)213 ; CHECK-NEXT: RET_ReallyLR implicit $w0214 %1 = tail call i32 asm "ldr $0, $1", "=r,*m"(ptr elementtype(i32) %a)215 ret i32 %1216}217 218define i16 @test_anyext_input() {219 ; CHECK-LABEL: name: test_anyext_input220 ; CHECK: bb.1 (%ir-block.0):221 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1222 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)223 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)224 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, {{[0-9]+}} /* reguse:GPR32common */, [[COPY]]225 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0226 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)227 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)228 ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](s32)229 ; CHECK-NEXT: RET_ReallyLR implicit $w0230 %1 = call i16 asm sideeffect "", "=r,r"(i16 1)231 ret i16 %1232}233 234define i16 @test_anyext_input_with_matching_constraint() {235 ; CHECK-LABEL: name: test_anyext_input_with_matching_constraint236 ; CHECK: bb.1 (%ir-block.0):237 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1238 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)239 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)240 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0, 2147483657 /* reguse tiedto:$0 */, [[COPY]](tied-def 3)241 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %0242 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)243 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)244 ; CHECK-NEXT: $w0 = COPY [[ANYEXT1]](s32)245 ; CHECK-NEXT: RET_ReallyLR implicit $w0246 %1 = call i16 asm sideeffect "", "=r,0"(i16 1)247 ret i16 %1248}249 250define i64 @test_input_with_matching_constraint_to_physical_register() {251 ; CHECK-LABEL: name: test_input_with_matching_constraint_to_physical_register252 ; CHECK: bb.1 (%ir-block.0):253 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0254 ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, [[C]](tied-def 3)(s64)255 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x2256 ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)257 ; CHECK-NEXT: RET_ReallyLR implicit $x0258 %1 = tail call i64 asm "", "={x2},0"(i64 0)259 ret i64 %1260}261 262define void @test_indirectify_i32_value(i32 %x, i32 %y) {263 ; CHECK-LABEL: name: test_indirectify_i32_value264 ; CHECK: bb.1.entry:265 ; CHECK-NEXT: liveins: $w0, $w1266 ; CHECK-NEXT: {{ $}}267 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0268 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1269 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0270 ; CHECK-NEXT: G_STORE [[COPY]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %stack.0)271 ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1272 ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %stack.1)273 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)274 ; CHECK-NEXT: RET_ReallyLR275entry:276 tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 %x, i32 %y)277 ret void278}279 280define void @test_indirectify_i32_constant() {281 ; CHECK-LABEL: name: test_indirectify_i32_constant282 ; CHECK: bb.1.entry:283 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42284 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0285 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0286 ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %stack.0)287 ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1288 ; CHECK-NEXT: G_STORE [[C1]](s32), [[FRAME_INDEX1]](p0) :: (store (s32) into %stack.1)289 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0), 262158 /* mem:m */, [[FRAME_INDEX1]](p0)290 ; CHECK-NEXT: RET_ReallyLR291entry:292 tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 42, i32 0)293 ret void294}295 296define void @test_indirectify_i16_value(i16 %val) {297 ; CHECK-LABEL: name: test_indirectify_i16_value298 ; CHECK: bb.1.entry:299 ; CHECK-NEXT: liveins: $w0300 ; CHECK-NEXT: {{ $}}301 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0302 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)303 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0304 ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[FRAME_INDEX]](p0) :: (store (s16) into %stack.0)305 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)306 ; CHECK-NEXT: RET_ReallyLR307entry:308 tail call void asm sideeffect "", "imr,~{memory}"(i16 %val)309 ret void310}311 312define void @test_indirectify_i16_constant() {313 ; CHECK-LABEL: name: test_indirectify_i16_constant314 ; CHECK: bb.1.entry:315 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 42316 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0317 ; CHECK-NEXT: G_STORE [[C]](s16), [[FRAME_INDEX]](p0) :: (store (s16) into %stack.0)318 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)319 ; CHECK-NEXT: RET_ReallyLR320entry:321 tail call void asm sideeffect "", "imr,~{memory}"(i16 42)322 ret void323}324 325define void @test_indirectify_i64_value(i64 %val) {326 ; CHECK-LABEL: name: test_indirectify_i64_value327 ; CHECK: bb.1.entry:328 ; CHECK-NEXT: liveins: $x0329 ; CHECK-NEXT: {{ $}}330 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0331 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0332 ; CHECK-NEXT: G_STORE [[COPY]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %stack.0)333 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)334 ; CHECK-NEXT: RET_ReallyLR335entry:336 tail call void asm sideeffect "", "imr,~{memory}"(i64 %val)337 ret void338}339 340define void @test_indirectify_i64_constant() {341 ; CHECK-LABEL: name: test_indirectify_i64_constant342 ; CHECK: bb.1.entry:343 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42344 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0345 ; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %stack.0)346 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, {{[0-9]+}} /* mem:m */, [[FRAME_INDEX]](p0)347 ; CHECK-NEXT: RET_ReallyLR348entry:349 tail call void asm sideeffect "", "imr,~{memory}"(i64 42)350 ret void351}352 353; TODO: add more types354