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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=aarch64-- -mcpu=falkor -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s3 4define i32 @load_invariant(ptr %ptr) {5 ; CHECK-LABEL: name: load_invariant6 ; CHECK: bb.1 (%ir-block.0):7 ; CHECK-NEXT: liveins: $x08 ; CHECK-NEXT: {{ $}}9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x010 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load (s32) from %ir.ptr)11 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)12 ; CHECK-NEXT: RET_ReallyLR implicit $w013 %load = load i32, ptr %ptr, align 4, !invariant.load !014 ret i32 %load15}16 17define i32 @load_volatile_invariant(ptr %ptr) {18 ; CHECK-LABEL: name: load_volatile_invariant19 ; CHECK: bb.1 (%ir-block.0):20 ; CHECK-NEXT: liveins: $x021 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x023 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (volatile invariant load (s32) from %ir.ptr)24 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)25 ; CHECK-NEXT: RET_ReallyLR implicit $w026 %load = load volatile i32, ptr %ptr, align 4, !invariant.load !027 ret i32 %load28}29 30define i32 @load_dereferenceable(ptr dereferenceable(4) %ptr) {31 ; CHECK-LABEL: name: load_dereferenceable32 ; CHECK: bb.1 (%ir-block.0):33 ; CHECK-NEXT: liveins: $x034 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x036 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr)37 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)38 ; CHECK-NEXT: RET_ReallyLR implicit $w039 %load = load i32, ptr %ptr, align 440 ret i32 %load41}42 43define i32 @load_dereferenceable_invariant(ptr dereferenceable(4) %ptr) {44 ; CHECK-LABEL: name: load_dereferenceable_invariant45 ; CHECK: bb.1 (%ir-block.0):46 ; CHECK-NEXT: liveins: $x047 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x049 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load (s32) from %ir.ptr)50 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)51 ; CHECK-NEXT: RET_ReallyLR implicit $w052 %load = load i32, ptr %ptr, align 4, !invariant.load !053 ret i32 %load54}55 56define i32 @load_nontemporal(ptr %ptr) {57 ; CHECK-LABEL: name: load_nontemporal58 ; CHECK: bb.1 (%ir-block.0):59 ; CHECK-NEXT: liveins: $x060 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x062 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (non-temporal load (s32) from %ir.ptr)63 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)64 ; CHECK-NEXT: RET_ReallyLR implicit $w065 %load = load i32, ptr %ptr, align 4, !nontemporal !066 ret i32 %load67}68 69define i32 @load_falkor_strided_access(ptr %ptr) {70 ; CHECK-LABEL: name: load_falkor_strided_access71 ; CHECK: bb.1 (%ir-block.0):72 ; CHECK-NEXT: liveins: $x073 ; CHECK-NEXT: {{ $}}74 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x075 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load (s32) from %ir.ptr)76 ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)77 ; CHECK-NEXT: RET_ReallyLR implicit $w078 %load = load i32, ptr %ptr, align 4, !falkor.strided.access !079 ret i32 %load80}81 82!0 = !{}83