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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -disable-expand-reductions -stop-after=irtranslator %s -o - | FileCheck %s3 4define float @fadd_seq(float %start, <4 x float> %vec) {5 ; CHECK-LABEL: name: fadd_seq6 ; CHECK: bb.1 (%ir-block.0):7 ; CHECK-NEXT: liveins: $q1, $s08 ; CHECK-NEXT: {{ $}}9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s010 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q111 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)12 ; CHECK-NEXT: [[VECREDUCE_SEQ_FADD:%[0-9]+]]:_(s32) = G_VECREDUCE_SEQ_FADD [[COPY]](s32), [[BITCAST]](<4 x s32>)13 ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_SEQ_FADD]](s32)14 ; CHECK-NEXT: RET_ReallyLR implicit $s015 %res = call float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %vec)16 ret float %res17}18 19define float @fadd_seq_scalar(float %start, <1 x float> %vec) {20 ; CHECK-LABEL: name: fadd_seq_scalar21 ; CHECK: bb.1 (%ir-block.0):22 ; CHECK-NEXT: liveins: $d1, $s023 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s025 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d126 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)27 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[UV]]28 ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)29 ; CHECK-NEXT: RET_ReallyLR implicit $s030 %res = call float @llvm.vector.reduce.fadd.v1f32(float %start, <1 x float> %vec)31 ret float %res32}33 34define float @fadd_fast(float %start, <4 x float> %vec) {35 ; CHECK-LABEL: name: fadd_fast36 ; CHECK: bb.1 (%ir-block.0):37 ; CHECK-NEXT: liveins: $q1, $s038 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s040 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q141 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)42 ; CHECK-NEXT: [[VECREDUCE_FADD:%[0-9]+]]:_(s32) = reassoc G_VECREDUCE_FADD [[BITCAST]](<4 x s32>)43 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = reassoc G_FADD [[COPY]], [[VECREDUCE_FADD]]44 ; CHECK-NEXT: $s0 = COPY [[FADD]](s32)45 ; CHECK-NEXT: RET_ReallyLR implicit $s046 %res = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %vec)47 ret float %res48}49 50define double @fmul_seq(double %start, <4 x double> %vec) {51 ; CHECK-LABEL: name: fmul_seq52 ; CHECK: bb.1 (%ir-block.0):53 ; CHECK-NEXT: liveins: $d0, $q1, $q254 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d056 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q157 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q258 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>)59 ; CHECK-NEXT: [[VECREDUCE_SEQ_FMUL:%[0-9]+]]:_(s64) = G_VECREDUCE_SEQ_FMUL [[COPY]](s64), [[CONCAT_VECTORS]](<4 x s64>)60 ; CHECK-NEXT: $d0 = COPY [[VECREDUCE_SEQ_FMUL]](s64)61 ; CHECK-NEXT: RET_ReallyLR implicit $d062 %res = call double @llvm.vector.reduce.fmul.v4f64(double %start, <4 x double> %vec)63 ret double %res64}65 66define double @fmul_seq_scalar(double %start, <1 x double> %vec) {67 ; CHECK-LABEL: name: fmul_seq_scalar68 ; CHECK: bb.1 (%ir-block.0):69 ; CHECK-NEXT: liveins: $d0, $d170 ; CHECK-NEXT: {{ $}}71 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d072 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $d173 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]74 ; CHECK-NEXT: $d0 = COPY [[FMUL]](s64)75 ; CHECK-NEXT: RET_ReallyLR implicit $d076 %res = call double @llvm.vector.reduce.fmul.v1f64(double %start, <1 x double> %vec)77 ret double %res78}79 80define double @fmul_fast(double %start, <4 x double> %vec) {81 ; CHECK-LABEL: name: fmul_fast82 ; CHECK: bb.1 (%ir-block.0):83 ; CHECK-NEXT: liveins: $d0, $q1, $q284 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d086 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q187 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q288 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>)89 ; CHECK-NEXT: [[VECREDUCE_FMUL:%[0-9]+]]:_(s64) = reassoc G_VECREDUCE_FMUL [[CONCAT_VECTORS]](<4 x s64>)90 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = reassoc G_FMUL [[COPY]], [[VECREDUCE_FMUL]]91 ; CHECK-NEXT: $d0 = COPY [[FMUL]](s64)92 ; CHECK-NEXT: RET_ReallyLR implicit $d093 %res = call reassoc double @llvm.vector.reduce.fmul.v4f64(double %start, <4 x double> %vec)94 ret double %res95}96 97define float @fmax(<4 x float> %vec) {98 ; CHECK-LABEL: name: fmax99 ; CHECK: bb.1 (%ir-block.0):100 ; CHECK-NEXT: liveins: $q0101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0103 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)104 ; CHECK-NEXT: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAX [[BITCAST]](<4 x s32>)105 ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAX]](s32)106 ; CHECK-NEXT: RET_ReallyLR implicit $s0107 %res = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %vec)108 ret float %res109}110 111define float @fmin(<4 x float> %vec) {112 ; CHECK-LABEL: name: fmin113 ; CHECK: bb.1 (%ir-block.0):114 ; CHECK-NEXT: liveins: $q0115 ; CHECK-NEXT: {{ $}}116 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0117 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)118 ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_FMIN [[BITCAST]](<4 x s32>)119 ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](s32)120 ; CHECK-NEXT: RET_ReallyLR implicit $s0121 %res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %vec)122 ret float %res123}124 125define float @fmin_nnan(<4 x float> %vec) {126 ; CHECK-LABEL: name: fmin_nnan127 ; CHECK: bb.1 (%ir-block.0):128 ; CHECK-NEXT: liveins: $q0129 ; CHECK-NEXT: {{ $}}130 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0131 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)132 ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = nnan G_VECREDUCE_FMIN [[BITCAST]](<4 x s32>)133 ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](s32)134 ; CHECK-NEXT: RET_ReallyLR implicit $s0135 %res = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %vec)136 ret float %res137}138 139define float @fmaximum(<4 x float> %vec) {140 ; CHECK-LABEL: name: fmaximum141 ; CHECK: bb.1 (%ir-block.0):142 ; CHECK-NEXT: liveins: $q0143 ; CHECK-NEXT: {{ $}}144 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0145 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)146 ; CHECK-NEXT: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAXIMUM [[BITCAST]](<4 x s32>)147 ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMAXIMUM]](s32)148 ; CHECK-NEXT: RET_ReallyLR implicit $s0149 %res = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %vec)150 ret float %res151}152 153define float @fminimum(<4 x float> %vec) {154 ; CHECK-LABEL: name: fminimum155 ; CHECK: bb.1 (%ir-block.0):156 ; CHECK-NEXT: liveins: $q0157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0159 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)160 ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x s32>)161 ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](s32)162 ; CHECK-NEXT: RET_ReallyLR implicit $s0163 %res = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %vec)164 ret float %res165}166 167define float @fminimum_nnan(<4 x float> %vec) {168 ; CHECK-LABEL: name: fminimum_nnan169 ; CHECK: bb.1 (%ir-block.0):170 ; CHECK-NEXT: liveins: $q0171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0173 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)174 ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(s32) = nnan G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x s32>)175 ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](s32)176 ; CHECK-NEXT: RET_ReallyLR implicit $s0177 %res = call nnan float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %vec)178 ret float %res179}180 181define i32 @add(<4 x i32> %vec) {182 ; CHECK-LABEL: name: add183 ; CHECK: bb.1 (%ir-block.0):184 ; CHECK-NEXT: liveins: $q0185 ; CHECK-NEXT: {{ $}}186 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0187 ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[COPY]](<4 x s32>)188 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)189 ; CHECK-NEXT: RET_ReallyLR implicit $w0190 %res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %vec)191 ret i32 %res192}193 194define i32 @mul(<4 x i32> %vec) {195 ; CHECK-LABEL: name: mul196 ; CHECK: bb.1 (%ir-block.0):197 ; CHECK-NEXT: liveins: $q0198 ; CHECK-NEXT: {{ $}}199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0200 ; CHECK-NEXT: [[VECREDUCE_MUL:%[0-9]+]]:_(s32) = G_VECREDUCE_MUL [[COPY]](<4 x s32>)201 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_MUL]](s32)202 ; CHECK-NEXT: RET_ReallyLR implicit $w0203 %res = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %vec)204 ret i32 %res205}206 207define i32 @and(<4 x i32> %vec) {208 ; CHECK-LABEL: name: and209 ; CHECK: bb.1 (%ir-block.0):210 ; CHECK-NEXT: liveins: $q0211 ; CHECK-NEXT: {{ $}}212 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0213 ; CHECK-NEXT: [[VECREDUCE_AND:%[0-9]+]]:_(s32) = G_VECREDUCE_AND [[COPY]](<4 x s32>)214 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_AND]](s32)215 ; CHECK-NEXT: RET_ReallyLR implicit $w0216 %res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %vec)217 ret i32 %res218}219 220define i32 @or(<4 x i32> %vec) {221 ; CHECK-LABEL: name: or222 ; CHECK: bb.1 (%ir-block.0):223 ; CHECK-NEXT: liveins: $q0224 ; CHECK-NEXT: {{ $}}225 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0226 ; CHECK-NEXT: [[VECREDUCE_OR:%[0-9]+]]:_(s32) = G_VECREDUCE_OR [[COPY]](<4 x s32>)227 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_OR]](s32)228 ; CHECK-NEXT: RET_ReallyLR implicit $w0229 %res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %vec)230 ret i32 %res231}232 233define i32 @xor(<4 x i32> %vec) {234 ; CHECK-LABEL: name: xor235 ; CHECK: bb.1 (%ir-block.0):236 ; CHECK-NEXT: liveins: $q0237 ; CHECK-NEXT: {{ $}}238 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0239 ; CHECK-NEXT: [[VECREDUCE_XOR:%[0-9]+]]:_(s32) = G_VECREDUCE_XOR [[COPY]](<4 x s32>)240 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_XOR]](s32)241 ; CHECK-NEXT: RET_ReallyLR implicit $w0242 %res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %vec)243 ret i32 %res244}245 246define i32 @smax(<4 x i32> %vec) {247 ; CHECK-LABEL: name: smax248 ; CHECK: bb.1 (%ir-block.0):249 ; CHECK-NEXT: liveins: $q0250 ; CHECK-NEXT: {{ $}}251 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0252 ; CHECK-NEXT: [[VECREDUCE_SMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_SMAX [[COPY]](<4 x s32>)253 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMAX]](s32)254 ; CHECK-NEXT: RET_ReallyLR implicit $w0255 %res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)256 ret i32 %res257}258 259define i32 @smin(<4 x i32> %vec) {260 ; CHECK-LABEL: name: smin261 ; CHECK: bb.1 (%ir-block.0):262 ; CHECK-NEXT: liveins: $q0263 ; CHECK-NEXT: {{ $}}264 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0265 ; CHECK-NEXT: [[VECREDUCE_SMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_SMIN [[COPY]](<4 x s32>)266 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_SMIN]](s32)267 ; CHECK-NEXT: RET_ReallyLR implicit $w0268 %res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)269 ret i32 %res270}271 272define i32 @umax(<4 x i32> %vec) {273 ; CHECK-LABEL: name: umax274 ; CHECK: bb.1 (%ir-block.0):275 ; CHECK-NEXT: liveins: $q0276 ; CHECK-NEXT: {{ $}}277 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0278 ; CHECK-NEXT: [[VECREDUCE_UMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_UMAX [[COPY]](<4 x s32>)279 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMAX]](s32)280 ; CHECK-NEXT: RET_ReallyLR implicit $w0281 %res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)282 ret i32 %res283}284 285define i32 @umin(<4 x i32> %vec) {286 ; CHECK-LABEL: name: umin287 ; CHECK: bb.1 (%ir-block.0):288 ; CHECK-NEXT: liveins: $q0289 ; CHECK-NEXT: {{ $}}290 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0291 ; CHECK-NEXT: [[VECREDUCE_UMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_UMIN [[COPY]](<4 x s32>)292 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_UMIN]](s32)293 ; CHECK-NEXT: RET_ReallyLR implicit $w0294 %res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)295 ret i32 %res296}297