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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve -global-isel -stop-after=irtranslator -aarch64-enable-gisel-sve=1 %s -o - | FileCheck %s3 4define i32 @extract_v4i32_vector_insert_const(<4 x i32> %a, <2 x i32> %b, i32 %c) {5 ; CHECK-LABEL: name: extract_v4i32_vector_insert_const6 ; CHECK: bb.1.entry:7 ; CHECK-NEXT: liveins: $d1, $q0, $w08 ; CHECK-NEXT: {{ $}}9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q010 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d111 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w012 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 113 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x s32>), 014 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[C]](s64)15 ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)16 ; CHECK-NEXT: RET_ReallyLR implicit $w017entry:18 %vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)19 %d = extractelement <4 x i32> %vector, i32 120 ret i32 %d21}22 23define double @extract_v4double_vector_insert_const(<4 x double> %a, <2 x double> %b, i32 %c) {24 ; CHECK-LABEL: name: extract_v4double_vector_insert_const25 ; CHECK: bb.1.entry:26 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $w027 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q029 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q130 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)31 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q232 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w033 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 134 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s64>) = G_INSERT_SUBVECTOR [[CONCAT_VECTORS]], [[COPY2]](<2 x s64>), 035 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s64>), [[C]](s64)36 ; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)37 ; CHECK-NEXT: RET_ReallyLR implicit $d038entry:39 %vector = call <4 x double> @llvm.vector.insert.v4f64.v2f64(<4 x double> %a, <2 x double> %b, i64 0)40 %d = extractelement <4 x double> %vector, i32 141 ret double %d42}43 44define float @extract_v4float_vector_insert_const(<4 x float> %a, <2 x float> %b, i32 %c) {45 ; CHECK-LABEL: name: extract_v4float_vector_insert_const46 ; CHECK: bb.1.entry:47 ; CHECK-NEXT: liveins: $d1, $q0, $w048 ; CHECK-NEXT: {{ $}}49 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q050 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)51 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d152 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w053 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 154 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[BITCAST]], [[COPY1]](<2 x s32>), 055 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[C]](s64)56 ; CHECK-NEXT: $s0 = COPY [[EVEC]](s32)57 ; CHECK-NEXT: RET_ReallyLR implicit $s058entry:59 %vector = call <4 x float> @llvm.vector.insert.v4f32.v2f32(<4 x float> %a, <2 x float> %b, i64 0)60 %d = extractelement <4 x float> %vector, i32 161 ret float %d62}63 64define i32 @extract_v4i32_vector_insert(<4 x i32> %a, <2 x i32> %b, i32 %c) {65 ; CHECK-LABEL: name: extract_v4i32_vector_insert66 ; CHECK: bb.1.entry:67 ; CHECK-NEXT: liveins: $d1, $q0, $w068 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q070 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d171 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w072 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<2 x s32>), 073 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)74 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[INSERT_SUBVECTOR]](<4 x s32>), [[ZEXT]](s64)75 ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)76 ; CHECK-NEXT: RET_ReallyLR implicit $w077entry:78 %vector = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> %a, <2 x i32> %b, i64 0)79 %d = extractelement <4 x i32> %vector, i32 %c80 ret i32 %d81}82 83define i32 @extract_v4i32_vector_extract(<4 x i32> %a, <2 x i32> %b, i32 %c) {84 ; CHECK-LABEL: name: extract_v4i32_vector_extract85 ; CHECK: bb.1.entry:86 ; CHECK-NEXT: liveins: $d1, $q0, $w087 ; CHECK-NEXT: {{ $}}88 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q089 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d190 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w091 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<4 x s32>), 092 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)93 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[EXTRACT_SUBVECTOR]](<4 x s32>), [[ZEXT]](s64)94 ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)95 ; CHECK-NEXT: RET_ReallyLR implicit $w096entry:97 %vector = call <4 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %a, i64 0)98 %d = extractelement <4 x i32> %vector, i32 %c99 ret i32 %d100}101 102define i32 @extract_v4i32_vector_extract_const(<vscale x 4 x i32> %a, i32 %c, ptr %p) {103 ; CHECK-LABEL: name: extract_v4i32_vector_extract_const104 ; CHECK: bb.1.entry:105 ; CHECK-NEXT: liveins: $w0, $x1, $z0106 ; CHECK-NEXT: {{ $}}107 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0108 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0109 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1110 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1111 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 4 x s32>), 0112 ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 4 x s32>), [[COPY2]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)113 ; CHECK-NEXT: $w0 = COPY [[C]](s32)114 ; CHECK-NEXT: RET_ReallyLR implicit $w0115entry:116 %vector = call <vscale x 4 x i32> @llvm.vector.extract(<vscale x 4 x i32> %a, i64 0)117 store <vscale x 4 x i32> %vector, ptr %p, align 16118 ret i32 1119}120 121define i32 @extract_v2double_vector_extract_const(<vscale x 2 x double> %a, i32 %c, ptr %p) {122 ; CHECK-LABEL: name: extract_v2double_vector_extract_const123 ; CHECK: bb.1.entry:124 ; CHECK-NEXT: liveins: $w0, $x1, $z0125 ; CHECK-NEXT: {{ $}}126 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $z0127 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0128 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1129 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1130 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 2 x s64>), 0131 ; CHECK-NEXT: G_STORE [[EXTRACT_SUBVECTOR]](<vscale x 2 x s64>), [[COPY2]](p0) :: (store (<vscale x 2 x s64>) into %ir.p)132 ; CHECK-NEXT: $w0 = COPY [[C]](s32)133 ; CHECK-NEXT: RET_ReallyLR implicit $w0134entry:135 %vector = call <vscale x 2 x double> @llvm.vector.extract(<vscale x 2 x double> %a, i64 0)136 store <vscale x 2 x double> %vector, ptr %p, align 16137 ret i32 1138}139 140define i32 @extract_v4i32_vector_insert_const_vscale(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 %c, ptr %p) {141 ; CHECK-LABEL: name: extract_v4i32_vector_insert_const_vscale142 ; CHECK: bb.1.entry:143 ; CHECK-NEXT: liveins: $w0, $x1, $z0, $z1144 ; CHECK-NEXT: {{ $}}145 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0146 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z1147 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0148 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1149 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1150 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[COPY1]](<vscale x 4 x s32>), 0151 ; CHECK-NEXT: G_STORE [[INSERT_SUBVECTOR]](<vscale x 4 x s32>), [[COPY3]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)152 ; CHECK-NEXT: $w0 = COPY [[C]](s32)153 ; CHECK-NEXT: RET_ReallyLR implicit $w0154entry:155 %vector = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i64 0)156 store <vscale x 4 x i32> %vector, ptr %p, align 16157 ret i32 1158}159 160define i32 @extract_v4i32_vector_extract_const_illegal_fixed(<4 x i32> %a, ptr %p) {161 ; CHECK-LABEL: name: extract_v4i32_vector_extract_const_illegal_fixed162 ; CHECK: bb.1.entry:163 ; CHECK-NEXT: liveins: $q0, $x0164 ; CHECK-NEXT: {{ $}}165 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0166 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0167 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0168 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1169 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64)170 ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[COPY1]](p0) :: (store (s32) into %ir.p, align 16)171 ; CHECK-NEXT: $w0 = COPY [[C1]](s32)172 ; CHECK-NEXT: RET_ReallyLR implicit $w0173entry:174 %vector = call <1 x i32> @llvm.vector.extract(<4 x i32> %a, i64 0)175 store <1 x i32> %vector, ptr %p, align 16176 ret i32 1177}178 179define i32 @extract_v4i32_vector_extract_const_illegal_scalable(<vscale x 4 x i32> %a, ptr %p) {180 ; CHECK-LABEL: name: extract_v4i32_vector_extract_const_illegal_scalable181 ; CHECK: bb.1.entry:182 ; CHECK-NEXT: liveins: $x0, $z0183 ; CHECK-NEXT: {{ $}}184 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0185 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0186 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0187 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1188 ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1189 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]190 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s32>), [[MUL]](s64)191 ; CHECK-NEXT: G_STORE [[EVEC]](s32), [[COPY1]](p0) :: (store (s32) into %ir.p, align 16)192 ; CHECK-NEXT: $w0 = COPY [[C1]](s32)193 ; CHECK-NEXT: RET_ReallyLR implicit $w0194entry:195 %vector = call <1 x i32> @llvm.vector.extract(<vscale x 4 x i32> %a, i64 0)196 store <1 x i32> %vector, ptr %p, align 16197 ret i32 1198}199 200define i32 @extract_v4i32_vector_insert_const_illegal_scalable(<vscale x 4 x i32> %a, <1 x i32> %b, i32 %c, ptr %p) {201 ; CHECK-LABEL: name: extract_v4i32_vector_insert_const_illegal_scalable202 ; CHECK: bb.1.entry:203 ; CHECK-NEXT: liveins: $d1, $w0, $x1, $z0204 ; CHECK-NEXT: {{ $}}205 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $z0206 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1207 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)208 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0209 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1210 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0211 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1212 ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1213 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[VSCALE]], [[C]]214 ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](s32), [[MUL]](s64)215 ; CHECK-NEXT: G_STORE [[IVEC]](<vscale x 4 x s32>), [[COPY3]](p0) :: (store (<vscale x 4 x s32>) into %ir.p)216 ; CHECK-NEXT: $w0 = COPY [[C1]](s32)217 ; CHECK-NEXT: RET_ReallyLR implicit $w0218entry:219 %vector = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> %a, <1 x i32> %b, i64 0)220 store <vscale x 4 x i32> %vector, ptr %p, align 16221 ret i32 1222}223 224define i32 @extract_v4i32_vector_insert_const_fixed(<4 x i32> %a, <1 x i32> %b, i32 %c, ptr %p) {225 ; CHECK-LABEL: name: extract_v4i32_vector_insert_const_fixed226 ; CHECK: bb.1.entry:227 ; CHECK-NEXT: liveins: $d1, $q0, $w0, $x1228 ; CHECK-NEXT: {{ $}}229 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0230 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1231 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)232 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0233 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1234 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0235 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1236 ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[UV]](s32), [[C]](s64)237 ; CHECK-NEXT: G_STORE [[IVEC]](<4 x s32>), [[COPY3]](p0) :: (store (<4 x s32>) into %ir.p)238 ; CHECK-NEXT: $w0 = COPY [[C1]](s32)239 ; CHECK-NEXT: RET_ReallyLR implicit $w0240entry:241 %vector = call <4 x i32> @llvm.vector.insert.v4i32.v4i32(<4 x i32> %a, <1 x i32> %b, i64 0)242 store <4 x i32> %vector, ptr %p, align 16243 ret i32 1244}245 246define i32 @extract_v4i32_vector_insert_const_fixed_illegal(<1 x i32> %a, <1 x i32> %b, i32 %c, ptr %p) {247 ; CHECK-LABEL: name: extract_v4i32_vector_insert_const_fixed_illegal248 ; CHECK: bb.1.entry:249 ; CHECK-NEXT: liveins: $d0, $d1, $w0, $x1250 ; CHECK-NEXT: {{ $}}251 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0252 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)253 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1254 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)255 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0256 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1257 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1258 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)259 ; CHECK-NEXT: G_STORE [[COPY4]](s32), [[COPY3]](p0) :: (store (s32) into %ir.p, align 16)260 ; CHECK-NEXT: $w0 = COPY [[C]](s32)261 ; CHECK-NEXT: RET_ReallyLR implicit $w0262entry:263 %vector = call <1 x i32> @llvm.vector.insert.v1i32.v4i32(<1 x i32> %a, <1 x i32> %b, i64 0)264 store <1 x i32> %vector, ptr %p, align 16265 ret i32 1266}267 268define i32 @extract_v4ptr_vector_insert_const_fixed_illegal(<1 x ptr> %a, <1 x ptr> %b, i32 %c, ptr %p) {269 ; CHECK-LABEL: name: extract_v4ptr_vector_insert_const_fixed_illegal270 ; CHECK: bb.1.entry:271 ; CHECK-NEXT: liveins: $d0, $d1, $w0, $x1272 ; CHECK-NEXT: {{ $}}273 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $d0274 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $d1275 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w0276 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1277 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1278 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)279 ; CHECK-NEXT: G_STORE [[COPY4]](p0), [[COPY3]](p0) :: (store (p0) into %ir.p, align 16)280 ; CHECK-NEXT: $w0 = COPY [[C]](s32)281 ; CHECK-NEXT: RET_ReallyLR implicit $w0282entry:283 %vector = call <1 x ptr> @llvm.vector.insert.v1ptr.v4ptr(<1 x ptr> %a, <1 x ptr> %b, i64 0)284 store <1 x ptr> %vector, ptr %p, align 16285 ret i32 1286}287 288define i32 @extract_v4ifloat_vector_insert_const_fixed_illegal(<1 x float> %a, <1 x float> %b, float %c, ptr %p) {289 ; CHECK-LABEL: name: extract_v4ifloat_vector_insert_const_fixed_illegal290 ; CHECK: bb.1.entry:291 ; CHECK-NEXT: liveins: $d0, $d1, $s2, $x0292 ; CHECK-NEXT: {{ $}}293 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0294 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)295 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1296 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)297 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2298 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0299 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1300 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)301 ; CHECK-NEXT: G_STORE [[COPY4]](s32), [[COPY3]](p0) :: (store (s32) into %ir.p, align 16)302 ; CHECK-NEXT: $w0 = COPY [[C]](s32)303 ; CHECK-NEXT: RET_ReallyLR implicit $w0304entry:305 %vector = call <1 x float> @llvm.vector.insert.v1f32.v4f32(<1 x float> %a, <1 x float> %b, i64 0)306 store <1 x float> %vector, ptr %p, align 16307 ret i32 1308}309 310define i32 @extract_v4iptr_vector_insert_const_fixed_illegal(<1 x ptr> %a, <1 x ptr> %b, ptr %c, ptr %p) {311 ; CHECK-LABEL: name: extract_v4iptr_vector_insert_const_fixed_illegal312 ; CHECK: bb.1.entry:313 ; CHECK-NEXT: liveins: $d0, $d1, $x0, $x1314 ; CHECK-NEXT: {{ $}}315 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $d0316 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $d1317 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0318 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x1319 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1320 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)321 ; CHECK-NEXT: G_STORE [[COPY4]](p0), [[COPY3]](p0) :: (store (p0) into %ir.p, align 16)322 ; CHECK-NEXT: $w0 = COPY [[C]](s32)323 ; CHECK-NEXT: RET_ReallyLR implicit $w0324entry:325 %vector = call <1 x ptr> @llvm.vector.insert.v1ptr.v4ptr(<1 x ptr> %a, <1 x ptr> %b, i64 0)326 store <1 x ptr> %vector, ptr %p, align 16327 ret i32 1328}329 330define i32 @extract_v4iptr_vector_insert_const_fixed_legal(<4 x ptr> %a, <4 x ptr> %b, ptr %c, ptr %p) {331 ; CHECK-LABEL: name: extract_v4iptr_vector_insert_const_fixed_legal332 ; CHECK: bb.1.entry:333 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $x0, $x1334 ; CHECK-NEXT: {{ $}}335 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0336 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1337 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)338 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2339 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3340 ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[COPY2]](<2 x s64>), [[COPY3]](<2 x s64>)341 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY $x0342 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY $x1343 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1344 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<4 x p0>) = G_INSERT_SUBVECTOR [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]](<4 x p0>), 0345 ; CHECK-NEXT: G_STORE [[INSERT_SUBVECTOR]](<4 x p0>), [[COPY5]](p0) :: (store (<4 x p0>) into %ir.p, align 16)346 ; CHECK-NEXT: $w0 = COPY [[C]](s32)347 ; CHECK-NEXT: RET_ReallyLR implicit $w0348entry:349 %vector = call <4 x ptr> @llvm.vector.insert.v4ptr.v4ptr(<4 x ptr> %a, <4 x ptr> %b, i64 0)350 store <4 x ptr> %vector, ptr %p, align 16351 ret i32 1352}353