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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer %s -o - | FileCheck %s3---4name: test_div5body: |6 bb.0.entry:7 ; CHECK-LABEL: name: test_div8 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x09 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x110 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)11 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 812 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)13 ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 814 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]15 ; CHECK-NEXT: $w0 = COPY [[SDIV]](s32)16 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)17 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25518 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]19 ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)20 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]21 ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]22 ; CHECK-NEXT: $w0 = COPY [[UDIV]](s32)23 %0:_(s64) = COPY $x024 %1:_(s64) = COPY $x125 %2:_(s8) = G_TRUNC %0(s64)26 %3:_(s8) = G_TRUNC %1(s64)27 %4:_(s8) = G_SDIV %2, %328 %6:_(s32) = G_ANYEXT %4(s8)29 $w0 = COPY %6(s32)30 %5:_(s8) = G_UDIV %2, %331 %7:_(s32) = G_ANYEXT %5(s8)32 $w0 = COPY %7(s32)33 34...35---36name: sdiv_v4s3237alignment: 438tracksRegLiveness: true39machineFunctionInfo: {}40body: |41 bb.1:42 liveins: $q0, $q143 44 ; CHECK-LABEL: name: sdiv_v4s3245 ; CHECK: liveins: $q0, $q146 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q048 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q149 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)50 ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)51 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[UV]], [[UV4]]52 ; CHECK-NEXT: [[SDIV1:%[0-9]+]]:_(s32) = G_SDIV [[UV1]], [[UV5]]53 ; CHECK-NEXT: [[SDIV2:%[0-9]+]]:_(s32) = G_SDIV [[UV2]], [[UV6]]54 ; CHECK-NEXT: [[SDIV3:%[0-9]+]]:_(s32) = G_SDIV [[UV3]], [[UV7]]55 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SDIV]](s32), [[SDIV1]](s32), [[SDIV2]](s32), [[SDIV3]](s32)56 ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)57 ; CHECK-NEXT: RET_ReallyLR implicit $q058 %0:_(<4 x s32>) = COPY $q059 %1:_(<4 x s32>) = COPY $q160 %2:_(<4 x s32>) = G_SDIV %0, %161 $q0 = COPY %2(<4 x s32>)62 RET_ReallyLR implicit $q063 64...65