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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -global-isel-abort=1 -O0 -run-pass=legalizer %s -o - | FileCheck %s3--- |4  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5  target triple = "aarch64"6 7  define ptr @test_simple_alloca(i32 %numelts) {8    %addr = alloca i8, i32 %numelts9    ret ptr %addr10  }11 12  define ptr @test_aligned_alloca(i32 %numelts) {13    %addr = alloca i8, i32 %numelts, align 3214    ret ptr %addr15  }16 17  define ptr @test_natural_alloca(i32 %numelts) {18    %addr = alloca i128, i32 %numelts19    ret ptr %addr20  }21 22  define ptr @test_simple_alloca_stack_probing(i32 %numelts) "probe-stack"="inline-asm" {23    %addr = alloca i8, i32 %numelts24    ret ptr %addr25  }26 27  define ptr @test_aligned_alloca_stack_probing(i32 %numelts) "probe-stack"="inline-asm" {28    %addr = alloca i8, i32 %numelts, align 3229    ret ptr %addr30  }31 32  define ptr @test_natural_alloca_stack_probing(i32 %numelts) "probe-stack"="inline-asm" {33    %addr = alloca i128, i32 %numelts34    ret ptr %addr35  }36 37...38---39name:            test_simple_alloca40alignment:       441tracksRegLiveness: true42liveins:43  - { reg: '$w0' }44frameInfo:45  maxAlignment:    146stack:47  - { id: 0, name: addr, type: variable-sized, alignment: 1 }48machineFunctionInfo: {}49body:             |50  bb.1 (%ir-block.0):51    liveins: $w052 53    ; CHECK-LABEL: name: test_simple_alloca54    ; CHECK: liveins: $w055    ; CHECK-NEXT: {{  $}}56    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w057    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 158    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)59    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]60    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1561    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]62    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1663    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]64    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp65    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)66    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]67    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)68    ; CHECK-NEXT: $sp = COPY [[INTTOPTR]](p0)69    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)70    ; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)71    ; CHECK-NEXT: RET_ReallyLR implicit $x072    %0:_(s32) = COPY $w073    %3:_(s64) = G_CONSTANT i64 174    %1:_(s64) = G_ZEXT %0(s32)75    %2:_(s64) = G_MUL %1, %376    %4:_(s64) = G_CONSTANT i64 1577    %5:_(s64) = nuw G_ADD %2, %478    %6:_(s64) = G_CONSTANT i64 -1679    %7:_(s64) = G_AND %5, %680    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 081    $x0 = COPY %8(p0)82    RET_ReallyLR implicit $x083 84...85---86name:            test_aligned_alloca87alignment:       488tracksRegLiveness: true89liveins:90  - { reg: '$w0' }91frameInfo:92  maxAlignment:    3293stack:94  - { id: 0, name: addr, type: variable-sized, alignment: 32 }95machineFunctionInfo: {}96body:             |97  bb.1 (%ir-block.0):98    liveins: $w099 100    ; CHECK-LABEL: name: test_aligned_alloca101    ; CHECK: liveins: $w0102    ; CHECK-NEXT: {{  $}}103    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0104    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1105    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)106    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]107    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15108    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]109    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16110    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]111    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp112    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)113    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]114    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -32115    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]]116    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND1]](s64)117    ; CHECK-NEXT: $sp = COPY [[INTTOPTR]](p0)118    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)119    ; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)120    ; CHECK-NEXT: RET_ReallyLR implicit $x0121    %0:_(s32) = COPY $w0122    %3:_(s64) = G_CONSTANT i64 1123    %1:_(s64) = G_ZEXT %0(s32)124    %2:_(s64) = G_MUL %1, %3125    %4:_(s64) = G_CONSTANT i64 15126    %5:_(s64) = nuw G_ADD %2, %4127    %6:_(s64) = G_CONSTANT i64 -16128    %7:_(s64) = G_AND %5, %6129    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 32130    $x0 = COPY %8(p0)131    RET_ReallyLR implicit $x0132 133...134---135name:            test_natural_alloca136alignment:       4137tracksRegLiveness: true138liveins:139  - { reg: '$w0' }140frameInfo:141  maxAlignment:    1142stack:143  - { id: 0, name: addr, type: variable-sized, alignment: 1 }144machineFunctionInfo: {}145body:             |146  bb.1 (%ir-block.0):147    liveins: $w0148 149    ; CHECK-LABEL: name: test_natural_alloca150    ; CHECK: liveins: $w0151    ; CHECK-NEXT: {{  $}}152    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0153    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16154    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)155    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]156    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15157    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]158    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16159    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]160    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp161    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)162    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]163    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)164    ; CHECK-NEXT: $sp = COPY [[INTTOPTR]](p0)165    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)166    ; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)167    ; CHECK-NEXT: RET_ReallyLR implicit $x0168    %0:_(s32) = COPY $w0169    %3:_(s64) = G_CONSTANT i64 16170    %1:_(s64) = G_ZEXT %0(s32)171    %2:_(s64) = G_MUL %1, %3172    %4:_(s64) = G_CONSTANT i64 15173    %5:_(s64) = nuw G_ADD %2, %4174    %6:_(s64) = G_CONSTANT i64 -16175    %7:_(s64) = G_AND %5, %6176    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 0177    $x0 = COPY %8(p0)178    RET_ReallyLR implicit $x0179 180...181---182name:            test_simple_alloca_stack_probing183alignment:       4184tracksRegLiveness: true185liveins:186  - { reg: '$w0' }187frameInfo:188  maxAlignment:    1189stack:190  - { id: 0, name: addr, type: variable-sized, alignment: 1 }191machineFunctionInfo: {}192body:             |193  bb.1 (%ir-block.0):194    liveins: $w0195 196    ; CHECK-LABEL: name: test_simple_alloca_stack_probing197    ; CHECK: liveins: $w0198    ; CHECK-NEXT: {{  $}}199    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0200    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)201    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0202    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s64)203    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15204    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[SHL]], [[C1]]205    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16206    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]207    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp208    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)209    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]210    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr64common(p0) = G_INTTOPTR [[SUB]](s64)211    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)212    ; CHECK-NEXT: PROBED_STACKALLOC_DYN [[INTTOPTR]](p0), implicit-def $sp, implicit-def $nzcv, implicit $sp213    ; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)214    ; CHECK-NEXT: RET_ReallyLR implicit $x0215    %0:_(s32) = COPY $w0216    %1:_(s64) = G_ZEXT %0(s32)217    %9:_(s64) = G_CONSTANT i64 0218    %2:_(s64) = G_SHL %1, %9(s64)219    %4:_(s64) = G_CONSTANT i64 15220    %5:_(s64) = nuw G_ADD %2, %4221    %6:_(s64) = G_CONSTANT i64 -16222    %7:_(s64) = G_AND %5, %6223    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 1224    $x0 = COPY %8(p0)225    RET_ReallyLR implicit $x0226 227...228---229name:            test_aligned_alloca_stack_probing230alignment:       4231tracksRegLiveness: true232liveins:233  - { reg: '$w0' }234frameInfo:235  maxAlignment:    32236stack:237  - { id: 0, name: addr, type: variable-sized, alignment: 32 }238machineFunctionInfo: {}239body:             |240  bb.1 (%ir-block.0):241    liveins: $w0242 243    ; CHECK-LABEL: name: test_aligned_alloca_stack_probing244    ; CHECK: liveins: $w0245    ; CHECK-NEXT: {{  $}}246    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0247    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)248    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0249    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s64)250    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15251    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[SHL]], [[C1]]252    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16253    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]254    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp255    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)256    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]257    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -32258    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]]259    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr64common(p0) = G_INTTOPTR [[AND1]](s64)260    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)261    ; CHECK-NEXT: PROBED_STACKALLOC_DYN [[INTTOPTR]](p0), implicit-def $sp, implicit-def $nzcv, implicit $sp262    ; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)263    ; CHECK-NEXT: RET_ReallyLR implicit $x0264    %0:_(s32) = COPY $w0265    %1:_(s64) = G_ZEXT %0(s32)266    %9:_(s64) = G_CONSTANT i64 0267    %2:_(s64) = G_SHL %1, %9(s64)268    %4:_(s64) = G_CONSTANT i64 15269    %5:_(s64) = nuw G_ADD %2, %4270    %6:_(s64) = G_CONSTANT i64 -16271    %7:_(s64) = G_AND %5, %6272    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 32273    $x0 = COPY %8(p0)274    RET_ReallyLR implicit $x0275 276...277---278name:            test_natural_alloca_stack_probing279alignment:       4280tracksRegLiveness: true281liveins:282  - { reg: '$w0' }283frameInfo:284  maxAlignment:    1285stack:286  - { id: 0, name: addr, type: variable-sized, alignment: 1 }287machineFunctionInfo: {}288body:             |289  bb.1 (%ir-block.0):290    liveins: $w0291 292    ; CHECK-LABEL: name: test_natural_alloca_stack_probing293    ; CHECK: liveins: $w0294    ; CHECK-NEXT: {{  $}}295    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0296    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)297    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4298    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s64)299    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15300    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[SHL]], [[C1]]301    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16302    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]303    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp304    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)305    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]306    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr64common(p0) = G_INTTOPTR [[SUB]](s64)307    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)308    ; CHECK-NEXT: PROBED_STACKALLOC_DYN [[INTTOPTR]](p0), implicit-def $sp, implicit-def $nzcv, implicit $sp309    ; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)310    ; CHECK-NEXT: RET_ReallyLR implicit $x0311    %0:_(s32) = COPY $w0312    %1:_(s64) = G_ZEXT %0(s32)313    %9:_(s64) = G_CONSTANT i64 4314    %2:_(s64) = G_SHL %1, %9(s64)315    %4:_(s64) = G_CONSTANT i64 15316    %5:_(s64) = nuw G_ADD %2, %4317    %6:_(s64) = G_CONSTANT i64 -16318    %7:_(s64) = G_AND %5, %6319    %8:_(p0) = G_DYN_STACKALLOC %7(s64), 1320    $x0 = COPY %8(p0)321    RET_ReallyLR implicit $x0322 323...324