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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=-fullfp16 -o - | FileCheck %s --check-prefix=NO-FP163# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=+fullfp16 -o - | FileCheck %s --check-prefix=FP164...5---6name: test_v4f16.fma7alignment: 48tracksRegLiveness: true9machineFunctionInfo: {}10body: |11 bb.0:12 liveins: $d0, $d1, $d213 14 ; NO-FP16-LABEL: name: test_v4f16.fma15 ; NO-FP16: liveins: $d0, $d1, $d216 ; NO-FP16-NEXT: {{ $}}17 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d018 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d119 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d220 ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)21 ; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY1]](<4 x s16>)22 ; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY2]](<4 x s16>)23 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT]], [[FPEXT1]], [[FPEXT2]]24 ; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA]](<4 x s32>)25 ; NO-FP16-NEXT: $d0 = COPY [[FPTRUNC]](<4 x s16>)26 ; NO-FP16-NEXT: RET_ReallyLR implicit $d027 ;28 ; FP16-LABEL: name: test_v4f16.fma29 ; FP16: liveins: $d0, $d1, $d230 ; FP16-NEXT: {{ $}}31 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d032 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d133 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d234 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]35 ; FP16-NEXT: $d0 = COPY [[FMA]](<4 x s16>)36 ; FP16-NEXT: RET_ReallyLR implicit $d037 %0:_(<4 x s16>) = COPY $d038 %1:_(<4 x s16>) = COPY $d139 %2:_(<4 x s16>) = COPY $d240 %3:_(<4 x s16>) = G_FMA %0, %1, %241 $d0 = COPY %3(<4 x s16>)42 RET_ReallyLR implicit $d043 44...45---46name: test_v8f16.fma47alignment: 448tracksRegLiveness: true49machineFunctionInfo: {}50body: |51 bb.0:52 liveins: $q0, $q1, $q253 54 ; NO-FP16-LABEL: name: test_v8f16.fma55 ; NO-FP16: liveins: $q0, $q1, $q256 ; NO-FP16-NEXT: {{ $}}57 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q058 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q159 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q260 ; NO-FP16-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)61 ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)62 ; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)63 ; NO-FP16-NEXT: [[UV2:%[0-9]+]]:_(<4 x s16>), [[UV3:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY1]](<8 x s16>)64 ; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV2]](<4 x s16>)65 ; NO-FP16-NEXT: [[FPEXT3:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV3]](<4 x s16>)66 ; NO-FP16-NEXT: [[UV4:%[0-9]+]]:_(<4 x s16>), [[UV5:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY2]](<8 x s16>)67 ; NO-FP16-NEXT: [[FPEXT4:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV4]](<4 x s16>)68 ; NO-FP16-NEXT: [[FPEXT5:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV5]](<4 x s16>)69 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT]], [[FPEXT2]], [[FPEXT4]]70 ; NO-FP16-NEXT: [[FMA1:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT1]], [[FPEXT3]], [[FPEXT5]]71 ; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA]](<4 x s32>)72 ; NO-FP16-NEXT: [[FPTRUNC1:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA1]](<4 x s32>)73 ; NO-FP16-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[FPTRUNC]](<4 x s16>), [[FPTRUNC1]](<4 x s16>)74 ; NO-FP16-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x s16>)75 ; NO-FP16-NEXT: RET_ReallyLR implicit $q076 ;77 ; FP16-LABEL: name: test_v8f16.fma78 ; FP16: liveins: $q0, $q1, $q279 ; FP16-NEXT: {{ $}}80 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q081 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q182 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q283 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<8 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]84 ; FP16-NEXT: $q0 = COPY [[FMA]](<8 x s16>)85 ; FP16-NEXT: RET_ReallyLR implicit $q086 %0:_(<8 x s16>) = COPY $q087 %1:_(<8 x s16>) = COPY $q188 %2:_(<8 x s16>) = COPY $q289 %3:_(<8 x s16>) = G_FMA %0, %1, %290 $q0 = COPY %3(<8 x s16>)91 RET_ReallyLR implicit $q092 93...94---95name: test_v2f32.fma96alignment: 497tracksRegLiveness: true98machineFunctionInfo: {}99body: |100 bb.0:101 liveins: $d0, $d1, $d2102 103 ; NO-FP16-LABEL: name: test_v2f32.fma104 ; NO-FP16: liveins: $d0, $d1, $d2105 ; NO-FP16-NEXT: {{ $}}106 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0107 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1108 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2109 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]110 ; NO-FP16-NEXT: $d0 = COPY [[FMA]](<2 x s32>)111 ; NO-FP16-NEXT: RET_ReallyLR implicit $d0112 ;113 ; FP16-LABEL: name: test_v2f32.fma114 ; FP16: liveins: $d0, $d1, $d2115 ; FP16-NEXT: {{ $}}116 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0117 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1118 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2119 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]120 ; FP16-NEXT: $d0 = COPY [[FMA]](<2 x s32>)121 ; FP16-NEXT: RET_ReallyLR implicit $d0122 %0:_(<2 x s32>) = COPY $d0123 %1:_(<2 x s32>) = COPY $d1124 %2:_(<2 x s32>) = COPY $d2125 %3:_(<2 x s32>) = G_FMA %0, %1, %2126 $d0 = COPY %3(<2 x s32>)127 RET_ReallyLR implicit $d0128 129...130---131name: test_v4f32.fma132alignment: 4133tracksRegLiveness: true134machineFunctionInfo: {}135body: |136 bb.0:137 liveins: $q0, $q1, $q2138 139 ; NO-FP16-LABEL: name: test_v4f32.fma140 ; NO-FP16: liveins: $q0, $q1, $q2141 ; NO-FP16-NEXT: {{ $}}142 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0143 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1144 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2145 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]146 ; NO-FP16-NEXT: $q0 = COPY [[FMA]](<4 x s32>)147 ; NO-FP16-NEXT: RET_ReallyLR implicit $q0148 ;149 ; FP16-LABEL: name: test_v4f32.fma150 ; FP16: liveins: $q0, $q1, $q2151 ; FP16-NEXT: {{ $}}152 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0153 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1154 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2155 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]156 ; FP16-NEXT: $q0 = COPY [[FMA]](<4 x s32>)157 ; FP16-NEXT: RET_ReallyLR implicit $q0158 %0:_(<4 x s32>) = COPY $q0159 %1:_(<4 x s32>) = COPY $q1160 %2:_(<4 x s32>) = COPY $q2161 %3:_(<4 x s32>) = G_FMA %0, %1, %2162 $q0 = COPY %3(<4 x s32>)163 RET_ReallyLR implicit $q0164 165...166---167name: test_v2f64.fma168alignment: 4169tracksRegLiveness: true170machineFunctionInfo: {}171body: |172 bb.0:173 liveins: $q0, $q1, $q2174 175 ; NO-FP16-LABEL: name: test_v2f64.fma176 ; NO-FP16: liveins: $q0, $q1, $q2177 ; NO-FP16-NEXT: {{ $}}178 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0179 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1180 ; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2181 ; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]182 ; NO-FP16-NEXT: $q0 = COPY [[FMA]](<2 x s64>)183 ; NO-FP16-NEXT: RET_ReallyLR implicit $q0184 ;185 ; FP16-LABEL: name: test_v2f64.fma186 ; FP16: liveins: $q0, $q1, $q2187 ; FP16-NEXT: {{ $}}188 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0189 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1190 ; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2191 ; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]192 ; FP16-NEXT: $q0 = COPY [[FMA]](<2 x s64>)193 ; FP16-NEXT: RET_ReallyLR implicit $q0194 %0:_(<2 x s64>) = COPY $q0195 %1:_(<2 x s64>) = COPY $q1196 %2:_(<2 x s64>) = COPY $q2197 %3:_(<2 x s64>) = G_FMA %0, %1, %2198 $q0 = COPY %3(<2 x s64>)199 RET_ReallyLR implicit $q0200