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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2 3# RUN:llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=-fullfp16 -o - | FileCheck %s --check-prefix=NO-FP164# RUN:llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -o - | FileCheck %s --check-prefix=FP165 6...7---8name: test_f16.roundeven9alignment: 410tracksRegLiveness: true11machineFunctionInfo: {}12body: |13 bb.0:14 liveins: $h015 16 ; NO-FP16-LABEL: name: test_f16.roundeven17 ; NO-FP16: liveins: $h018 ; NO-FP16-NEXT: {{ $}}19 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h020 ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16)21 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FPEXT]]22 ; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUNDEVEN]](s32)23 ; NO-FP16-NEXT: $h0 = COPY [[FPTRUNC]](s16)24 ; NO-FP16-NEXT: RET_ReallyLR implicit $h025 ;26 ; FP16-LABEL: name: test_f16.roundeven27 ; FP16: liveins: $h028 ; FP16-NEXT: {{ $}}29 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h030 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s16) = G_INTRINSIC_ROUNDEVEN [[COPY]]31 ; FP16-NEXT: $h0 = COPY [[INTRINSIC_ROUNDEVEN]](s16)32 ; FP16-NEXT: RET_ReallyLR implicit $h033 %0:_(s16) = COPY $h034 %1:_(s16) = G_INTRINSIC_ROUNDEVEN %035 $h0 = COPY %1(s16)36 RET_ReallyLR implicit $h037 38...39---40name: test_f32.roundeven41alignment: 442tracksRegLiveness: true43machineFunctionInfo: {}44body: |45 bb.0:46 liveins: $s047 48 ; NO-FP16-LABEL: name: test_f32.roundeven49 ; NO-FP16: liveins: $s050 ; NO-FP16-NEXT: {{ $}}51 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s052 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[COPY]]53 ; NO-FP16-NEXT: $s0 = COPY [[INTRINSIC_ROUNDEVEN]](s32)54 ; NO-FP16-NEXT: RET_ReallyLR implicit $s055 ;56 ; FP16-LABEL: name: test_f32.roundeven57 ; FP16: liveins: $s058 ; FP16-NEXT: {{ $}}59 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s060 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[COPY]]61 ; FP16-NEXT: $s0 = COPY [[INTRINSIC_ROUNDEVEN]](s32)62 ; FP16-NEXT: RET_ReallyLR implicit $s063 %0:_(s32) = COPY $s064 %1:_(s32) = G_INTRINSIC_ROUNDEVEN %065 $s0 = COPY %1(s32)66 RET_ReallyLR implicit $s067 68...69---70name: test_f64.roundeven71alignment: 472tracksRegLiveness: true73machineFunctionInfo: {}74body: |75 bb.0:76 liveins: $d077 78 ; NO-FP16-LABEL: name: test_f64.roundeven79 ; NO-FP16: liveins: $d080 ; NO-FP16-NEXT: {{ $}}81 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d082 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUNDEVEN [[COPY]]83 ; NO-FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](s64)84 ; NO-FP16-NEXT: RET_ReallyLR implicit $d085 ;86 ; FP16-LABEL: name: test_f64.roundeven87 ; FP16: liveins: $d088 ; FP16-NEXT: {{ $}}89 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d090 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUNDEVEN [[COPY]]91 ; FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](s64)92 ; FP16-NEXT: RET_ReallyLR implicit $d093 %0:_(s64) = COPY $d094 %1:_(s64) = G_INTRINSIC_ROUNDEVEN %095 $d0 = COPY %1(s64)96 RET_ReallyLR implicit $d097 98...99---100name: test_v8f16.roundeven101alignment: 4102tracksRegLiveness: true103machineFunctionInfo: {}104body: |105 bb.0:106 liveins: $q0107 108 ; NO-FP16-LABEL: name: test_v8f16.roundeven109 ; NO-FP16: liveins: $q0110 ; NO-FP16-NEXT: {{ $}}111 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0112 ; NO-FP16-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)113 ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)114 ; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)115 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_ROUNDEVEN [[FPEXT]]116 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_ROUNDEVEN [[FPEXT1]]117 ; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[INTRINSIC_ROUNDEVEN]](<4 x s32>)118 ; NO-FP16-NEXT: [[FPTRUNC1:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[INTRINSIC_ROUNDEVEN1]](<4 x s32>)119 ; NO-FP16-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[FPTRUNC]](<4 x s16>), [[FPTRUNC1]](<4 x s16>)120 ; NO-FP16-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x s16>)121 ; NO-FP16-NEXT: RET_ReallyLR implicit $q0122 ;123 ; FP16-LABEL: name: test_v8f16.roundeven124 ; FP16: liveins: $q0125 ; FP16-NEXT: {{ $}}126 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0127 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC_ROUNDEVEN [[COPY]]128 ; FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<8 x s16>)129 ; FP16-NEXT: RET_ReallyLR implicit $q0130 %0:_(<8 x s16>) = COPY $q0131 %1:_(<8 x s16>) = G_INTRINSIC_ROUNDEVEN %0132 $q0 = COPY %1(<8 x s16>)133 RET_ReallyLR implicit $q0134 135...136---137name: test_v4f16.roundeven138alignment: 4139tracksRegLiveness: true140registers:141 - { id: 0, class: _ }142 - { id: 1, class: _ }143machineFunctionInfo: {}144body: |145 bb.0:146 liveins: $d0147 148 ; NO-FP16-LABEL: name: test_v4f16.roundeven149 ; NO-FP16: liveins: $d0150 ; NO-FP16-NEXT: {{ $}}151 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0152 ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)153 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_ROUNDEVEN [[FPEXT]]154 ; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[INTRINSIC_ROUNDEVEN]](<4 x s32>)155 ; NO-FP16-NEXT: $d0 = COPY [[FPTRUNC]](<4 x s16>)156 ; NO-FP16-NEXT: RET_ReallyLR implicit $d0157 ;158 ; FP16-LABEL: name: test_v4f16.roundeven159 ; FP16: liveins: $d0160 ; FP16-NEXT: {{ $}}161 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0162 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x s16>) = G_INTRINSIC_ROUNDEVEN [[COPY]]163 ; FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](<4 x s16>)164 ; FP16-NEXT: RET_ReallyLR implicit $d0165 %0:_(<4 x s16>) = COPY $d0166 %1:_(<4 x s16>) = G_INTRINSIC_ROUNDEVEN %0167 $d0 = COPY %1(<4 x s16>)168 RET_ReallyLR implicit $d0169 170...171---172name: test_v2f32.roundeven173alignment: 4174tracksRegLiveness: true175registers:176 - { id: 0, class: _ }177 - { id: 1, class: _ }178machineFunctionInfo: {}179body: |180 bb.0:181 liveins: $d0182 183 ; NO-FP16-LABEL: name: test_v2f32.roundeven184 ; NO-FP16: liveins: $d0185 ; NO-FP16-NEXT: {{ $}}186 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0187 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_ROUNDEVEN [[COPY]]188 ; NO-FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x s32>)189 ; NO-FP16-NEXT: RET_ReallyLR implicit $d0190 ;191 ; FP16-LABEL: name: test_v2f32.roundeven192 ; FP16: liveins: $d0193 ; FP16-NEXT: {{ $}}194 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0195 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_ROUNDEVEN [[COPY]]196 ; FP16-NEXT: $d0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x s32>)197 ; FP16-NEXT: RET_ReallyLR implicit $d0198 %0:_(<2 x s32>) = COPY $d0199 %1:_(<2 x s32>) = G_INTRINSIC_ROUNDEVEN %0200 $d0 = COPY %1(<2 x s32>)201 RET_ReallyLR implicit $d0202 203...204---205name: test_v4f32.roundeven206alignment: 4207tracksRegLiveness: true208registers:209 - { id: 0, class: _ }210 - { id: 1, class: _ }211machineFunctionInfo: {}212body: |213 bb.0:214 liveins: $q0215 216 ; NO-FP16-LABEL: name: test_v4f32.roundeven217 ; NO-FP16: liveins: $q0218 ; NO-FP16-NEXT: {{ $}}219 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0220 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_ROUNDEVEN [[COPY]]221 ; NO-FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<4 x s32>)222 ; NO-FP16-NEXT: RET_ReallyLR implicit $q0223 ;224 ; FP16-LABEL: name: test_v4f32.roundeven225 ; FP16: liveins: $q0226 ; FP16-NEXT: {{ $}}227 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0228 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_ROUNDEVEN [[COPY]]229 ; FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<4 x s32>)230 ; FP16-NEXT: RET_ReallyLR implicit $q0231 %0:_(<4 x s32>) = COPY $q0232 %1:_(<4 x s32>) = G_INTRINSIC_ROUNDEVEN %0233 $q0 = COPY %1(<4 x s32>)234 RET_ReallyLR implicit $q0235 236...237---238name: test_v2f64.roundeven239alignment: 4240tracksRegLiveness: true241registers:242 - { id: 0, class: _ }243 - { id: 1, class: _ }244machineFunctionInfo: {}245body: |246 bb.0:247 liveins: $q0248 249 ; NO-FP16-LABEL: name: test_v2f64.roundeven250 ; NO-FP16: liveins: $q0251 ; NO-FP16-NEXT: {{ $}}252 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0253 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUNDEVEN [[COPY]]254 ; NO-FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x s64>)255 ; NO-FP16-NEXT: RET_ReallyLR implicit $q0256 ;257 ; FP16-LABEL: name: test_v2f64.roundeven258 ; FP16: liveins: $q0259 ; FP16-NEXT: {{ $}}260 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0261 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUNDEVEN [[COPY]]262 ; FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x s64>)263 ; FP16-NEXT: RET_ReallyLR implicit $q0264 %0:_(<2 x s64>) = COPY $q0265 %1:_(<2 x s64>) = G_INTRINSIC_ROUNDEVEN %0266 $q0 = COPY %1(<2 x s64>)267 RET_ReallyLR implicit $q0268 269...270---271name: test_v4f64.roundeven272alignment: 4273tracksRegLiveness: true274body: |275 bb.0:276 liveins: $q0, $q1277 278 ; NO-FP16-LABEL: name: test_v4f64.roundeven279 ; NO-FP16: liveins: $q0, $q1280 ; NO-FP16-NEXT: {{ $}}281 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0282 ; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1283 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUNDEVEN [[COPY]]284 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUNDEVEN [[COPY1]]285 ; NO-FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x s64>)286 ; NO-FP16-NEXT: $q1 = COPY [[INTRINSIC_ROUNDEVEN1]](<2 x s64>)287 ; NO-FP16-NEXT: RET_ReallyLR implicit $q0288 ;289 ; FP16-LABEL: name: test_v4f64.roundeven290 ; FP16: liveins: $q0, $q1291 ; FP16-NEXT: {{ $}}292 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0293 ; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1294 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUNDEVEN [[COPY]]295 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN1:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUNDEVEN [[COPY1]]296 ; FP16-NEXT: $q0 = COPY [[INTRINSIC_ROUNDEVEN]](<2 x s64>)297 ; FP16-NEXT: $q1 = COPY [[INTRINSIC_ROUNDEVEN1]](<2 x s64>)298 ; FP16-NEXT: RET_ReallyLR implicit $q0299 %0:_(<2 x s64>) = COPY $q0300 %1:_(<2 x s64>) = COPY $q1301 %2:_(<4 x s64>) = G_CONCAT_VECTORS %0, %1302 %3:_(<4 x s64>) = G_INTRINSIC_ROUNDEVEN %2303 %4:_(<2 x s64>), %5:_(<2 x s64>) = G_UNMERGE_VALUES %3304 $q0 = COPY %4(<2 x s64>)305 $q1 = COPY %5(<2 x s64>)306 RET_ReallyLR implicit $q0307 308...309---310name: test_v2f16.roundeven311alignment: 4312tracksRegLiveness: true313body: |314 bb.0:315 liveins: $s0, $s1316 317 ; NO-FP16-LABEL: name: test_v2f16.roundeven318 ; NO-FP16: liveins: $s0, $s1319 ; NO-FP16-NEXT: {{ $}}320 ; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0321 ; NO-FP16-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)322 ; NO-FP16-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF323 ; NO-FP16-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[DEF]](s16), [[DEF]](s16)324 ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[BUILD_VECTOR]](<4 x s16>)325 ; NO-FP16-NEXT: [[UV2:%[0-9]+]]:_(<2 x s32>), [[UV3:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FPEXT]](<4 x s32>)326 ; NO-FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_ROUNDEVEN [[UV2]]327 ; NO-FP16-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INTRINSIC_ROUNDEVEN]](<2 x s32>)328 ; NO-FP16-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF329 ; NO-FP16-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV4]](s32), [[UV5]](s32), [[DEF1]](s32), [[DEF1]](s32)330 ; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[BUILD_VECTOR1]](<4 x s32>)331 ; NO-FP16-NEXT: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[FPTRUNC]](<4 x s16>)332 ; NO-FP16-NEXT: $s0 = COPY [[UV6]](<2 x s16>)333 ; NO-FP16-NEXT: RET_ReallyLR implicit $s0334 ;335 ; FP16-LABEL: name: test_v2f16.roundeven336 ; FP16: liveins: $s0, $s1337 ; FP16-NEXT: {{ $}}338 ; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0339 ; FP16-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)340 ; FP16-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF341 ; FP16-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[DEF]](s16), [[DEF]](s16)342 ; FP16-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(<4 x s16>) = G_INTRINSIC_ROUNDEVEN [[BUILD_VECTOR]]343 ; FP16-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INTRINSIC_ROUNDEVEN]](<4 x s16>)344 ; FP16-NEXT: $s0 = COPY [[UV2]](<2 x s16>)345 ; FP16-NEXT: RET_ReallyLR implicit $s0346 %0:_(<2 x s16>) = COPY $s0347 %1:_(<2 x s16>) = G_INTRINSIC_ROUNDEVEN %0348 $s0 = COPY %1(<2 x s16>)349 RET_ReallyLR implicit $s0350