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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=aarch64 -run-pass=legalizer -global-isel -o - %s | FileCheck %s3 4--- |5 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"6 target triple = "aarch64"7 8 define <3 x i16> @range_v3i16(ptr %a_ptr, ptr %b_ptr) {9 %a = load <3 x i16>, ptr %a_ptr, align 8, !range !0, !noundef !110 %b = load <3 x i16>, ptr %b_ptr, align 8, !range !2, !noundef !111 %result = add <3 x i16> %a, %b12 ret <3 x i16> %result13 }14 15 !0 = !{i16 16, i16 17}16 !1 = !{}17 !2 = !{i16 32, i16 33}18...19---20name: range_v3i1621body: |22 bb.1 (%ir-block.0):23 liveins: $x0, $x124 ; Make sure we drop the range metadata when widening an aligned load.25 26 ; CHECK-LABEL: name: range_v3i1627 ; CHECK: liveins: $x0, $x128 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x030 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x131 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<4 x s16>) from %ir.a_ptr)32 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s16>) from %ir.b_ptr)33 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[LOAD]], [[LOAD1]]34 ; CHECK-NEXT: $d0 = COPY [[ADD]](<4 x s16>)35 ; CHECK-NEXT: RET_ReallyLR implicit $d036 %0:_(p0) = COPY $x037 %1:_(p0) = COPY $x138 %2:_(<3 x s16>) = G_LOAD %0(p0) :: (load (<3 x s16>) from %ir.a_ptr, align 8, !range !0)39 %3:_(<3 x s16>) = G_LOAD %1(p0) :: (load (<3 x s16>) from %ir.b_ptr, align 8, !range !2)40 %4:_(<3 x s16>) = G_ADD %2, %341 %5:_(s16), %6:_(s16), %7:_(s16) = G_UNMERGE_VALUES %4(<3 x s16>)42 %8:_(s16) = G_IMPLICIT_DEF43 %9:_(<4 x s16>) = G_BUILD_VECTOR %5(s16), %6(s16), %7(s16), %8(s16)44 $d0 = COPY %9(<4 x s16>)45 RET_ReallyLR implicit $d046...47