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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: v8s8_smin6tracksRegLiveness: true7body: |8 bb.0:9 liveins: $x010 11 ; CHECK-LABEL: name: v8s8_smin12 ; CHECK: liveins: $x013 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF15 ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF16 ; CHECK-NEXT: %smin:_(<8 x s8>) = G_SMIN %vec, %vec117 ; CHECK-NEXT: $x0 = COPY %smin(<8 x s8>)18 ; CHECK-NEXT: RET_ReallyLR implicit $x019 %vec:_(<8 x s8>) = G_IMPLICIT_DEF20 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF21 %smin:_(<8 x s8>) = G_SMIN %vec, %vec122 $x0 = COPY %smin23 RET_ReallyLR implicit $x024 25...26---27name: v16s8_smin28tracksRegLiveness: true29body: |30 bb.0:31 liveins: $q032 33 ; CHECK-LABEL: name: v16s8_smin34 ; CHECK: liveins: $q035 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF37 ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF38 ; CHECK-NEXT: %smin:_(<16 x s8>) = G_SMIN %vec, %vec139 ; CHECK-NEXT: $q0 = COPY %smin(<16 x s8>)40 ; CHECK-NEXT: RET_ReallyLR implicit $q041 %vec:_(<16 x s8>) = G_IMPLICIT_DEF42 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF43 %smin:_(<16 x s8>) = G_SMIN %vec, %vec144 $q0 = COPY %smin45 RET_ReallyLR implicit $q046 47...48---49name: v32s8_smin50tracksRegLiveness: true51body: |52 bb.0:53 liveins: $x0, $q0, $q154 55 ; CHECK-LABEL: name: v32s8_smin56 ; CHECK: liveins: $x0, $q0, $q157 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF59 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(<16 x s8>) = G_SMIN [[DEF]], [[DEF]]60 ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<16 x s8>) = G_SMIN [[DEF]], [[DEF]]61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x062 ; CHECK-NEXT: G_STORE [[SMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)63 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1664 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)65 ; CHECK-NEXT: G_STORE [[SMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)66 %vec:_(<32 x s8>) = G_IMPLICIT_DEF67 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF68 %smin:_(<32 x s8>) = G_SMIN %vec, %vec169 %1:_(p0) = COPY $x070 G_STORE %smin(<32 x s8>), %1(p0) :: (store (<32 x s8>))71 72...73---74name: v4s16_smin75tracksRegLiveness: true76body: |77 bb.0:78 liveins: $x079 80 ; CHECK-LABEL: name: v4s16_smin81 ; CHECK: liveins: $x082 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF84 ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF85 ; CHECK-NEXT: %smin:_(<4 x s16>) = G_SMIN %vec, %vec186 ; CHECK-NEXT: $x0 = COPY %smin(<4 x s16>)87 ; CHECK-NEXT: RET_ReallyLR implicit $x088 %vec:_(<4 x s16>) = G_IMPLICIT_DEF89 %vec1:_(<4 x s16>) = G_IMPLICIT_DEF90 %smin:_(<4 x s16>) = G_SMIN %vec, %vec191 $x0 = COPY %smin92 RET_ReallyLR implicit $x093 94...95---96name: v8s16_smin97tracksRegLiveness: true98body: |99 bb.0:100 liveins: $q0101 102 ; CHECK-LABEL: name: v8s16_smin103 ; CHECK: liveins: $q0104 ; CHECK-NEXT: {{ $}}105 ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF106 ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF107 ; CHECK-NEXT: %smin:_(<8 x s16>) = G_SMIN %vec, %vec1108 ; CHECK-NEXT: $q0 = COPY %smin(<8 x s16>)109 ; CHECK-NEXT: RET_ReallyLR implicit $q0110 %vec:_(<8 x s16>) = G_IMPLICIT_DEF111 %vec1:_(<8 x s16>) = G_IMPLICIT_DEF112 %smin:_(<8 x s16>) = G_SMIN %vec, %vec1113 $q0 = COPY %smin114 RET_ReallyLR implicit $q0115 116...117---118name: v16s16_smin119tracksRegLiveness: true120body: |121 bb.0:122 liveins: $x0, $q0, $q1123 124 ; CHECK-LABEL: name: v16s16_smin125 ; CHECK: liveins: $x0, $q0, $q1126 ; CHECK-NEXT: {{ $}}127 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF128 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(<8 x s16>) = G_SMIN [[DEF]], [[DEF]]129 ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<8 x s16>) = G_SMIN [[DEF]], [[DEF]]130 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0131 ; CHECK-NEXT: G_STORE [[SMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)132 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16133 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)134 ; CHECK-NEXT: G_STORE [[SMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)135 %vec:_(<16 x s16>) = G_IMPLICIT_DEF136 %vec1:_(<16 x s16>) = G_IMPLICIT_DEF137 %smin:_(<16 x s16>) = G_SMIN %vec, %vec1138 %1:_(p0) = COPY $x0139 G_STORE %smin(<16 x s16>), %1(p0) :: (store (<16 x s16>))140 141...142---143name: v2s32_smin144tracksRegLiveness: true145body: |146 bb.0:147 liveins: $x0148 149 ; CHECK-LABEL: name: v2s32_smin150 ; CHECK: liveins: $x0151 ; CHECK-NEXT: {{ $}}152 ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF153 ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF154 ; CHECK-NEXT: %smin:_(<2 x s32>) = G_SMIN %vec, %vec1155 ; CHECK-NEXT: $x0 = COPY %smin(<2 x s32>)156 ; CHECK-NEXT: RET_ReallyLR implicit $x0157 %vec:_(<2 x s32>) = G_IMPLICIT_DEF158 %vec1:_(<2 x s32>) = G_IMPLICIT_DEF159 %smin:_(<2 x s32>) = G_SMIN %vec, %vec1160 $x0 = COPY %smin161 RET_ReallyLR implicit $x0162 163...164---165name: v4s32_smin166tracksRegLiveness: true167body: |168 bb.0:169 liveins: $q0170 171 ; CHECK-LABEL: name: v4s32_smin172 ; CHECK: liveins: $q0173 ; CHECK-NEXT: {{ $}}174 ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF175 ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF176 ; CHECK-NEXT: %smin:_(<4 x s32>) = G_SMIN %vec, %vec1177 ; CHECK-NEXT: $q0 = COPY %smin(<4 x s32>)178 ; CHECK-NEXT: RET_ReallyLR implicit $q0179 %vec:_(<4 x s32>) = G_IMPLICIT_DEF180 %vec1:_(<4 x s32>) = G_IMPLICIT_DEF181 %smin:_(<4 x s32>) = G_SMIN %vec, %vec1182 $q0 = COPY %smin183 RET_ReallyLR implicit $q0184 185...186---187name: v8s32_smin188tracksRegLiveness: true189body: |190 bb.0:191 liveins: $x0, $q0, $q1192 193 ; CHECK-LABEL: name: v8s32_smin194 ; CHECK: liveins: $x0, $q0, $q1195 ; CHECK-NEXT: {{ $}}196 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF197 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(<4 x s32>) = G_SMIN [[DEF]], [[DEF]]198 ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<4 x s32>) = G_SMIN [[DEF]], [[DEF]]199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0200 ; CHECK-NEXT: G_STORE [[SMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)201 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16202 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)203 ; CHECK-NEXT: G_STORE [[SMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)204 %vec:_(<8 x s32>) = G_IMPLICIT_DEF205 %vec1:_(<8 x s32>) = G_IMPLICIT_DEF206 %smin:_(<8 x s32>) = G_SMIN %vec, %vec1207 %1:_(p0) = COPY $x0208 G_STORE %smin(<8 x s32>), %1(p0) :: (store (<8 x s32>))209 210...211---212name: v2s64_smin213tracksRegLiveness: true214body: |215 bb.0:216 liveins: $q0217 218 ; CHECK-LABEL: name: v2s64_smin219 ; CHECK: liveins: $q0220 ; CHECK-NEXT: {{ $}}221 ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF222 ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF223 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1224 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1225 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)226 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]227 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]228 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]229 ; CHECK-NEXT: %smin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]230 ; CHECK-NEXT: $q0 = COPY %smin(<2 x s64>)231 ; CHECK-NEXT: RET_ReallyLR implicit $q0232 %vec:_(<2 x s64>) = G_IMPLICIT_DEF233 %vec1:_(<2 x s64>) = G_IMPLICIT_DEF234 %smin:_(<2 x s64>) = G_SMIN %vec, %vec1235 $q0 = COPY %smin236 RET_ReallyLR implicit $q0237 238...239---240name: v4s64_smin241tracksRegLiveness: true242body: |243 bb.0:244 liveins: $x0, $q0, $q1245 246 ; CHECK-LABEL: name: v4s64_smin247 ; CHECK: liveins: $x0, $q0, $q1248 ; CHECK-NEXT: {{ $}}249 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF250 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]251 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]252 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1253 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)254 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]255 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]256 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]257 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]258 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]259 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]260 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]261 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]262 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0263 ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)264 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16265 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)266 ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)267 %vec:_(<4 x s64>) = G_IMPLICIT_DEF268 %vec1:_(<4 x s64>) = G_IMPLICIT_DEF269 %smin:_(<4 x s64>) = G_SMIN %vec, %vec1270 %1:_(p0) = COPY $x0271 G_STORE %smin(<4 x s64>), %1(p0) :: (store (<4 x s64>))272 273...274---275name: v8s8_umin276tracksRegLiveness: true277body: |278 bb.0:279 liveins: $x0280 281 ; CHECK-LABEL: name: v8s8_umin282 ; CHECK: liveins: $x0283 ; CHECK-NEXT: {{ $}}284 ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF285 ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF286 ; CHECK-NEXT: %umin:_(<8 x s8>) = G_UMIN %vec, %vec1287 ; CHECK-NEXT: $x0 = COPY %umin(<8 x s8>)288 ; CHECK-NEXT: RET_ReallyLR implicit $x0289 %vec:_(<8 x s8>) = G_IMPLICIT_DEF290 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF291 %umin:_(<8 x s8>) = G_UMIN %vec, %vec1292 $x0 = COPY %umin293 RET_ReallyLR implicit $x0294 295...296---297name: v16s8_umin298tracksRegLiveness: true299body: |300 bb.0:301 liveins: $q0302 303 ; CHECK-LABEL: name: v16s8_umin304 ; CHECK: liveins: $q0305 ; CHECK-NEXT: {{ $}}306 ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF307 ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF308 ; CHECK-NEXT: %umin:_(<16 x s8>) = G_UMIN %vec, %vec1309 ; CHECK-NEXT: $q0 = COPY %umin(<16 x s8>)310 ; CHECK-NEXT: RET_ReallyLR implicit $q0311 %vec:_(<16 x s8>) = G_IMPLICIT_DEF312 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF313 %umin:_(<16 x s8>) = G_UMIN %vec, %vec1314 $q0 = COPY %umin315 RET_ReallyLR implicit $q0316 317...318---319name: v32s8_umin320tracksRegLiveness: true321body: |322 bb.0:323 liveins: $x0, $q0, $q1324 325 ; CHECK-LABEL: name: v32s8_umin326 ; CHECK: liveins: $x0, $q0, $q1327 ; CHECK-NEXT: {{ $}}328 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF329 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(<16 x s8>) = G_UMIN [[DEF]], [[DEF]]330 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<16 x s8>) = G_UMIN [[DEF]], [[DEF]]331 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0332 ; CHECK-NEXT: G_STORE [[UMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)333 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16334 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)335 ; CHECK-NEXT: G_STORE [[UMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)336 %vec:_(<32 x s8>) = G_IMPLICIT_DEF337 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF338 %umin:_(<32 x s8>) = G_UMIN %vec, %vec1339 %1:_(p0) = COPY $x0340 G_STORE %umin(<32 x s8>), %1(p0) :: (store (<32 x s8>))341 342...343---344name: v4s16_umin345tracksRegLiveness: true346body: |347 bb.0:348 liveins: $x0349 350 ; CHECK-LABEL: name: v4s16_umin351 ; CHECK: liveins: $x0352 ; CHECK-NEXT: {{ $}}353 ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF354 ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF355 ; CHECK-NEXT: %umin:_(<4 x s16>) = G_UMIN %vec, %vec1356 ; CHECK-NEXT: $x0 = COPY %umin(<4 x s16>)357 ; CHECK-NEXT: RET_ReallyLR implicit $x0358 %vec:_(<4 x s16>) = G_IMPLICIT_DEF359 %vec1:_(<4 x s16>) = G_IMPLICIT_DEF360 %umin:_(<4 x s16>) = G_UMIN %vec, %vec1361 $x0 = COPY %umin362 RET_ReallyLR implicit $x0363 364...365---366name: v8s16_umin367tracksRegLiveness: true368body: |369 bb.0:370 liveins: $q0371 372 ; CHECK-LABEL: name: v8s16_umin373 ; CHECK: liveins: $q0374 ; CHECK-NEXT: {{ $}}375 ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF376 ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF377 ; CHECK-NEXT: %umin:_(<8 x s16>) = G_UMIN %vec, %vec1378 ; CHECK-NEXT: $q0 = COPY %umin(<8 x s16>)379 ; CHECK-NEXT: RET_ReallyLR implicit $q0380 %vec:_(<8 x s16>) = G_IMPLICIT_DEF381 %vec1:_(<8 x s16>) = G_IMPLICIT_DEF382 %umin:_(<8 x s16>) = G_UMIN %vec, %vec1383 $q0 = COPY %umin384 RET_ReallyLR implicit $q0385 386...387---388name: v16s16_umin389tracksRegLiveness: true390body: |391 bb.0:392 liveins: $x0, $q0, $q1393 394 ; CHECK-LABEL: name: v16s16_umin395 ; CHECK: liveins: $x0, $q0, $q1396 ; CHECK-NEXT: {{ $}}397 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF398 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(<8 x s16>) = G_UMIN [[DEF]], [[DEF]]399 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<8 x s16>) = G_UMIN [[DEF]], [[DEF]]400 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0401 ; CHECK-NEXT: G_STORE [[UMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)402 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16403 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)404 ; CHECK-NEXT: G_STORE [[UMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)405 %vec:_(<16 x s16>) = G_IMPLICIT_DEF406 %vec1:_(<16 x s16>) = G_IMPLICIT_DEF407 %umin:_(<16 x s16>) = G_UMIN %vec, %vec1408 %1:_(p0) = COPY $x0409 G_STORE %umin(<16 x s16>), %1(p0) :: (store (<16 x s16>))410 411...412---413name: v2s32_umin414tracksRegLiveness: true415body: |416 bb.0:417 liveins: $x0418 419 ; CHECK-LABEL: name: v2s32_umin420 ; CHECK: liveins: $x0421 ; CHECK-NEXT: {{ $}}422 ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF423 ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF424 ; CHECK-NEXT: %umin:_(<2 x s32>) = G_UMIN %vec, %vec1425 ; CHECK-NEXT: $x0 = COPY %umin(<2 x s32>)426 ; CHECK-NEXT: RET_ReallyLR implicit $x0427 %vec:_(<2 x s32>) = G_IMPLICIT_DEF428 %vec1:_(<2 x s32>) = G_IMPLICIT_DEF429 %umin:_(<2 x s32>) = G_UMIN %vec, %vec1430 $x0 = COPY %umin431 RET_ReallyLR implicit $x0432 433...434---435name: v4s32_umin436tracksRegLiveness: true437body: |438 bb.0:439 liveins: $q0440 441 ; CHECK-LABEL: name: v4s32_umin442 ; CHECK: liveins: $q0443 ; CHECK-NEXT: {{ $}}444 ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF445 ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF446 ; CHECK-NEXT: %umin:_(<4 x s32>) = G_UMIN %vec, %vec1447 ; CHECK-NEXT: $q0 = COPY %umin(<4 x s32>)448 ; CHECK-NEXT: RET_ReallyLR implicit $q0449 %vec:_(<4 x s32>) = G_IMPLICIT_DEF450 %vec1:_(<4 x s32>) = G_IMPLICIT_DEF451 %umin:_(<4 x s32>) = G_UMIN %vec, %vec1452 $q0 = COPY %umin453 RET_ReallyLR implicit $q0454 455...456---457name: v8s32_umin458tracksRegLiveness: true459body: |460 bb.0:461 liveins: $x0, $q0, $q1462 463 ; CHECK-LABEL: name: v8s32_umin464 ; CHECK: liveins: $x0, $q0, $q1465 ; CHECK-NEXT: {{ $}}466 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF467 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(<4 x s32>) = G_UMIN [[DEF]], [[DEF]]468 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<4 x s32>) = G_UMIN [[DEF]], [[DEF]]469 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0470 ; CHECK-NEXT: G_STORE [[UMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)471 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16472 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)473 ; CHECK-NEXT: G_STORE [[UMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)474 %vec:_(<8 x s32>) = G_IMPLICIT_DEF475 %vec1:_(<8 x s32>) = G_IMPLICIT_DEF476 %umin:_(<8 x s32>) = G_UMIN %vec, %vec1477 %1:_(p0) = COPY $x0478 G_STORE %umin(<8 x s32>), %1(p0) :: (store (<8 x s32>))479 480...481---482name: v2s64_umin483tracksRegLiveness: true484body: |485 bb.0:486 liveins: $q0487 488 ; CHECK-LABEL: name: v2s64_umin489 ; CHECK: liveins: $q0490 ; CHECK-NEXT: {{ $}}491 ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF492 ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF493 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1494 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1495 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)496 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]497 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]498 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]499 ; CHECK-NEXT: %umin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]500 ; CHECK-NEXT: $q0 = COPY %umin(<2 x s64>)501 ; CHECK-NEXT: RET_ReallyLR implicit $q0502 %vec:_(<2 x s64>) = G_IMPLICIT_DEF503 %vec1:_(<2 x s64>) = G_IMPLICIT_DEF504 %umin:_(<2 x s64>) = G_UMIN %vec, %vec1505 $q0 = COPY %umin506 RET_ReallyLR implicit $q0507 508...509---510name: v4s64_umin511tracksRegLiveness: true512body: |513 bb.0:514 liveins: $x0, $q0, $q1515 516 ; CHECK-LABEL: name: v4s64_umin517 ; CHECK: liveins: $x0, $q0, $q1518 ; CHECK-NEXT: {{ $}}519 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF520 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]521 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]522 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1523 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)524 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]525 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]526 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]527 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]528 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]529 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]530 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]531 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]532 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0533 ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)534 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16535 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)536 ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)537 %vec:_(<4 x s64>) = G_IMPLICIT_DEF538 %vec1:_(<4 x s64>) = G_IMPLICIT_DEF539 %umin:_(<4 x s64>) = G_UMIN %vec, %vec1540 %1:_(p0) = COPY $x0541 G_STORE %umin(<4 x s64>), %1(p0) :: (store (<4 x s64>))542 543...544---545name: v8s8_smax546tracksRegLiveness: true547body: |548 bb.0:549 liveins: $x0550 551 ; CHECK-LABEL: name: v8s8_smax552 ; CHECK: liveins: $x0553 ; CHECK-NEXT: {{ $}}554 ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF555 ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF556 ; CHECK-NEXT: %smax:_(<8 x s8>) = G_SMAX %vec, %vec1557 ; CHECK-NEXT: $x0 = COPY %smax(<8 x s8>)558 ; CHECK-NEXT: RET_ReallyLR implicit $x0559 %vec:_(<8 x s8>) = G_IMPLICIT_DEF560 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF561 %smax:_(<8 x s8>) = G_SMAX %vec, %vec1562 $x0 = COPY %smax563 RET_ReallyLR implicit $x0564 565...566---567name: v16s8_smax568tracksRegLiveness: true569body: |570 bb.0:571 liveins: $q0572 573 ; CHECK-LABEL: name: v16s8_smax574 ; CHECK: liveins: $q0575 ; CHECK-NEXT: {{ $}}576 ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF577 ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF578 ; CHECK-NEXT: %smax:_(<16 x s8>) = G_SMAX %vec, %vec1579 ; CHECK-NEXT: $q0 = COPY %smax(<16 x s8>)580 ; CHECK-NEXT: RET_ReallyLR implicit $q0581 %vec:_(<16 x s8>) = G_IMPLICIT_DEF582 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF583 %smax:_(<16 x s8>) = G_SMAX %vec, %vec1584 $q0 = COPY %smax585 RET_ReallyLR implicit $q0586 587...588---589name: v4s16_smax590tracksRegLiveness: true591body: |592 bb.0:593 liveins: $x0594 595 ; CHECK-LABEL: name: v4s16_smax596 ; CHECK: liveins: $x0597 ; CHECK-NEXT: {{ $}}598 ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF599 ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF600 ; CHECK-NEXT: %smax:_(<4 x s16>) = G_SMAX %vec, %vec1601 ; CHECK-NEXT: $x0 = COPY %smax(<4 x s16>)602 ; CHECK-NEXT: RET_ReallyLR implicit $x0603 %vec:_(<4 x s16>) = G_IMPLICIT_DEF604 %vec1:_(<4 x s16>) = G_IMPLICIT_DEF605 %smax:_(<4 x s16>) = G_SMAX %vec, %vec1606 $x0 = COPY %smax607 RET_ReallyLR implicit $x0608 609...610---611name: v32s8_smax612tracksRegLiveness: true613body: |614 bb.0:615 liveins: $x0, $q0, $q1616 617 ; CHECK-LABEL: name: v32s8_smax618 ; CHECK: liveins: $x0, $q0, $q1619 ; CHECK-NEXT: {{ $}}620 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF621 ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(<16 x s8>) = G_SMAX [[DEF]], [[DEF]]622 ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<16 x s8>) = G_SMAX [[DEF]], [[DEF]]623 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0624 ; CHECK-NEXT: G_STORE [[SMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)625 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16626 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)627 ; CHECK-NEXT: G_STORE [[SMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)628 %vec:_(<32 x s8>) = G_IMPLICIT_DEF629 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF630 %smax:_(<32 x s8>) = G_SMAX %vec, %vec1631 %1:_(p0) = COPY $x0632 G_STORE %smax(<32 x s8>), %1(p0) :: (store (<32 x s8>))633 634...635---636name: v8s16_smax637tracksRegLiveness: true638body: |639 bb.0:640 liveins: $q0641 642 ; CHECK-LABEL: name: v8s16_smax643 ; CHECK: liveins: $q0644 ; CHECK-NEXT: {{ $}}645 ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF646 ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF647 ; CHECK-NEXT: %smax:_(<8 x s16>) = G_SMAX %vec, %vec1648 ; CHECK-NEXT: $q0 = COPY %smax(<8 x s16>)649 ; CHECK-NEXT: RET_ReallyLR implicit $q0650 %vec:_(<8 x s16>) = G_IMPLICIT_DEF651 %vec1:_(<8 x s16>) = G_IMPLICIT_DEF652 %smax:_(<8 x s16>) = G_SMAX %vec, %vec1653 $q0 = COPY %smax654 RET_ReallyLR implicit $q0655 656...657---658name: v16s16_smax659tracksRegLiveness: true660body: |661 bb.0:662 liveins: $x0, $q0, $q1663 664 ; CHECK-LABEL: name: v16s16_smax665 ; CHECK: liveins: $x0, $q0, $q1666 ; CHECK-NEXT: {{ $}}667 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF668 ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(<8 x s16>) = G_SMAX [[DEF]], [[DEF]]669 ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<8 x s16>) = G_SMAX [[DEF]], [[DEF]]670 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0671 ; CHECK-NEXT: G_STORE [[SMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)672 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16673 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)674 ; CHECK-NEXT: G_STORE [[SMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)675 %vec:_(<16 x s16>) = G_IMPLICIT_DEF676 %vec1:_(<16 x s16>) = G_IMPLICIT_DEF677 %smax:_(<16 x s16>) = G_SMAX %vec, %vec1678 %1:_(p0) = COPY $x0679 G_STORE %smax(<16 x s16>), %1(p0) :: (store (<16 x s16>))680 681...682---683name: v2s32_smax684tracksRegLiveness: true685body: |686 bb.0:687 liveins: $x0688 689 ; CHECK-LABEL: name: v2s32_smax690 ; CHECK: liveins: $x0691 ; CHECK-NEXT: {{ $}}692 ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF693 ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF694 ; CHECK-NEXT: %smax:_(<2 x s32>) = G_SMAX %vec, %vec1695 ; CHECK-NEXT: $x0 = COPY %smax(<2 x s32>)696 ; CHECK-NEXT: RET_ReallyLR implicit $x0697 %vec:_(<2 x s32>) = G_IMPLICIT_DEF698 %vec1:_(<2 x s32>) = G_IMPLICIT_DEF699 %smax:_(<2 x s32>) = G_SMAX %vec, %vec1700 $x0 = COPY %smax701 RET_ReallyLR implicit $x0702 703...704---705name: v4s32_smax706tracksRegLiveness: true707body: |708 bb.0:709 liveins: $q0710 711 ; CHECK-LABEL: name: v4s32_smax712 ; CHECK: liveins: $q0713 ; CHECK-NEXT: {{ $}}714 ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF715 ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF716 ; CHECK-NEXT: %smax:_(<4 x s32>) = G_SMAX %vec, %vec1717 ; CHECK-NEXT: $q0 = COPY %smax(<4 x s32>)718 ; CHECK-NEXT: RET_ReallyLR implicit $q0719 %vec:_(<4 x s32>) = G_IMPLICIT_DEF720 %vec1:_(<4 x s32>) = G_IMPLICIT_DEF721 %smax:_(<4 x s32>) = G_SMAX %vec, %vec1722 $q0 = COPY %smax723 RET_ReallyLR implicit $q0724 725...726---727name: v8s32_smax728tracksRegLiveness: true729body: |730 bb.0:731 liveins: $x0, $q0, $q1732 733 ; CHECK-LABEL: name: v8s32_smax734 ; CHECK: liveins: $x0, $q0, $q1735 ; CHECK-NEXT: {{ $}}736 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF737 ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(<4 x s32>) = G_SMAX [[DEF]], [[DEF]]738 ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<4 x s32>) = G_SMAX [[DEF]], [[DEF]]739 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0740 ; CHECK-NEXT: G_STORE [[SMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)741 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16742 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)743 ; CHECK-NEXT: G_STORE [[SMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)744 %vec:_(<8 x s32>) = G_IMPLICIT_DEF745 %vec1:_(<8 x s32>) = G_IMPLICIT_DEF746 %smax:_(<8 x s32>) = G_SMAX %vec, %vec1747 %1:_(p0) = COPY $x0748 G_STORE %smax(<8 x s32>), %1(p0) :: (store (<8 x s32>))749 750...751---752name: v2s64_smax753tracksRegLiveness: true754body: |755 bb.0:756 liveins: $q0757 758 ; CHECK-LABEL: name: v2s64_smax759 ; CHECK: liveins: $q0760 ; CHECK-NEXT: {{ $}}761 ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF762 ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF763 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1764 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1765 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)766 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]767 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]768 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]769 ; CHECK-NEXT: %smax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]770 ; CHECK-NEXT: $q0 = COPY %smax(<2 x s64>)771 ; CHECK-NEXT: RET_ReallyLR implicit $q0772 %vec:_(<2 x s64>) = G_IMPLICIT_DEF773 %vec1:_(<2 x s64>) = G_IMPLICIT_DEF774 %smax:_(<2 x s64>) = G_SMAX %vec, %vec1775 $q0 = COPY %smax776 RET_ReallyLR implicit $q0777 778...779---780name: v4s64_smax781tracksRegLiveness: true782body: |783 bb.0:784 liveins: $x0, $q0, $q1785 786 ; CHECK-LABEL: name: v4s64_smax787 ; CHECK: liveins: $x0, $q0, $q1788 ; CHECK-NEXT: {{ $}}789 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF790 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]791 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]792 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1793 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)794 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]795 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]796 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]797 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]798 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]799 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]800 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]801 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]802 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0803 ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)804 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16805 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)806 ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)807 %vec:_(<4 x s64>) = G_IMPLICIT_DEF808 %vec1:_(<4 x s64>) = G_IMPLICIT_DEF809 %smax:_(<4 x s64>) = G_SMAX %vec, %vec1810 %1:_(p0) = COPY $x0811 G_STORE %smax(<4 x s64>), %1(p0) :: (store (<4 x s64>))812 813...814---815name: v8s8_umax816tracksRegLiveness: true817body: |818 bb.0:819 liveins: $x0820 821 ; CHECK-LABEL: name: v8s8_umax822 ; CHECK: liveins: $x0823 ; CHECK-NEXT: {{ $}}824 ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF825 ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF826 ; CHECK-NEXT: %umax:_(<8 x s8>) = G_UMAX %vec, %vec1827 ; CHECK-NEXT: $x0 = COPY %umax(<8 x s8>)828 ; CHECK-NEXT: RET_ReallyLR implicit $x0829 %vec:_(<8 x s8>) = G_IMPLICIT_DEF830 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF831 %umax:_(<8 x s8>) = G_UMAX %vec, %vec1832 $x0 = COPY %umax833 RET_ReallyLR implicit $x0834 835...836---837name: v16s8_umax838tracksRegLiveness: true839body: |840 bb.0:841 liveins: $q0842 843 ; CHECK-LABEL: name: v16s8_umax844 ; CHECK: liveins: $q0845 ; CHECK-NEXT: {{ $}}846 ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF847 ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF848 ; CHECK-NEXT: %umax:_(<16 x s8>) = G_UMAX %vec, %vec1849 ; CHECK-NEXT: $q0 = COPY %umax(<16 x s8>)850 ; CHECK-NEXT: RET_ReallyLR implicit $q0851 %vec:_(<16 x s8>) = G_IMPLICIT_DEF852 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF853 %umax:_(<16 x s8>) = G_UMAX %vec, %vec1854 $q0 = COPY %umax855 RET_ReallyLR implicit $q0856 857...858---859name: v32s8_umax860tracksRegLiveness: true861body: |862 bb.0:863 liveins: $x0, $q0, $q1864 865 ; CHECK-LABEL: name: v32s8_umax866 ; CHECK: liveins: $x0, $q0, $q1867 ; CHECK-NEXT: {{ $}}868 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF869 ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(<16 x s8>) = G_UMAX [[DEF]], [[DEF]]870 ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<16 x s8>) = G_UMAX [[DEF]], [[DEF]]871 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0872 ; CHECK-NEXT: G_STORE [[UMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)873 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16874 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)875 ; CHECK-NEXT: G_STORE [[UMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16)876 %vec:_(<32 x s8>) = G_IMPLICIT_DEF877 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF878 %umax:_(<32 x s8>) = G_UMAX %vec, %vec1879 %1:_(p0) = COPY $x0880 G_STORE %umax(<32 x s8>), %1(p0) :: (store (<32 x s8>))881 882...883---884name: v4s16_umax885tracksRegLiveness: true886body: |887 bb.0:888 liveins: $x0889 890 ; CHECK-LABEL: name: v4s16_umax891 ; CHECK: liveins: $x0892 ; CHECK-NEXT: {{ $}}893 ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF894 ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF895 ; CHECK-NEXT: %umax:_(<4 x s16>) = G_UMAX %vec, %vec1896 ; CHECK-NEXT: $x0 = COPY %umax(<4 x s16>)897 ; CHECK-NEXT: RET_ReallyLR implicit $x0898 %vec:_(<4 x s16>) = G_IMPLICIT_DEF899 %vec1:_(<4 x s16>) = G_IMPLICIT_DEF900 %umax:_(<4 x s16>) = G_UMAX %vec, %vec1901 $x0 = COPY %umax902 RET_ReallyLR implicit $x0903 904...905---906name: v8s16_umax907tracksRegLiveness: true908body: |909 bb.0:910 liveins: $q0911 912 ; CHECK-LABEL: name: v8s16_umax913 ; CHECK: liveins: $q0914 ; CHECK-NEXT: {{ $}}915 ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF916 ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF917 ; CHECK-NEXT: %umax:_(<8 x s16>) = G_UMAX %vec, %vec1918 ; CHECK-NEXT: $q0 = COPY %umax(<8 x s16>)919 ; CHECK-NEXT: RET_ReallyLR implicit $q0920 %vec:_(<8 x s16>) = G_IMPLICIT_DEF921 %vec1:_(<8 x s16>) = G_IMPLICIT_DEF922 %umax:_(<8 x s16>) = G_UMAX %vec, %vec1923 $q0 = COPY %umax924 RET_ReallyLR implicit $q0925 926...927---928name: v16s16_umax929tracksRegLiveness: true930body: |931 bb.0:932 liveins: $x0, $q0, $q1933 934 ; CHECK-LABEL: name: v16s16_umax935 ; CHECK: liveins: $x0, $q0, $q1936 ; CHECK-NEXT: {{ $}}937 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF938 ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(<8 x s16>) = G_UMAX [[DEF]], [[DEF]]939 ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<8 x s16>) = G_UMAX [[DEF]], [[DEF]]940 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0941 ; CHECK-NEXT: G_STORE [[UMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)942 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16943 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)944 ; CHECK-NEXT: G_STORE [[UMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16)945 %vec:_(<16 x s16>) = G_IMPLICIT_DEF946 %vec1:_(<16 x s16>) = G_IMPLICIT_DEF947 %umax:_(<16 x s16>) = G_UMAX %vec, %vec1948 %1:_(p0) = COPY $x0949 G_STORE %umax(<16 x s16>), %1(p0) :: (store (<16 x s16>))950 951...952---953name: v2s32_umax954tracksRegLiveness: true955body: |956 bb.0:957 liveins: $x0958 959 ; CHECK-LABEL: name: v2s32_umax960 ; CHECK: liveins: $x0961 ; CHECK-NEXT: {{ $}}962 ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF963 ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF964 ; CHECK-NEXT: %umax:_(<2 x s32>) = G_UMAX %vec, %vec1965 ; CHECK-NEXT: $x0 = COPY %umax(<2 x s32>)966 ; CHECK-NEXT: RET_ReallyLR implicit $x0967 %vec:_(<2 x s32>) = G_IMPLICIT_DEF968 %vec1:_(<2 x s32>) = G_IMPLICIT_DEF969 %umax:_(<2 x s32>) = G_UMAX %vec, %vec1970 $x0 = COPY %umax971 RET_ReallyLR implicit $x0972 973...974---975name: v4s32_umax976tracksRegLiveness: true977body: |978 bb.0:979 liveins: $q0980 981 ; CHECK-LABEL: name: v4s32_umax982 ; CHECK: liveins: $q0983 ; CHECK-NEXT: {{ $}}984 ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF985 ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF986 ; CHECK-NEXT: %umax:_(<4 x s32>) = G_UMAX %vec, %vec1987 ; CHECK-NEXT: $q0 = COPY %umax(<4 x s32>)988 ; CHECK-NEXT: RET_ReallyLR implicit $q0989 %vec:_(<4 x s32>) = G_IMPLICIT_DEF990 %vec1:_(<4 x s32>) = G_IMPLICIT_DEF991 %umax:_(<4 x s32>) = G_UMAX %vec, %vec1992 $q0 = COPY %umax993 RET_ReallyLR implicit $q0994 995...996---997name: v8s32_umax998tracksRegLiveness: true999body: |1000 bb.0:1001 liveins: $x0, $q0, $q11002 1003 ; CHECK-LABEL: name: v8s32_umax1004 ; CHECK: liveins: $x0, $q0, $q11005 ; CHECK-NEXT: {{ $}}1006 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF1007 ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(<4 x s32>) = G_UMAX [[DEF]], [[DEF]]1008 ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<4 x s32>) = G_UMAX [[DEF]], [[DEF]]1009 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x01010 ; CHECK-NEXT: G_STORE [[UMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)1011 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 161012 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)1013 ; CHECK-NEXT: G_STORE [[UMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16)1014 %vec:_(<8 x s32>) = G_IMPLICIT_DEF1015 %vec1:_(<8 x s32>) = G_IMPLICIT_DEF1016 %umax:_(<8 x s32>) = G_UMAX %vec, %vec11017 %1:_(p0) = COPY $x01018 G_STORE %umax(<8 x s32>), %1(p0) :: (store (<8 x s32>))1019 1020...1021---1022name: v2s64_umax1023tracksRegLiveness: true1024body: |1025 bb.0:1026 liveins: $q01027 1028 ; CHECK-LABEL: name: v2s64_umax1029 ; CHECK: liveins: $q01030 ; CHECK-NEXT: {{ $}}1031 ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF1032 ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF1033 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec11034 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11035 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)1036 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]1037 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]]1038 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]1039 ; CHECK-NEXT: %umax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]1040 ; CHECK-NEXT: $q0 = COPY %umax(<2 x s64>)1041 ; CHECK-NEXT: RET_ReallyLR implicit $q01042 %vec:_(<2 x s64>) = G_IMPLICIT_DEF1043 %vec1:_(<2 x s64>) = G_IMPLICIT_DEF1044 %umax:_(<2 x s64>) = G_UMAX %vec, %vec11045 $q0 = COPY %umax1046 RET_ReallyLR implicit $q01047 1048...1049---1050name: v4s64_umax1051tracksRegLiveness: true1052body: |1053 bb.0:1054 liveins: $x0, $q0, $q11055 1056 ; CHECK-LABEL: name: v4s64_umax1057 ; CHECK: liveins: $x0, $q0, $q11058 ; CHECK-NEXT: {{ $}}1059 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF1060 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]1061 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]1062 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11063 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)1064 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]1065 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]1066 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]1067 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]1068 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]1069 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]1070 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]1071 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]1072 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x01073 ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)1074 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 161075 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C1]](s64)1076 ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)1077 %vec:_(<4 x s64>) = G_IMPLICIT_DEF1078 %vec1:_(<4 x s64>) = G_IMPLICIT_DEF1079 %umax:_(<4 x s64>) = G_UMAX %vec, %vec11080 %1:_(p0) = COPY $x01081 G_STORE %umax(<4 x s64>), %1(p0) :: (store (<4 x s64>))1082 1083...1084 1085