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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s3---4name: test_scalar_mul_small5body: |6 bb.0.entry:7 ; CHECK-LABEL: name: test_scalar_mul_small8 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x09 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x110 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)11 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)12 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]13 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)14 ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)15 %0:_(s64) = COPY $x016 %1:_(s64) = COPY $x117 %2:_(s8) = G_TRUNC %0(s64)18 %3:_(s8) = G_TRUNC %1(s64)19 %4:_(s8) = G_MUL %2, %320 %5:_(s64) = G_ANYEXT %4(s8)21 $x0 = COPY %5(s64)22 23...24---25name: test_smul_overflow26body: |27 bb.0:28 ; CHECK-LABEL: name: test_smul_overflow29 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x030 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x131 ; CHECK-NEXT: [[SMULH:%[0-9]+]]:_(s64) = G_SMULH [[COPY]], [[COPY1]]32 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]33 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 6334 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[MUL]], [[C]](s64)35 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[ASHR]]36 ; CHECK-NEXT: $x0 = COPY [[MUL]](s64)37 ; CHECK-NEXT: $w0 = COPY [[ICMP]](s32)38 %0:_(s64) = COPY $x039 %1:_(s64) = COPY $x140 %2:_(s64), %3:_(s1) = G_SMULO %0, %141 $x0 = COPY %2(s64)42 %4:_(s32) = G_ANYEXT %3(s1)43 $w0 = COPY %4(s32)44 45...46---47name: test_umul_overflow48body: |49 bb.0:50 ; CHECK-LABEL: name: test_umul_overflow51 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x052 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x153 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH [[COPY]], [[COPY1]]54 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 055 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]56 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s64), [[C]]57 ; CHECK-NEXT: $x0 = COPY [[MUL]](s64)58 ; CHECK-NEXT: $w0 = COPY [[ICMP]](s32)59 %0:_(s64) = COPY $x060 %1:_(s64) = COPY $x161 %2:_(s64), %3:_(s1) = G_UMULO %0, %162 $x0 = COPY %2(s64)63 %4:_(s32) = G_ANYEXT %3(s1)64 $w0 = COPY %4(s32)65 66...67---68name: test_smul_overflow_s3269body: |70 bb.0:71 ; CHECK-LABEL: name: test_smul_overflow_s3272 ; CHECK: %lhs:_(s32) = COPY $w073 ; CHECK-NEXT: %rhs:_(s32) = COPY $w174 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT %lhs(s32)75 ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT %rhs(s32)76 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[SEXT1]]77 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3278 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[MUL]], [[C]](s64)79 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASHR]](s64)80 ; CHECK-NEXT: %mul:_(s32) = G_MUL %lhs, %rhs81 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3182 ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR %mul, [[C1]](s64)83 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[TRUNC]](s32), [[ASHR1]]84 ; CHECK-NEXT: $w0 = COPY %mul(s32)85 ; CHECK-NEXT: $w0 = COPY [[ICMP]](s32)86 ; CHECK-NEXT: RET_ReallyLR implicit $w087 %lhs:_(s32) = COPY $w088 %rhs:_(s32) = COPY $w189 %mul:_(s32), %overflow:_(s1) = G_SMULO %lhs, %rhs90 $w0 = COPY %mul(s32)91 %ext_overflow:_(s32) = G_ANYEXT %overflow(s1)92 $w0 = COPY %ext_overflow(s32)93 RET_ReallyLR implicit $w094 95...96---97name: test_umul_overflow_s3298body: |99 bb.0:100 ; CHECK-LABEL: name: test_umul_overflow_s32101 ; CHECK: %lhs:_(s32) = COPY $w0102 ; CHECK-NEXT: %rhs:_(s32) = COPY $w1103 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT %lhs(s32)104 ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT %rhs(s32)105 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[ZEXT1]]106 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32107 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C]](s64)108 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)109 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0110 ; CHECK-NEXT: %mul:_(s32) = G_MUL %lhs, %rhs111 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[TRUNC]](s32), [[C1]]112 ; CHECK-NEXT: $w0 = COPY %mul(s32)113 ; CHECK-NEXT: $w0 = COPY [[ICMP]](s32)114 ; CHECK-NEXT: RET_ReallyLR implicit $w0115 %lhs:_(s32) = COPY $w0116 %rhs:_(s32) = COPY $w1117 %mul:_(s32), %overflow:_(s1) = G_UMULO %lhs, %rhs118 $w0 = COPY %mul(s32)119 %ext_overflow:_(s32) = G_ANYEXT %overflow(s1)120 $w0 = COPY %ext_overflow(s32)121 RET_ReallyLR implicit $w0122 123...124---125name: test_umul_overflow_s24126body: |127 bb.0:128 ; CHECK-LABEL: name: test_umul_overflow_s24129 ; CHECK: %lhs_wide:_(s32) = COPY $w0130 ; CHECK-NEXT: %rhs_wide:_(s32) = COPY $w1131 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215132 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %lhs_wide, [[C]]133 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND %rhs_wide, [[C]]134 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT %lhs_wide(s32)135 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215136 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]137 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT %rhs_wide(s32)138 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C1]]139 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND2]], [[AND3]]140 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32141 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C2]](s64)142 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)143 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0144 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]145 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[TRUNC]](s32), [[C3]]146 ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]147 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND4]]148 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[ICMP1]]149 ; CHECK-NEXT: $w0 = COPY [[MUL1]](s32)150 ; CHECK-NEXT: $w0 = COPY [[OR]](s32)151 ; CHECK-NEXT: RET_ReallyLR implicit $w0152 %lhs_wide:_(s32) = COPY $w0153 %rhs_wide:_(s32) = COPY $w1154 %lhs:_(s24) = G_TRUNC %lhs_wide155 %rhs:_(s24) = G_TRUNC %rhs_wide156 %mul:_(s24), %overflow:_(s1) = G_UMULO %lhs, %rhs157 %ext_mul:_(s32) = G_ANYEXT %mul158 $w0 = COPY %ext_mul(s32)159 %ext_overflow:_(s32) = G_ANYEXT %overflow(s1)160 $w0 = COPY %ext_overflow(s32)161 RET_ReallyLR implicit $w0162 163...164---165name: vector_mul_scalarize166liveins:167 - { reg: '$q0' }168 - { reg: '$q1' }169body: |170 bb.1:171 liveins: $q0, $q1172 173 ; CHECK-LABEL: name: vector_mul_scalarize174 ; CHECK: liveins: $q0, $q1175 ; CHECK-NEXT: {{ $}}176 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0177 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1178 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[COPY]], [[COPY1]]179 ; CHECK-NEXT: $q0 = COPY [[MUL]](<2 x s64>)180 ; CHECK-NEXT: RET_ReallyLR implicit $q0181 %0:_(<2 x s64>) = COPY $q0182 %1:_(<2 x s64>) = COPY $q1183 %2:_(<2 x s64>) = G_MUL %0, %1184 $q0 = COPY %2(<2 x s64>)185 RET_ReallyLR implicit $q0186...187---188name: test_umulo_overflow_no_invalid_mir189alignment: 4190tracksRegLiveness: true191liveins:192 - { reg: '$x0' }193 - { reg: '$x1' }194 - { reg: '$x2' }195frameInfo:196 maxAlignment: 16197stack:198 - { id: 0, size: 8, alignment: 8 }199 - { id: 1, size: 8, alignment: 8 }200 - { id: 2, size: 16, alignment: 16 }201 - { id: 3, size: 16, alignment: 8 }202machineFunctionInfo: {}203body: |204 bb.1:205 liveins: $x0, $x1, $x2206 ; Check that the overflow result doesn't generate incorrect MIR by using a G_CONSTANT 0207 ; before it's been defined.208 ; CHECK-LABEL: name: test_umulo_overflow_no_invalid_mir209 ; CHECK: liveins: $x0, $x1, $x2210 ; CHECK-NEXT: {{ $}}211 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0212 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1213 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2214 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0215 ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1216 ; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.3217 ; CHECK-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX]](p0) :: (store (s64))218 ; CHECK-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX1]](p0) :: (store (s64))219 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64))220 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (s64))221 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH [[LOAD]], [[LOAD1]]222 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0223 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[LOAD]], [[LOAD1]]224 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s64), [[C]]225 ; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX2]](p0) :: (store (s64), align 1)226 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)227 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1228 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]229 ; CHECK-NEXT: $x0 = COPY [[MUL]](s64)230 ; CHECK-NEXT: $x1 = COPY [[AND]](s64)231 ; CHECK-NEXT: RET_ReallyLR implicit $x0232 %0:_(p0) = COPY $x0233 %1:_(s64) = COPY $x1234 %2:_(s64) = COPY $x2235 %25:_(s32) = G_CONSTANT i32 0236 %3:_(p0) = G_FRAME_INDEX %stack.0237 %4:_(p0) = G_FRAME_INDEX %stack.1238 %6:_(p0) = G_FRAME_INDEX %stack.3239 G_STORE %2(s64), %3(p0) :: (store (s64))240 G_STORE %1(s64), %4(p0) :: (store (s64))241 %7:_(s64) = G_LOAD %3(p0) :: (dereferenceable load (s64))242 %8:_(s64) = G_LOAD %4(p0) :: (dereferenceable load (s64))243 %9:_(s64), %10:_(s1) = G_UMULO %7, %8244 %31:_(s64) = G_CONSTANT i64 0245 G_STORE %31(s64), %6(p0) :: (store (s64), align 1)246 %16:_(s64) = G_ZEXT %10(s1)247 $x0 = COPY %9(s64)248 $x1 = COPY %16(s64)249 RET_ReallyLR implicit $x0250 251...252---253name: umulh_s32254exposesReturnsTwice: false255tracksRegLiveness: true256body: |257 bb.1:258 liveins: $w0, $w1259 260 ; CHECK-LABEL: name: umulh_s32261 ; CHECK: liveins: $w0, $w1262 ; CHECK-NEXT: {{ $}}263 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0264 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1265 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)266 ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)267 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[ZEXT1]]268 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32269 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MUL]], [[C]](s64)270 ; CHECK-NEXT: %mul:_(s32) = G_TRUNC [[LSHR]](s64)271 ; CHECK-NEXT: $w0 = COPY %mul(s32)272 ; CHECK-NEXT: RET_ReallyLR implicit $w0273 %0:_(s32) = COPY $w0274 %1:_(s32) = COPY $w1275 %mul:_(s32) = G_UMULH %0, %1276 $w0 = COPY %mul(s32)277 RET_ReallyLR implicit $w0278 279...280---281name: smulh_s32282exposesReturnsTwice: false283tracksRegLiveness: true284body: |285 bb.1:286 liveins: $w0, $w1287 288 ; CHECK-LABEL: name: smulh_s32289 ; CHECK: liveins: $w0, $w1290 ; CHECK-NEXT: {{ $}}291 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0292 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1293 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)294 ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)295 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[SEXT1]]296 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32297 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[MUL]], [[C]](s64)298 ; CHECK-NEXT: %mul:_(s32) = G_TRUNC [[ASHR]](s64)299 ; CHECK-NEXT: $w0 = COPY %mul(s32)300 ; CHECK-NEXT: RET_ReallyLR implicit $w0301 %0:_(s32) = COPY $w0302 %1:_(s32) = COPY $w1303 %mul:_(s32) = G_SMULH %0, %1304 $w0 = COPY %mul(s32)305 RET_ReallyLR implicit $w0306 307...308---309name: umulh_v8s16310exposesReturnsTwice: false311tracksRegLiveness: true312liveins:313 - { reg: '$q0', virtual-reg: '' }314body: |315 bb.1:316 liveins: $q0, $q1317 318 ; CHECK-LABEL: name: umulh_v8s16319 ; CHECK: liveins: $q0, $q1320 ; CHECK-NEXT: {{ $}}321 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0322 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1323 ; CHECK-NEXT: %mul:_(<8 x s16>) = G_UMULH [[COPY]], [[COPY1]]324 ; CHECK-NEXT: $q0 = COPY %mul(<8 x s16>)325 ; CHECK-NEXT: RET_ReallyLR implicit $q0326 %0:_(<8 x s16>) = COPY $q0327 %1:_(<8 x s16>) = COPY $q1328 %mul:_(<8 x s16>) = G_UMULH %0, %1329 $q0 = COPY %mul(<8 x s16>)330 RET_ReallyLR implicit $q0331 332...333---334name: umulh_v16s8335exposesReturnsTwice: false336tracksRegLiveness: true337liveins:338 - { reg: '$q0', virtual-reg: '' }339body: |340 bb.1:341 liveins: $q0, $q1342 343 ; CHECK-LABEL: name: umulh_v16s8344 ; CHECK: liveins: $q0, $q1345 ; CHECK-NEXT: {{ $}}346 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0347 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1348 ; CHECK-NEXT: %mul:_(<16 x s8>) = G_UMULH [[COPY]], [[COPY1]]349 ; CHECK-NEXT: $q0 = COPY %mul(<16 x s8>)350 ; CHECK-NEXT: RET_ReallyLR implicit $q0351 %0:_(<16 x s8>) = COPY $q0352 %1:_(<16 x s8>) = COPY $q1353 %mul:_(<16 x s8>) = G_UMULH %0, %1354 $q0 = COPY %mul(<16 x s8>)355 RET_ReallyLR implicit $q0356 357...358---359name: umulh_v4s32360exposesReturnsTwice: false361tracksRegLiveness: true362liveins:363 - { reg: '$q0', virtual-reg: '' }364body: |365 bb.1:366 liveins: $q0, $q1367 368 ; CHECK-LABEL: name: umulh_v4s32369 ; CHECK: liveins: $q0, $q1370 ; CHECK-NEXT: {{ $}}371 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0372 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1373 ; CHECK-NEXT: %mul:_(<4 x s32>) = G_UMULH [[COPY]], [[COPY1]]374 ; CHECK-NEXT: $q0 = COPY %mul(<4 x s32>)375 ; CHECK-NEXT: RET_ReallyLR implicit $q0376 %0:_(<4 x s32>) = COPY $q0377 %1:_(<4 x s32>) = COPY $q1378 %mul:_(<4 x s32>) = G_UMULH %0, %1379 $q0 = COPY %mul(<4 x s32>)380 RET_ReallyLR implicit $q0381 382...383---384name: smulh_v8s16385exposesReturnsTwice: false386tracksRegLiveness: true387liveins:388 - { reg: '$q0', virtual-reg: '' }389body: |390 bb.1:391 liveins: $q0, $q1392 393 ; CHECK-LABEL: name: smulh_v8s16394 ; CHECK: liveins: $q0, $q1395 ; CHECK-NEXT: {{ $}}396 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0397 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1398 ; CHECK-NEXT: %mul:_(<8 x s16>) = G_SMULH [[COPY]], [[COPY1]]399 ; CHECK-NEXT: $q0 = COPY %mul(<8 x s16>)400 ; CHECK-NEXT: RET_ReallyLR implicit $q0401 %0:_(<8 x s16>) = COPY $q0402 %1:_(<8 x s16>) = COPY $q1403 %mul:_(<8 x s16>) = G_SMULH %0, %1404 $q0 = COPY %mul(<8 x s16>)405 RET_ReallyLR implicit $q0406 407...408---409name: smulh_v16s8410exposesReturnsTwice: false411tracksRegLiveness: true412liveins:413 - { reg: '$q0', virtual-reg: '' }414body: |415 bb.1:416 liveins: $q0, $q1417 418 ; CHECK-LABEL: name: smulh_v16s8419 ; CHECK: liveins: $q0, $q1420 ; CHECK-NEXT: {{ $}}421 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0422 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1423 ; CHECK-NEXT: %mul:_(<16 x s8>) = G_SMULH [[COPY]], [[COPY1]]424 ; CHECK-NEXT: $q0 = COPY %mul(<16 x s8>)425 ; CHECK-NEXT: RET_ReallyLR implicit $q0426 %0:_(<16 x s8>) = COPY $q0427 %1:_(<16 x s8>) = COPY $q1428 %mul:_(<16 x s8>) = G_SMULH %0, %1429 $q0 = COPY %mul(<16 x s8>)430 RET_ReallyLR implicit $q0431 432...433---434name: smulh_v4s32435exposesReturnsTwice: false436tracksRegLiveness: true437liveins:438 - { reg: '$q0', virtual-reg: '' }439body: |440 bb.1:441 liveins: $q0, $q1442 443 ; CHECK-LABEL: name: smulh_v4s32444 ; CHECK: liveins: $q0, $q1445 ; CHECK-NEXT: {{ $}}446 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0447 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1448 ; CHECK-NEXT: %mul:_(<4 x s32>) = G_SMULH [[COPY]], [[COPY1]]449 ; CHECK-NEXT: $q0 = COPY %mul(<4 x s32>)450 ; CHECK-NEXT: RET_ReallyLR implicit $q0451 %0:_(<4 x s32>) = COPY $q0452 %1:_(<4 x s32>) = COPY $q1453 %mul:_(<4 x s32>) = G_SMULH %0, %1454 $q0 = COPY %mul(<4 x s32>)455 RET_ReallyLR implicit $q0456 457...458---459name: test_vector_mul_v16s16460body: |461 bb.0.entry:462 ; CHECK-LABEL: name: test_vector_mul_v16s16463 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0464 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1465 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[COPY]], [[COPY]]466 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<8 x s16>) = G_MUL [[COPY1]], [[COPY1]]467 ; CHECK-NEXT: $q0 = COPY [[MUL]](<8 x s16>)468 ; CHECK-NEXT: $q1 = COPY [[MUL1]](<8 x s16>)469 %1:_(<8 x s16>) = COPY $q0470 %2:_(<8 x s16>) = COPY $q1471 %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)472 %3:_(<16 x s16>) = G_MUL %0, %0473 %4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)474 $q0 = COPY %4(<8 x s16>)475 $q1 = COPY %5(<8 x s16>)476 477...478---479name: test_vector_mul_v32s8480body: |481 bb.0.entry:482 ; CHECK-LABEL: name: test_vector_mul_v32s8483 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0484 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1485 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[COPY]], [[COPY]]486 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<16 x s8>) = G_MUL [[COPY1]], [[COPY1]]487 ; CHECK-NEXT: $q0 = COPY [[MUL]](<16 x s8>)488 ; CHECK-NEXT: $q1 = COPY [[MUL1]](<16 x s8>)489 %0:_(<16 x s8>) = COPY $q0490 %1:_(<16 x s8>) = COPY $q1491 %2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1492 %3:_(<32 x s8>) = G_MUL %2, %2493 %7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)494 $q0 = COPY %7(<16 x s8>)495 $q1 = COPY %8(<16 x s8>)496 497...498---499name: mul_v2s1500tracksRegLiveness: true501body: |502 bb.1:503 liveins: $d0, $d1, $d2, $d3504 505 ; CHECK-LABEL: name: mul_v2s1506 ; CHECK: liveins: $d0, $d1, $d2, $d3507 ; CHECK-NEXT: {{ $}}508 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0509 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1510 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2511 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3512 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]513 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]514 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x s32>) = G_MUL [[ICMP]], [[ICMP1]]515 ; CHECK-NEXT: $d0 = COPY [[MUL]](<2 x s32>)516 ; CHECK-NEXT: RET_ReallyLR implicit $d0517 %0:_(<2 x s32>) = COPY $d0518 %1:_(<2 x s32>) = COPY $d1519 %2:_(<2 x s32>) = COPY $d2520 %3:_(<2 x s32>) = COPY $d3521 %4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1522 %5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3523 %6:_(<2 x s1>) = G_MUL %4, %5524 %7:_(<2 x s32>) = G_ANYEXT %6525 $d0 = COPY %7:_(<2 x s32>)526 RET_ReallyLR implicit $d0527...528---529name: mul_v3s1530tracksRegLiveness: true531body: |532 bb.1:533 liveins: $b0, $b1, $b2534 535 ; CHECK-LABEL: name: mul_v3s1536 ; CHECK: liveins: $b0, $b1, $b2537 ; CHECK-NEXT: {{ $}}538 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0539 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1540 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2541 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)542 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)543 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)544 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF545 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[DEF]](s16)546 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s16>) = G_MUL [[BUILD_VECTOR]], [[BUILD_VECTOR]]547 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[MUL]](<4 x s16>)548 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)549 ; CHECK-NEXT: $b0 = COPY [[TRUNC]](s8)550 ; CHECK-NEXT: RET_ReallyLR implicit $b0551 %1:_(s8) = COPY $b0552 %2:_(s8) = COPY $b1553 %3:_(s8) = COPY $b2554 %4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)555 %0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)556 %5:_(<3 x s1>) = G_MUL %0, %0557 %7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)558 %8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)559 $b0 = COPY %8:_(s8)560 RET_ReallyLR implicit $b0561...562---563name: mul_v4s1564tracksRegLiveness: true565body: |566 bb.1:567 liveins: $d0, $d1, $d2, $d3568 569 ; CHECK-LABEL: name: mul_v4s1570 ; CHECK: liveins: $d0, $d1, $d2, $d3571 ; CHECK-NEXT: {{ $}}572 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0573 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1574 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2575 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3576 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]577 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]578 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s16>) = G_MUL [[ICMP]], [[ICMP1]]579 ; CHECK-NEXT: $d0 = COPY [[MUL]](<4 x s16>)580 ; CHECK-NEXT: RET_ReallyLR implicit $d0581 %0:_(<4 x s16>) = COPY $d0582 %1:_(<4 x s16>) = COPY $d1583 %2:_(<4 x s16>) = COPY $d2584 %3:_(<4 x s16>) = COPY $d3585 %4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1586 %5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3587 %6:_(<4 x s1>) = G_MUL %4, %5588 %7:_(<4 x s16>) = G_ANYEXT %6589 $d0 = COPY %7:_(<4 x s16>)590 RET_ReallyLR implicit $d0591...592---593name: mul_v8s1594tracksRegLiveness: true595body: |596 bb.1:597 liveins: $d0, $d1, $d2, $d3598 599 ; CHECK-LABEL: name: mul_v8s1600 ; CHECK: liveins: $d0, $d1, $d2, $d3601 ; CHECK-NEXT: {{ $}}602 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0603 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1604 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2605 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3606 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]607 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]608 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<8 x s8>) = G_MUL [[ICMP]], [[ICMP1]]609 ; CHECK-NEXT: $d0 = COPY [[MUL]](<8 x s8>)610 ; CHECK-NEXT: RET_ReallyLR implicit $d0611 %0:_(<8 x s8>) = COPY $d0612 %1:_(<8 x s8>) = COPY $d1613 %2:_(<8 x s8>) = COPY $d2614 %3:_(<8 x s8>) = COPY $d3615 %4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1616 %5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3617 %6:_(<8 x s1>) = G_MUL %4, %5618 %7:_(<8 x s8>) = G_ANYEXT %6619 $d0 = COPY %7:_(<8 x s8>)620 RET_ReallyLR implicit $d0621...622---623name: mul_v16s1624tracksRegLiveness: true625body: |626 bb.1:627 liveins: $q0, $q1, $q2, $q3628 629 ; CHECK-LABEL: name: mul_v16s1630 ; CHECK: liveins: $q0, $q1, $q2, $q3631 ; CHECK-NEXT: {{ $}}632 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0633 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1634 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2635 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3636 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]637 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]638 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[ICMP]], [[ICMP1]]639 ; CHECK-NEXT: $q0 = COPY [[MUL]](<16 x s8>)640 ; CHECK-NEXT: RET_ReallyLR implicit $q0641 %0:_(<16 x s8>) = COPY $q0642 %1:_(<16 x s8>) = COPY $q1643 %2:_(<16 x s8>) = COPY $q2644 %3:_(<16 x s8>) = COPY $q3645 %4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1646 %5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3647 %6:_(<16 x s1>) = G_MUL %4, %5648 %7:_(<16 x s8>) = G_ANYEXT %6649 $q0 = COPY %7:_(<16 x s8>)650 RET_ReallyLR implicit $q0651...652