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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s3---4name: add_v16s85tracksRegLiveness: true6body: |7 bb.1:8 liveins: $x09 ; CHECK-LABEL: name: add_v16s810 ; CHECK: liveins: $x011 ; CHECK-NEXT: {{ $}}12 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x013 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>))14 ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>)15 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8)16 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)17 ; CHECK-NEXT: RET_ReallyLR implicit $w018 %0:_(p0) = COPY $x019 %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>))20 %2:_(s8) = G_VECREDUCE_ADD %1(<16 x s8>)21 %3:_(s32) = G_ANYEXT %2(s8)22 $w0 = COPY %3(s32)23 RET_ReallyLR implicit $w024 25...26---27name: add_v8s1628tracksRegLiveness: true29body: |30 bb.1:31 liveins: $x032 ; CHECK-LABEL: name: add_v8s1633 ; CHECK: liveins: $x034 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x036 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>))37 ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>)38 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16)39 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)40 ; CHECK-NEXT: RET_ReallyLR implicit $w041 %0:_(p0) = COPY $x042 %1:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>))43 %2:_(s16) = G_VECREDUCE_ADD %1(<8 x s16>)44 %3:_(s32) = G_ANYEXT %2(s16)45 $w0 = COPY %3(s32)46 RET_ReallyLR implicit $w047 48...49---50name: add_v4s3251tracksRegLiveness: true52body: |53 bb.1:54 liveins: $x055 ; CHECK-LABEL: name: add_v4s3256 ; CHECK: liveins: $x057 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x059 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>))60 ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>)61 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)62 ; CHECK-NEXT: RET_ReallyLR implicit $w063 %0:_(p0) = COPY $x064 %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>))65 %2:_(s32) = G_VECREDUCE_ADD %1(<4 x s32>)66 $w0 = COPY %2(s32)67 RET_ReallyLR implicit $w068 69...70---71name: add_v2s6472tracksRegLiveness: true73body: |74 bb.1:75 liveins: $x076 ; CHECK-LABEL: name: add_v2s6477 ; CHECK: liveins: $x078 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x080 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))81 ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>)82 ; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)83 ; CHECK-NEXT: RET_ReallyLR implicit $x084 %0:_(p0) = COPY $x085 %1:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>))86 %2:_(s64) = G_VECREDUCE_ADD %1(<2 x s64>)87 $x0 = COPY %2(s64)88 RET_ReallyLR implicit $x089 90...91---92name: add_v2s3293tracksRegLiveness: true94body: |95 bb.1:96 liveins: $x097 ; CHECK-LABEL: name: add_v2s3298 ; CHECK: liveins: $x099 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0101 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))102 ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<2 x s32>)103 ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)104 ; CHECK-NEXT: RET_ReallyLR implicit $w0105 %0:_(p0) = COPY $x0106 %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))107 %2:_(s32) = G_VECREDUCE_ADD %1(<2 x s32>)108 $w0 = COPY %2(s32)109 RET_ReallyLR implicit $w0110 111...112---113name: test_v8i64114# This is a power-of-2 legalization, so use a tree reduction.115alignment: 4116tracksRegLiveness: true117body: |118 bb.1:119 liveins: $q0, $q1, $q2, $q3120 ; CHECK-LABEL: name: test_v8i64121 ; CHECK: liveins: $q0, $q1, $q2, $q3122 ; CHECK-NEXT: {{ $}}123 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0124 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1125 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2126 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3127 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]128 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[COPY3]]129 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]130 ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[ADD2]](<2 x s64>)131 ; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)132 ; CHECK-NEXT: RET_ReallyLR implicit $x0133 %0:_(<2 x s64>) = COPY $q0134 %1:_(<2 x s64>) = COPY $q1135 %2:_(<2 x s64>) = COPY $q2136 %3:_(<2 x s64>) = COPY $q3137 %4:_(<4 x s64>) = G_CONCAT_VECTORS %0(<2 x s64>), %1(<2 x s64>)138 %5:_(<4 x s64>) = G_CONCAT_VECTORS %2(<2 x s64>), %3(<2 x s64>)139 %6:_(<8 x s64>) = G_CONCAT_VECTORS %4(<4 x s64>), %5(<4 x s64>)140 %7:_(s64) = G_VECREDUCE_ADD %6(<8 x s64>)141 $x0 = COPY %7(s64)142 RET_ReallyLR implicit $x0143 144...145---146name: test_v6i64147# This is a non-power-of-2 legalization, generate multiple vector reductions148# and combine them with scalar ops.149alignment: 4150tracksRegLiveness: true151body: |152 bb.1:153 liveins: $q0, $q1, $q2, $q3154 ; CHECK-LABEL: name: test_v6i64155 ; CHECK: liveins: $q0, $q1, $q2, $q3156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0158 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1159 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2160 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF161 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)162 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0163 ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s64), [[C]](s64)164 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1165 ; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[IVEC]], [[C]](s64), [[C1]](s64)166 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]167 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[IVEC1]]168 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]169 ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[ADD2]](<2 x s64>)170 ; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)171 ; CHECK-NEXT: RET_ReallyLR implicit $x0172 %0:_(<2 x s64>) = COPY $q0173 %1:_(<2 x s64>) = COPY $q1174 %2:_(<2 x s64>) = COPY $q2175 %3:_(<6 x s64>) = G_CONCAT_VECTORS %0(<2 x s64>), %1(<2 x s64>), %2(<2 x s64>)176 %4:_(s64) = G_VECREDUCE_ADD %3(<6 x s64>)177 $x0 = COPY %4(s64)178 RET_ReallyLR implicit $x0179 180...181