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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=legalizer -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s3---4name: rotr_s325alignment: 46tracksRegLiveness: true7body: |8 bb.0:9 liveins: $w0, $w110 ; CHECK-LABEL: name: rotr_s3211 ; CHECK: liveins: $w0, $w112 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w014 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w115 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)16 ; CHECK-NEXT: %rot:_(s32) = G_ROTR [[COPY]], [[ZEXT]](s64)17 ; CHECK-NEXT: $w0 = COPY %rot(s32)18 ; CHECK-NEXT: RET_ReallyLR implicit $w019 %0:_(s32) = COPY $w020 %1:_(s32) = COPY $w121 %rot:_(s32) = G_ROTR %0(s32), %1(s32)22 $w0 = COPY %rot(s32)23 RET_ReallyLR implicit $w024 25...26---27name: rotr_s6428alignment: 429tracksRegLiveness: true30body: |31 bb.0:32 liveins: $x0, $x133 ; CHECK-LABEL: name: rotr_s6434 ; CHECK: liveins: $x0, $x135 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x037 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x138 ; CHECK-NEXT: %rot:_(s64) = G_ROTR [[COPY]], [[COPY1]](s64)39 ; CHECK-NEXT: $x0 = COPY %rot(s64)40 ; CHECK-NEXT: RET_ReallyLR implicit $x041 %0:_(s64) = COPY $x042 %1:_(s64) = COPY $x143 %rot:_(s64) = G_ROTR %0(s64), %1(s64)44 $x0 = COPY %rot(s64)45 RET_ReallyLR implicit $x046 47...48---49name: rotl_s3250alignment: 451tracksRegLiveness: true52body: |53 bb.0:54 liveins: $w0, $w155 ; CHECK-LABEL: name: rotl_s3256 ; CHECK: liveins: $w0, $w157 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w059 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w160 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 061 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]62 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)63 ; CHECK-NEXT: %rot:_(s32) = G_ROTR [[COPY]], [[ZEXT]](s64)64 ; CHECK-NEXT: $w0 = COPY %rot(s32)65 ; CHECK-NEXT: RET_ReallyLR implicit $w066 %0:_(s32) = COPY $w067 %1:_(s32) = COPY $w168 %rot:_(s32) = G_ROTL %0(s32), %1(s32)69 $w0 = COPY %rot(s32)70 RET_ReallyLR implicit $w071 72...73---74name: rotl_s6475alignment: 476tracksRegLiveness: true77body: |78 bb.0:79 liveins: $x0, $x180 ; CHECK-LABEL: name: rotl_s6481 ; CHECK: liveins: $x0, $x182 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x084 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x185 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 086 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]87 ; CHECK-NEXT: %rot:_(s64) = G_ROTR [[COPY]], [[SUB]](s64)88 ; CHECK-NEXT: $x0 = COPY %rot(s64)89 ; CHECK-NEXT: RET_ReallyLR implicit $x090 %0:_(s64) = COPY $x091 %1:_(s64) = COPY $x192 %rot:_(s64) = G_ROTL %0(s64), %1(s64)93 $x0 = COPY %rot(s64)94 RET_ReallyLR implicit $x095 96...97---98name: test_rotl_v4s3299alignment: 4100tracksRegLiveness: true101body: |102 bb.0:103 liveins: $q0, $q1104 105 ; CHECK-LABEL: name: test_rotl_v4s32106 ; CHECK: liveins: $q0, $q1107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0109 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1110 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0111 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)112 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31113 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)114 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[BUILD_VECTOR]], [[COPY1]]115 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR1]]116 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[AND]](<4 x s32>)117 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[SUB]], [[BUILD_VECTOR1]]118 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[AND1]](<4 x s32>)119 ; CHECK-NEXT: %rot:_(<4 x s32>) = G_OR [[SHL]], [[LSHR]]120 ; CHECK-NEXT: $q0 = COPY %rot(<4 x s32>)121 ; CHECK-NEXT: RET_ReallyLR implicit $q0122 %0:_(<4 x s32>) = COPY $q0123 %1:_(<4 x s32>) = COPY $q1124 %rot:_(<4 x s32>) = G_ROTL %0(<4 x s32>), %1(<4 x s32>)125 $q0 = COPY %rot(<4 x s32>)126 RET_ReallyLR implicit $q0127 128...129---130name: test_rotr_v4s32131alignment: 4132tracksRegLiveness: true133body: |134 bb.0:135 liveins: $q0, $q1136 137 ; CHECK-LABEL: name: test_rotr_v4s32138 ; CHECK: liveins: $q0, $q1139 ; CHECK-NEXT: {{ $}}140 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0141 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1142 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0143 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)144 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31145 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)146 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[BUILD_VECTOR]], [[COPY1]]147 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR1]]148 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[AND]](<4 x s32>)149 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[SUB]], [[BUILD_VECTOR1]]150 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[AND1]](<4 x s32>)151 ; CHECK-NEXT: %rot:_(<4 x s32>) = G_OR [[LSHR]], [[SHL]]152 ; CHECK-NEXT: $q0 = COPY %rot(<4 x s32>)153 ; CHECK-NEXT: RET_ReallyLR implicit $q0154 %0:_(<4 x s32>) = COPY $q0155 %1:_(<4 x s32>) = COPY $q1156 %rot:_(<4 x s32>) = G_ROTR %0(<4 x s32>), %1(<4 x s32>)157 $q0 = COPY %rot(<4 x s32>)158 RET_ReallyLR implicit $q0159 160...161