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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64-apple-ios -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s3--- |4 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"5 target triple = "aarch64-apple-ios"6 7 define void @udiv_test(ptr %v1ptr, ptr %v2ptr) { ret void }8 9 define void @sdiv_test(ptr %v1ptr, ptr %v2ptr) { ret void }10 11...12---13name: udiv_test14alignment: 415tracksRegLiveness: true16liveins:17 - { reg: '$x0' }18 - { reg: '$x1' }19machineFunctionInfo: {}20body: |21 bb.1 (%ir-block.0):22 liveins: $x0, $x123 24 ; CHECK-LABEL: name: udiv_test25 ; CHECK: liveins: $x0, $x126 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x028 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x129 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.v1ptr)30 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.v2ptr)31 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp32 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)33 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)34 ; CHECK-NEXT: $x0 = COPY [[UV]](s64)35 ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)36 ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)37 ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)38 ; CHECK-NEXT: BL &__udivti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x139 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp40 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x041 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x142 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)43 ; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)44 ; CHECK-NEXT: RET_ReallyLR45 %0:_(p0) = COPY $x046 %1:_(p0) = COPY $x147 %2:_(s128) = G_LOAD %0(p0) :: (load (s128) from %ir.v1ptr)48 %3:_(s128) = G_LOAD %1(p0) :: (load (s128) from %ir.v2ptr)49 %4:_(s128) = G_UDIV %2, %350 G_STORE %4(s128), %0(p0) :: (store (s128) into %ir.v1ptr)51 RET_ReallyLR52 53...54---55name: sdiv_test56alignment: 457tracksRegLiveness: true58liveins:59 - { reg: '$x0' }60 - { reg: '$x1' }61machineFunctionInfo: {}62body: |63 bb.1 (%ir-block.0):64 liveins: $x0, $x165 66 ; CHECK-LABEL: name: sdiv_test67 ; CHECK: liveins: $x0, $x168 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x070 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x171 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.v1ptr)72 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.v2ptr)73 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp74 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)75 ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)76 ; CHECK-NEXT: $x0 = COPY [[UV]](s64)77 ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)78 ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)79 ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)80 ; CHECK-NEXT: BL &__divti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x181 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp82 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x083 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x184 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)85 ; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)86 ; CHECK-NEXT: RET_ReallyLR87 %0:_(p0) = COPY $x088 %1:_(p0) = COPY $x189 %2:_(s128) = G_LOAD %0(p0) :: (load (s128) from %ir.v1ptr)90 %3:_(s128) = G_LOAD %1(p0) :: (load (s128) from %ir.v2ptr)91 %4:_(s128) = G_SDIV %2, %392 G_STORE %4(s128), %0(p0) :: (store (s128) into %ir.v1ptr)93 RET_ReallyLR94 95...96