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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s3---4name: test_v2i64_eq5alignment: 46tracksRegLiveness: true7registers:8 - { id: 0, class: _ }9 - { id: 1, class: _ }10 - { id: 2, class: _ }11 - { id: 3, class: _ }12machineFunctionInfo: {}13body: |14 bb.1:15 liveins: $q0, $q116 17 ; CHECK-LABEL: name: test_v2i64_eq18 ; CHECK: liveins: $q0, $q119 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q021 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q122 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x s64>), [[COPY1]]23 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)24 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)25 ; CHECK-NEXT: RET_ReallyLR implicit $d026 %0:_(<2 x s64>) = COPY $q027 %1:_(<2 x s64>) = COPY $q128 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s64>), %129 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)30 $d0 = COPY %3(<2 x s32>)31 RET_ReallyLR implicit $d032 33...34---35name: test_v4i32_eq36alignment: 437tracksRegLiveness: true38registers:39 - { id: 0, class: _ }40 - { id: 1, class: _ }41 - { id: 2, class: _ }42 - { id: 3, class: _ }43machineFunctionInfo: {}44body: |45 bb.1:46 liveins: $q0, $q147 48 ; CHECK-LABEL: name: test_v4i32_eq49 ; CHECK: liveins: $q0, $q150 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q052 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q153 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY1]]54 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)55 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)56 ; CHECK-NEXT: RET_ReallyLR implicit $d057 %0:_(<4 x s32>) = COPY $q058 %1:_(<4 x s32>) = COPY $q159 %2:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s32>), %160 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)61 $d0 = COPY %3(<4 x s16>)62 RET_ReallyLR implicit $d063 64...65---66name: test_v2i32_eq67alignment: 468tracksRegLiveness: true69registers:70 - { id: 0, class: _ }71 - { id: 1, class: _ }72 - { id: 2, class: _ }73 - { id: 3, class: _ }74machineFunctionInfo: {}75body: |76 bb.1:77 liveins: $d0, $d178 79 ; CHECK-LABEL: name: test_v2i32_eq80 ; CHECK: liveins: $d0, $d181 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d083 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d184 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]85 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>)86 ; CHECK-NEXT: RET_ReallyLR implicit $d087 %0:_(<2 x s32>) = COPY $d088 %1:_(<2 x s32>) = COPY $d189 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %190 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)91 $d0 = COPY %3(<2 x s32>)92 RET_ReallyLR implicit $d093 94...95---96name: test_v8i16_eq97alignment: 498tracksRegLiveness: true99registers:100 - { id: 0, class: _ }101 - { id: 1, class: _ }102 - { id: 2, class: _ }103 - { id: 3, class: _ }104machineFunctionInfo: {}105body: |106 bb.1:107 liveins: $q0, $q1108 109 ; CHECK-LABEL: name: test_v8i16_eq110 ; CHECK: liveins: $q0, $q1111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0113 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1114 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[COPY]](<8 x s16>), [[COPY1]]115 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)116 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>)117 ; CHECK-NEXT: RET_ReallyLR implicit $d0118 %0:_(<8 x s16>) = COPY $q0119 %1:_(<8 x s16>) = COPY $q1120 %2:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s16>), %1121 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)122 $d0 = COPY %3(<8 x s8>)123 RET_ReallyLR implicit $d0124 125...126---127name: test_v4i16_eq128alignment: 4129tracksRegLiveness: true130registers:131 - { id: 0, class: _ }132 - { id: 1, class: _ }133 - { id: 2, class: _ }134 - { id: 3, class: _ }135machineFunctionInfo: {}136body: |137 bb.1:138 liveins: $d0, $d1139 140 ; CHECK-LABEL: name: test_v4i16_eq141 ; CHECK: liveins: $d0, $d1142 ; CHECK-NEXT: {{ $}}143 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0144 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1145 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]146 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>)147 ; CHECK-NEXT: RET_ReallyLR implicit $d0148 %0:_(<4 x s16>) = COPY $d0149 %1:_(<4 x s16>) = COPY $d1150 %2:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1151 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)152 $d0 = COPY %3(<4 x s16>)153 RET_ReallyLR implicit $d0154 155...156---157name: test_v16i8_eq158alignment: 4159tracksRegLiveness: true160registers:161 - { id: 0, class: _ }162 - { id: 1, class: _ }163 - { id: 2, class: _ }164 - { id: 3, class: _ }165machineFunctionInfo: {}166body: |167 bb.1:168 liveins: $q0, $q1169 170 ; CHECK-LABEL: name: test_v16i8_eq171 ; CHECK: liveins: $q0, $q1172 ; CHECK-NEXT: {{ $}}173 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0174 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1175 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]176 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>)177 ; CHECK-NEXT: RET_ReallyLR implicit $q0178 %0:_(<16 x s8>) = COPY $q0179 %1:_(<16 x s8>) = COPY $q1180 %2:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1181 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)182 $q0 = COPY %3(<16 x s8>)183 RET_ReallyLR implicit $q0184 185...186---187name: test_v8i8_eq188alignment: 4189tracksRegLiveness: true190registers:191 - { id: 0, class: _ }192 - { id: 1, class: _ }193 - { id: 2, class: _ }194 - { id: 3, class: _ }195machineFunctionInfo: {}196body: |197 bb.1:198 liveins: $d0, $d1199 200 ; CHECK-LABEL: name: test_v8i8_eq201 ; CHECK: liveins: $d0, $d1202 ; CHECK-NEXT: {{ $}}203 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0204 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1205 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]206 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>)207 ; CHECK-NEXT: RET_ReallyLR implicit $d0208 %0:_(<8 x s8>) = COPY $d0209 %1:_(<8 x s8>) = COPY $d1210 %2:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1211 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)212 $d0 = COPY %3(<8 x s8>)213 RET_ReallyLR implicit $d0214 215...216---217name: test_v2i64_ugt218alignment: 4219tracksRegLiveness: true220registers:221 - { id: 0, class: _ }222 - { id: 1, class: _ }223 - { id: 2, class: _ }224 - { id: 3, class: _ }225machineFunctionInfo: {}226body: |227 bb.1:228 liveins: $q0, $q1229 230 ; CHECK-LABEL: name: test_v2i64_ugt231 ; CHECK: liveins: $q0, $q1232 ; CHECK-NEXT: {{ $}}233 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0234 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1235 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[COPY]](<2 x s64>), [[COPY1]]236 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)237 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)238 ; CHECK-NEXT: RET_ReallyLR implicit $d0239 %0:_(<2 x s64>) = COPY $q0240 %1:_(<2 x s64>) = COPY $q1241 %2:_(<2 x s1>) = G_ICMP intpred(ugt), %0(<2 x s64>), %1242 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)243 $d0 = COPY %3(<2 x s32>)244 RET_ReallyLR implicit $d0245 246...247---248name: test_v4i32_ugt249alignment: 4250tracksRegLiveness: true251registers:252 - { id: 0, class: _ }253 - { id: 1, class: _ }254 - { id: 2, class: _ }255 - { id: 3, class: _ }256machineFunctionInfo: {}257body: |258 bb.1:259 liveins: $q0, $q1260 261 ; CHECK-LABEL: name: test_v4i32_ugt262 ; CHECK: liveins: $q0, $q1263 ; CHECK-NEXT: {{ $}}264 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0265 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1266 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ugt), [[COPY]](<4 x s32>), [[COPY1]]267 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)268 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)269 ; CHECK-NEXT: RET_ReallyLR implicit $d0270 %0:_(<4 x s32>) = COPY $q0271 %1:_(<4 x s32>) = COPY $q1272 %2:_(<4 x s1>) = G_ICMP intpred(ugt), %0(<4 x s32>), %1273 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)274 $d0 = COPY %3(<4 x s16>)275 RET_ReallyLR implicit $d0276 277...278---279name: test_v2i32_ugt280alignment: 4281tracksRegLiveness: true282registers:283 - { id: 0, class: _ }284 - { id: 1, class: _ }285 - { id: 2, class: _ }286 - { id: 3, class: _ }287machineFunctionInfo: {}288body: |289 bb.1:290 liveins: $d0, $d1291 292 ; CHECK-LABEL: name: test_v2i32_ugt293 ; CHECK: liveins: $d0, $d1294 ; CHECK-NEXT: {{ $}}295 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0296 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1297 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ugt), [[COPY]](<2 x s32>), [[COPY1]]298 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>)299 ; CHECK-NEXT: RET_ReallyLR implicit $d0300 %0:_(<2 x s32>) = COPY $d0301 %1:_(<2 x s32>) = COPY $d1302 %2:_(<2 x s1>) = G_ICMP intpred(ugt), %0(<2 x s32>), %1303 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)304 $d0 = COPY %3(<2 x s32>)305 RET_ReallyLR implicit $d0306 307...308---309name: test_v8i16_ugt310alignment: 4311tracksRegLiveness: true312registers:313 - { id: 0, class: _ }314 - { id: 1, class: _ }315 - { id: 2, class: _ }316 - { id: 3, class: _ }317machineFunctionInfo: {}318body: |319 bb.1:320 liveins: $q0, $q1321 322 ; CHECK-LABEL: name: test_v8i16_ugt323 ; CHECK: liveins: $q0, $q1324 ; CHECK-NEXT: {{ $}}325 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0326 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1327 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ugt), [[COPY]](<8 x s16>), [[COPY1]]328 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)329 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>)330 ; CHECK-NEXT: RET_ReallyLR implicit $d0331 %0:_(<8 x s16>) = COPY $q0332 %1:_(<8 x s16>) = COPY $q1333 %2:_(<8 x s1>) = G_ICMP intpred(ugt), %0(<8 x s16>), %1334 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)335 $d0 = COPY %3(<8 x s8>)336 RET_ReallyLR implicit $d0337 338...339---340name: test_v4i16_ugt341alignment: 4342tracksRegLiveness: true343registers:344 - { id: 0, class: _ }345 - { id: 1, class: _ }346 - { id: 2, class: _ }347 - { id: 3, class: _ }348machineFunctionInfo: {}349body: |350 bb.1:351 liveins: $d0, $d1352 353 ; CHECK-LABEL: name: test_v4i16_ugt354 ; CHECK: liveins: $d0, $d1355 ; CHECK-NEXT: {{ $}}356 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0357 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1358 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ugt), [[COPY]](<4 x s16>), [[COPY1]]359 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>)360 ; CHECK-NEXT: RET_ReallyLR implicit $d0361 %0:_(<4 x s16>) = COPY $d0362 %1:_(<4 x s16>) = COPY $d1363 %2:_(<4 x s1>) = G_ICMP intpred(ugt), %0(<4 x s16>), %1364 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)365 $d0 = COPY %3(<4 x s16>)366 RET_ReallyLR implicit $d0367 368...369---370name: test_v16i8_ugt371alignment: 4372tracksRegLiveness: true373registers:374 - { id: 0, class: _ }375 - { id: 1, class: _ }376 - { id: 2, class: _ }377 - { id: 3, class: _ }378machineFunctionInfo: {}379body: |380 bb.1:381 liveins: $q0, $q1382 383 ; CHECK-LABEL: name: test_v16i8_ugt384 ; CHECK: liveins: $q0, $q1385 ; CHECK-NEXT: {{ $}}386 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0387 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1388 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ugt), [[COPY]](<16 x s8>), [[COPY1]]389 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>)390 ; CHECK-NEXT: RET_ReallyLR implicit $q0391 %0:_(<16 x s8>) = COPY $q0392 %1:_(<16 x s8>) = COPY $q1393 %2:_(<16 x s1>) = G_ICMP intpred(ugt), %0(<16 x s8>), %1394 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)395 $q0 = COPY %3(<16 x s8>)396 RET_ReallyLR implicit $q0397 398...399---400name: test_v8i8_ugt401alignment: 4402tracksRegLiveness: true403registers:404 - { id: 0, class: _ }405 - { id: 1, class: _ }406 - { id: 2, class: _ }407 - { id: 3, class: _ }408machineFunctionInfo: {}409body: |410 bb.1:411 liveins: $d0, $d1412 413 ; CHECK-LABEL: name: test_v8i8_ugt414 ; CHECK: liveins: $d0, $d1415 ; CHECK-NEXT: {{ $}}416 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0417 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1418 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ugt), [[COPY]](<8 x s8>), [[COPY1]]419 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>)420 ; CHECK-NEXT: RET_ReallyLR implicit $d0421 %0:_(<8 x s8>) = COPY $d0422 %1:_(<8 x s8>) = COPY $d1423 %2:_(<8 x s1>) = G_ICMP intpred(ugt), %0(<8 x s8>), %1424 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)425 $d0 = COPY %3(<8 x s8>)426 RET_ReallyLR implicit $d0427 428...429---430name: test_v2i64_uge431alignment: 4432tracksRegLiveness: true433registers:434 - { id: 0, class: _ }435 - { id: 1, class: _ }436 - { id: 2, class: _ }437 - { id: 3, class: _ }438machineFunctionInfo: {}439body: |440 bb.1:441 liveins: $q0, $q1442 443 ; CHECK-LABEL: name: test_v2i64_uge444 ; CHECK: liveins: $q0, $q1445 ; CHECK-NEXT: {{ $}}446 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0447 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1448 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(uge), [[COPY]](<2 x s64>), [[COPY1]]449 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)450 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)451 ; CHECK-NEXT: RET_ReallyLR implicit $d0452 %0:_(<2 x s64>) = COPY $q0453 %1:_(<2 x s64>) = COPY $q1454 %2:_(<2 x s1>) = G_ICMP intpred(uge), %0(<2 x s64>), %1455 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)456 $d0 = COPY %3(<2 x s32>)457 RET_ReallyLR implicit $d0458 459...460---461name: test_v4i32_uge462alignment: 4463tracksRegLiveness: true464registers:465 - { id: 0, class: _ }466 - { id: 1, class: _ }467 - { id: 2, class: _ }468 - { id: 3, class: _ }469machineFunctionInfo: {}470body: |471 bb.1:472 liveins: $q0, $q1473 474 ; CHECK-LABEL: name: test_v4i32_uge475 ; CHECK: liveins: $q0, $q1476 ; CHECK-NEXT: {{ $}}477 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0478 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1479 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(uge), [[COPY]](<4 x s32>), [[COPY1]]480 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)481 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)482 ; CHECK-NEXT: RET_ReallyLR implicit $d0483 %0:_(<4 x s32>) = COPY $q0484 %1:_(<4 x s32>) = COPY $q1485 %2:_(<4 x s1>) = G_ICMP intpred(uge), %0(<4 x s32>), %1486 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)487 $d0 = COPY %3(<4 x s16>)488 RET_ReallyLR implicit $d0489 490...491---492name: test_v2i32_uge493alignment: 4494tracksRegLiveness: true495registers:496 - { id: 0, class: _ }497 - { id: 1, class: _ }498 - { id: 2, class: _ }499 - { id: 3, class: _ }500machineFunctionInfo: {}501body: |502 bb.1:503 liveins: $d0, $d1504 505 ; CHECK-LABEL: name: test_v2i32_uge506 ; CHECK: liveins: $d0, $d1507 ; CHECK-NEXT: {{ $}}508 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0509 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1510 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(uge), [[COPY]](<2 x s32>), [[COPY1]]511 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>)512 ; CHECK-NEXT: RET_ReallyLR implicit $d0513 %0:_(<2 x s32>) = COPY $d0514 %1:_(<2 x s32>) = COPY $d1515 %2:_(<2 x s1>) = G_ICMP intpred(uge), %0(<2 x s32>), %1516 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)517 $d0 = COPY %3(<2 x s32>)518 RET_ReallyLR implicit $d0519 520...521---522name: test_v8i16_uge523alignment: 4524tracksRegLiveness: true525registers:526 - { id: 0, class: _ }527 - { id: 1, class: _ }528 - { id: 2, class: _ }529 - { id: 3, class: _ }530machineFunctionInfo: {}531body: |532 bb.1:533 liveins: $q0, $q1534 535 ; CHECK-LABEL: name: test_v8i16_uge536 ; CHECK: liveins: $q0, $q1537 ; CHECK-NEXT: {{ $}}538 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0539 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1540 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(uge), [[COPY]](<8 x s16>), [[COPY1]]541 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)542 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>)543 ; CHECK-NEXT: RET_ReallyLR implicit $d0544 %0:_(<8 x s16>) = COPY $q0545 %1:_(<8 x s16>) = COPY $q1546 %2:_(<8 x s1>) = G_ICMP intpred(uge), %0(<8 x s16>), %1547 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)548 $d0 = COPY %3(<8 x s8>)549 RET_ReallyLR implicit $d0550 551...552---553name: test_v4i16_uge554alignment: 4555tracksRegLiveness: true556registers:557 - { id: 0, class: _ }558 - { id: 1, class: _ }559 - { id: 2, class: _ }560 - { id: 3, class: _ }561machineFunctionInfo: {}562body: |563 bb.1:564 liveins: $d0, $d1565 566 ; CHECK-LABEL: name: test_v4i16_uge567 ; CHECK: liveins: $d0, $d1568 ; CHECK-NEXT: {{ $}}569 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0570 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1571 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(uge), [[COPY]](<4 x s16>), [[COPY1]]572 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>)573 ; CHECK-NEXT: RET_ReallyLR implicit $d0574 %0:_(<4 x s16>) = COPY $d0575 %1:_(<4 x s16>) = COPY $d1576 %2:_(<4 x s1>) = G_ICMP intpred(uge), %0(<4 x s16>), %1577 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)578 $d0 = COPY %3(<4 x s16>)579 RET_ReallyLR implicit $d0580 581...582---583name: test_v16i8_uge584alignment: 4585tracksRegLiveness: true586registers:587 - { id: 0, class: _ }588 - { id: 1, class: _ }589 - { id: 2, class: _ }590 - { id: 3, class: _ }591machineFunctionInfo: {}592body: |593 bb.1:594 liveins: $q0, $q1595 596 ; CHECK-LABEL: name: test_v16i8_uge597 ; CHECK: liveins: $q0, $q1598 ; CHECK-NEXT: {{ $}}599 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0600 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1601 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(uge), [[COPY]](<16 x s8>), [[COPY1]]602 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>)603 ; CHECK-NEXT: RET_ReallyLR implicit $q0604 %0:_(<16 x s8>) = COPY $q0605 %1:_(<16 x s8>) = COPY $q1606 %2:_(<16 x s1>) = G_ICMP intpred(uge), %0(<16 x s8>), %1607 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)608 $q0 = COPY %3(<16 x s8>)609 RET_ReallyLR implicit $q0610 611...612---613name: test_v8i8_uge614alignment: 4615tracksRegLiveness: true616registers:617 - { id: 0, class: _ }618 - { id: 1, class: _ }619 - { id: 2, class: _ }620 - { id: 3, class: _ }621machineFunctionInfo: {}622body: |623 bb.1:624 liveins: $d0, $d1625 626 ; CHECK-LABEL: name: test_v8i8_uge627 ; CHECK: liveins: $d0, $d1628 ; CHECK-NEXT: {{ $}}629 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0630 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1631 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(uge), [[COPY]](<8 x s8>), [[COPY1]]632 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>)633 ; CHECK-NEXT: RET_ReallyLR implicit $d0634 %0:_(<8 x s8>) = COPY $d0635 %1:_(<8 x s8>) = COPY $d1636 %2:_(<8 x s1>) = G_ICMP intpred(uge), %0(<8 x s8>), %1637 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)638 $d0 = COPY %3(<8 x s8>)639 RET_ReallyLR implicit $d0640 641...642---643name: test_v2i64_ult644alignment: 4645tracksRegLiveness: true646registers:647 - { id: 0, class: _ }648 - { id: 1, class: _ }649 - { id: 2, class: _ }650 - { id: 3, class: _ }651machineFunctionInfo: {}652body: |653 bb.1:654 liveins: $q0, $q1655 656 ; CHECK-LABEL: name: test_v2i64_ult657 ; CHECK: liveins: $q0, $q1658 ; CHECK-NEXT: {{ $}}659 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0660 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1661 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[COPY]](<2 x s64>), [[COPY1]]662 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)663 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)664 ; CHECK-NEXT: RET_ReallyLR implicit $d0665 %0:_(<2 x s64>) = COPY $q0666 %1:_(<2 x s64>) = COPY $q1667 %2:_(<2 x s1>) = G_ICMP intpred(ult), %0(<2 x s64>), %1668 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)669 $d0 = COPY %3(<2 x s32>)670 RET_ReallyLR implicit $d0671 672...673---674name: test_v4i32_ult675alignment: 4676tracksRegLiveness: true677registers:678 - { id: 0, class: _ }679 - { id: 1, class: _ }680 - { id: 2, class: _ }681 - { id: 3, class: _ }682machineFunctionInfo: {}683body: |684 bb.1:685 liveins: $q0, $q1686 687 ; CHECK-LABEL: name: test_v4i32_ult688 ; CHECK: liveins: $q0, $q1689 ; CHECK-NEXT: {{ $}}690 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0691 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1692 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ult), [[COPY]](<4 x s32>), [[COPY1]]693 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)694 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)695 ; CHECK-NEXT: RET_ReallyLR implicit $d0696 %0:_(<4 x s32>) = COPY $q0697 %1:_(<4 x s32>) = COPY $q1698 %2:_(<4 x s1>) = G_ICMP intpred(ult), %0(<4 x s32>), %1699 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)700 $d0 = COPY %3(<4 x s16>)701 RET_ReallyLR implicit $d0702 703...704---705name: test_v2i32_ult706alignment: 4707tracksRegLiveness: true708registers:709 - { id: 0, class: _ }710 - { id: 1, class: _ }711 - { id: 2, class: _ }712 - { id: 3, class: _ }713machineFunctionInfo: {}714body: |715 bb.1:716 liveins: $d0, $d1717 718 ; CHECK-LABEL: name: test_v2i32_ult719 ; CHECK: liveins: $d0, $d1720 ; CHECK-NEXT: {{ $}}721 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0722 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1723 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]]724 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>)725 ; CHECK-NEXT: RET_ReallyLR implicit $d0726 %0:_(<2 x s32>) = COPY $d0727 %1:_(<2 x s32>) = COPY $d1728 %2:_(<2 x s1>) = G_ICMP intpred(ult), %0(<2 x s32>), %1729 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)730 $d0 = COPY %3(<2 x s32>)731 RET_ReallyLR implicit $d0732 733...734---735name: test_v8i16_ult736alignment: 4737tracksRegLiveness: true738registers:739 - { id: 0, class: _ }740 - { id: 1, class: _ }741 - { id: 2, class: _ }742 - { id: 3, class: _ }743machineFunctionInfo: {}744body: |745 bb.1:746 liveins: $q0, $q1747 748 ; CHECK-LABEL: name: test_v8i16_ult749 ; CHECK: liveins: $q0, $q1750 ; CHECK-NEXT: {{ $}}751 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0752 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1753 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ult), [[COPY]](<8 x s16>), [[COPY1]]754 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)755 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>)756 ; CHECK-NEXT: RET_ReallyLR implicit $d0757 %0:_(<8 x s16>) = COPY $q0758 %1:_(<8 x s16>) = COPY $q1759 %2:_(<8 x s1>) = G_ICMP intpred(ult), %0(<8 x s16>), %1760 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)761 $d0 = COPY %3(<8 x s8>)762 RET_ReallyLR implicit $d0763 764...765---766name: test_v4i16_ult767alignment: 4768tracksRegLiveness: true769registers:770 - { id: 0, class: _ }771 - { id: 1, class: _ }772 - { id: 2, class: _ }773 - { id: 3, class: _ }774machineFunctionInfo: {}775body: |776 bb.1:777 liveins: $d0, $d1778 779 ; CHECK-LABEL: name: test_v4i16_ult780 ; CHECK: liveins: $d0, $d1781 ; CHECK-NEXT: {{ $}}782 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0783 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1784 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ult), [[COPY]](<4 x s16>), [[COPY1]]785 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>)786 ; CHECK-NEXT: RET_ReallyLR implicit $d0787 %0:_(<4 x s16>) = COPY $d0788 %1:_(<4 x s16>) = COPY $d1789 %2:_(<4 x s1>) = G_ICMP intpred(ult), %0(<4 x s16>), %1790 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)791 $d0 = COPY %3(<4 x s16>)792 RET_ReallyLR implicit $d0793 794...795---796name: test_v16i8_ult797alignment: 4798tracksRegLiveness: true799registers:800 - { id: 0, class: _ }801 - { id: 1, class: _ }802 - { id: 2, class: _ }803 - { id: 3, class: _ }804machineFunctionInfo: {}805body: |806 bb.1:807 liveins: $q0, $q1808 809 ; CHECK-LABEL: name: test_v16i8_ult810 ; CHECK: liveins: $q0, $q1811 ; CHECK-NEXT: {{ $}}812 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0813 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1814 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ult), [[COPY]](<16 x s8>), [[COPY1]]815 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>)816 ; CHECK-NEXT: RET_ReallyLR implicit $q0817 %0:_(<16 x s8>) = COPY $q0818 %1:_(<16 x s8>) = COPY $q1819 %2:_(<16 x s1>) = G_ICMP intpred(ult), %0(<16 x s8>), %1820 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)821 $q0 = COPY %3(<16 x s8>)822 RET_ReallyLR implicit $q0823 824...825---826name: test_v8i8_ult827alignment: 4828tracksRegLiveness: true829registers:830 - { id: 0, class: _ }831 - { id: 1, class: _ }832 - { id: 2, class: _ }833 - { id: 3, class: _ }834machineFunctionInfo: {}835body: |836 bb.1:837 liveins: $d0, $d1838 839 ; CHECK-LABEL: name: test_v8i8_ult840 ; CHECK: liveins: $d0, $d1841 ; CHECK-NEXT: {{ $}}842 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0843 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1844 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ult), [[COPY]](<8 x s8>), [[COPY1]]845 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>)846 ; CHECK-NEXT: RET_ReallyLR implicit $d0847 %0:_(<8 x s8>) = COPY $d0848 %1:_(<8 x s8>) = COPY $d1849 %2:_(<8 x s1>) = G_ICMP intpred(ult), %0(<8 x s8>), %1850 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)851 $d0 = COPY %3(<8 x s8>)852 RET_ReallyLR implicit $d0853 854...855---856name: test_v2i64_ule857alignment: 4858tracksRegLiveness: true859registers:860 - { id: 0, class: _ }861 - { id: 1, class: _ }862 - { id: 2, class: _ }863 - { id: 3, class: _ }864machineFunctionInfo: {}865body: |866 bb.1:867 liveins: $q0, $q1868 869 ; CHECK-LABEL: name: test_v2i64_ule870 ; CHECK: liveins: $q0, $q1871 ; CHECK-NEXT: {{ $}}872 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0873 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1874 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ule), [[COPY]](<2 x s64>), [[COPY1]]875 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)876 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)877 ; CHECK-NEXT: RET_ReallyLR implicit $d0878 %0:_(<2 x s64>) = COPY $q0879 %1:_(<2 x s64>) = COPY $q1880 %2:_(<2 x s1>) = G_ICMP intpred(ule), %0(<2 x s64>), %1881 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)882 $d0 = COPY %3(<2 x s32>)883 RET_ReallyLR implicit $d0884 885...886---887name: test_v4i32_ule888alignment: 4889tracksRegLiveness: true890registers:891 - { id: 0, class: _ }892 - { id: 1, class: _ }893 - { id: 2, class: _ }894 - { id: 3, class: _ }895machineFunctionInfo: {}896body: |897 bb.1:898 liveins: $q0, $q1899 900 ; CHECK-LABEL: name: test_v4i32_ule901 ; CHECK: liveins: $q0, $q1902 ; CHECK-NEXT: {{ $}}903 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0904 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1905 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ule), [[COPY]](<4 x s32>), [[COPY1]]906 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)907 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)908 ; CHECK-NEXT: RET_ReallyLR implicit $d0909 %0:_(<4 x s32>) = COPY $q0910 %1:_(<4 x s32>) = COPY $q1911 %2:_(<4 x s1>) = G_ICMP intpred(ule), %0(<4 x s32>), %1912 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)913 $d0 = COPY %3(<4 x s16>)914 RET_ReallyLR implicit $d0915 916...917---918name: test_v2i32_ule919alignment: 4920tracksRegLiveness: true921registers:922 - { id: 0, class: _ }923 - { id: 1, class: _ }924 - { id: 2, class: _ }925 - { id: 3, class: _ }926machineFunctionInfo: {}927body: |928 bb.1:929 liveins: $d0, $d1930 931 ; CHECK-LABEL: name: test_v2i32_ule932 ; CHECK: liveins: $d0, $d1933 ; CHECK-NEXT: {{ $}}934 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0935 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1936 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ule), [[COPY]](<2 x s32>), [[COPY1]]937 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>)938 ; CHECK-NEXT: RET_ReallyLR implicit $d0939 %0:_(<2 x s32>) = COPY $d0940 %1:_(<2 x s32>) = COPY $d1941 %2:_(<2 x s1>) = G_ICMP intpred(ule), %0(<2 x s32>), %1942 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)943 $d0 = COPY %3(<2 x s32>)944 RET_ReallyLR implicit $d0945 946...947---948name: test_v8i16_ule949alignment: 4950tracksRegLiveness: true951registers:952 - { id: 0, class: _ }953 - { id: 1, class: _ }954 - { id: 2, class: _ }955 - { id: 3, class: _ }956machineFunctionInfo: {}957body: |958 bb.1:959 liveins: $q0, $q1960 961 ; CHECK-LABEL: name: test_v8i16_ule962 ; CHECK: liveins: $q0, $q1963 ; CHECK-NEXT: {{ $}}964 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0965 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1966 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ule), [[COPY]](<8 x s16>), [[COPY1]]967 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)968 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>)969 ; CHECK-NEXT: RET_ReallyLR implicit $d0970 %0:_(<8 x s16>) = COPY $q0971 %1:_(<8 x s16>) = COPY $q1972 %2:_(<8 x s1>) = G_ICMP intpred(ule), %0(<8 x s16>), %1973 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)974 $d0 = COPY %3(<8 x s8>)975 RET_ReallyLR implicit $d0976 977...978---979name: test_v4i16_ule980alignment: 4981tracksRegLiveness: true982registers:983 - { id: 0, class: _ }984 - { id: 1, class: _ }985 - { id: 2, class: _ }986 - { id: 3, class: _ }987machineFunctionInfo: {}988body: |989 bb.1:990 liveins: $d0, $d1991 992 ; CHECK-LABEL: name: test_v4i16_ule993 ; CHECK: liveins: $d0, $d1994 ; CHECK-NEXT: {{ $}}995 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0996 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1997 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ule), [[COPY]](<4 x s16>), [[COPY1]]998 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>)999 ; CHECK-NEXT: RET_ReallyLR implicit $d01000 %0:_(<4 x s16>) = COPY $d01001 %1:_(<4 x s16>) = COPY $d11002 %2:_(<4 x s1>) = G_ICMP intpred(ule), %0(<4 x s16>), %11003 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)1004 $d0 = COPY %3(<4 x s16>)1005 RET_ReallyLR implicit $d01006 1007...1008---1009name: test_v16i8_ule1010alignment: 41011tracksRegLiveness: true1012registers:1013 - { id: 0, class: _ }1014 - { id: 1, class: _ }1015 - { id: 2, class: _ }1016 - { id: 3, class: _ }1017machineFunctionInfo: {}1018body: |1019 bb.1:1020 liveins: $q0, $q11021 1022 ; CHECK-LABEL: name: test_v16i8_ule1023 ; CHECK: liveins: $q0, $q11024 ; CHECK-NEXT: {{ $}}1025 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q01026 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q11027 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ule), [[COPY]](<16 x s8>), [[COPY1]]1028 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>)1029 ; CHECK-NEXT: RET_ReallyLR implicit $q01030 %0:_(<16 x s8>) = COPY $q01031 %1:_(<16 x s8>) = COPY $q11032 %2:_(<16 x s1>) = G_ICMP intpred(ule), %0(<16 x s8>), %11033 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)1034 $q0 = COPY %3(<16 x s8>)1035 RET_ReallyLR implicit $q01036 1037...1038---1039name: test_v8i8_ule1040alignment: 41041tracksRegLiveness: true1042registers:1043 - { id: 0, class: _ }1044 - { id: 1, class: _ }1045 - { id: 2, class: _ }1046 - { id: 3, class: _ }1047machineFunctionInfo: {}1048body: |1049 bb.1:1050 liveins: $d0, $d11051 1052 ; CHECK-LABEL: name: test_v8i8_ule1053 ; CHECK: liveins: $d0, $d11054 ; CHECK-NEXT: {{ $}}1055 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d01056 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d11057 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ule), [[COPY]](<8 x s8>), [[COPY1]]1058 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>)1059 ; CHECK-NEXT: RET_ReallyLR implicit $d01060 %0:_(<8 x s8>) = COPY $d01061 %1:_(<8 x s8>) = COPY $d11062 %2:_(<8 x s1>) = G_ICMP intpred(ule), %0(<8 x s8>), %11063 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)1064 $d0 = COPY %3(<8 x s8>)1065 RET_ReallyLR implicit $d01066 1067...1068---1069name: test_v2i64_sgt1070alignment: 41071tracksRegLiveness: true1072registers:1073 - { id: 0, class: _ }1074 - { id: 1, class: _ }1075 - { id: 2, class: _ }1076 - { id: 3, class: _ }1077machineFunctionInfo: {}1078body: |1079 bb.1:1080 liveins: $q0, $q11081 1082 ; CHECK-LABEL: name: test_v2i64_sgt1083 ; CHECK: liveins: $q0, $q11084 ; CHECK-NEXT: {{ $}}1085 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q01086 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q11087 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[COPY1]]1088 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)1089 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)1090 ; CHECK-NEXT: RET_ReallyLR implicit $d01091 %0:_(<2 x s64>) = COPY $q01092 %1:_(<2 x s64>) = COPY $q11093 %2:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s64>), %11094 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)1095 $d0 = COPY %3(<2 x s32>)1096 RET_ReallyLR implicit $d01097 1098...1099---1100name: test_v4i32_sgt1101alignment: 41102tracksRegLiveness: true1103registers:1104 - { id: 0, class: _ }1105 - { id: 1, class: _ }1106 - { id: 2, class: _ }1107 - { id: 3, class: _ }1108machineFunctionInfo: {}1109body: |1110 bb.1:1111 liveins: $q0, $q11112 1113 ; CHECK-LABEL: name: test_v4i32_sgt1114 ; CHECK: liveins: $q0, $q11115 ; CHECK-NEXT: {{ $}}1116 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q01117 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q11118 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sgt), [[COPY]](<4 x s32>), [[COPY1]]1119 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)1120 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)1121 ; CHECK-NEXT: RET_ReallyLR implicit $d01122 %0:_(<4 x s32>) = COPY $q01123 %1:_(<4 x s32>) = COPY $q11124 %2:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s32>), %11125 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)1126 $d0 = COPY %3(<4 x s16>)1127 RET_ReallyLR implicit $d01128 1129...1130---1131name: test_v2i32_sgt1132alignment: 41133tracksRegLiveness: true1134registers:1135 - { id: 0, class: _ }1136 - { id: 1, class: _ }1137 - { id: 2, class: _ }1138 - { id: 3, class: _ }1139machineFunctionInfo: {}1140body: |1141 bb.1:1142 liveins: $d0, $d11143 1144 ; CHECK-LABEL: name: test_v2i32_sgt1145 ; CHECK: liveins: $d0, $d11146 ; CHECK-NEXT: {{ $}}1147 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d01148 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d11149 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[COPY1]]1150 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>)1151 ; CHECK-NEXT: RET_ReallyLR implicit $d01152 %0:_(<2 x s32>) = COPY $d01153 %1:_(<2 x s32>) = COPY $d11154 %2:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s32>), %11155 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)1156 $d0 = COPY %3(<2 x s32>)1157 RET_ReallyLR implicit $d01158 1159...1160---1161name: test_v8i16_sgt1162alignment: 41163tracksRegLiveness: true1164registers:1165 - { id: 0, class: _ }1166 - { id: 1, class: _ }1167 - { id: 2, class: _ }1168 - { id: 3, class: _ }1169machineFunctionInfo: {}1170body: |1171 bb.1:1172 liveins: $q0, $q11173 1174 ; CHECK-LABEL: name: test_v8i16_sgt1175 ; CHECK: liveins: $q0, $q11176 ; CHECK-NEXT: {{ $}}1177 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q01178 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q11179 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sgt), [[COPY]](<8 x s16>), [[COPY1]]1180 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)1181 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>)1182 ; CHECK-NEXT: RET_ReallyLR implicit $d01183 %0:_(<8 x s16>) = COPY $q01184 %1:_(<8 x s16>) = COPY $q11185 %2:_(<8 x s1>) = G_ICMP intpred(sgt), %0(<8 x s16>), %11186 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)1187 $d0 = COPY %3(<8 x s8>)1188 RET_ReallyLR implicit $d01189 1190...1191---1192name: test_v4i16_sgt1193alignment: 41194tracksRegLiveness: true1195registers:1196 - { id: 0, class: _ }1197 - { id: 1, class: _ }1198 - { id: 2, class: _ }1199 - { id: 3, class: _ }1200machineFunctionInfo: {}1201body: |1202 bb.1:1203 liveins: $d0, $d11204 1205 ; CHECK-LABEL: name: test_v4i16_sgt1206 ; CHECK: liveins: $d0, $d11207 ; CHECK-NEXT: {{ $}}1208 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d01209 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d11210 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sgt), [[COPY]](<4 x s16>), [[COPY1]]1211 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>)1212 ; CHECK-NEXT: RET_ReallyLR implicit $d01213 %0:_(<4 x s16>) = COPY $d01214 %1:_(<4 x s16>) = COPY $d11215 %2:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s16>), %11216 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)1217 $d0 = COPY %3(<4 x s16>)1218 RET_ReallyLR implicit $d01219 1220...1221---1222name: test_v16i8_sgt1223alignment: 41224tracksRegLiveness: true1225registers:1226 - { id: 0, class: _ }1227 - { id: 1, class: _ }1228 - { id: 2, class: _ }1229 - { id: 3, class: _ }1230machineFunctionInfo: {}1231body: |1232 bb.1:1233 liveins: $q0, $q11234 1235 ; CHECK-LABEL: name: test_v16i8_sgt1236 ; CHECK: liveins: $q0, $q11237 ; CHECK-NEXT: {{ $}}1238 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q01239 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q11240 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[COPY1]]1241 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>)1242 ; CHECK-NEXT: RET_ReallyLR implicit $q01243 %0:_(<16 x s8>) = COPY $q01244 %1:_(<16 x s8>) = COPY $q11245 %2:_(<16 x s1>) = G_ICMP intpred(sgt), %0(<16 x s8>), %11246 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)1247 $q0 = COPY %3(<16 x s8>)1248 RET_ReallyLR implicit $q01249 1250...1251---1252name: test_v8i8_sgt1253alignment: 41254tracksRegLiveness: true1255registers:1256 - { id: 0, class: _ }1257 - { id: 1, class: _ }1258 - { id: 2, class: _ }1259 - { id: 3, class: _ }1260machineFunctionInfo: {}1261body: |1262 bb.1:1263 liveins: $d0, $d11264 1265 ; CHECK-LABEL: name: test_v8i8_sgt1266 ; CHECK: liveins: $d0, $d11267 ; CHECK-NEXT: {{ $}}1268 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d01269 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d11270 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sgt), [[COPY]](<8 x s8>), [[COPY1]]1271 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>)1272 ; CHECK-NEXT: RET_ReallyLR implicit $d01273 %0:_(<8 x s8>) = COPY $d01274 %1:_(<8 x s8>) = COPY $d11275 %2:_(<8 x s1>) = G_ICMP intpred(sgt), %0(<8 x s8>), %11276 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)1277 $d0 = COPY %3(<8 x s8>)1278 RET_ReallyLR implicit $d01279 1280...1281---1282name: test_v2i64_sge1283alignment: 41284tracksRegLiveness: true1285registers:1286 - { id: 0, class: _ }1287 - { id: 1, class: _ }1288 - { id: 2, class: _ }1289 - { id: 3, class: _ }1290machineFunctionInfo: {}1291body: |1292 bb.1:1293 liveins: $q0, $q11294 1295 ; CHECK-LABEL: name: test_v2i64_sge1296 ; CHECK: liveins: $q0, $q11297 ; CHECK-NEXT: {{ $}}1298 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q01299 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q11300 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sge), [[COPY]](<2 x s64>), [[COPY1]]1301 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)1302 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)1303 ; CHECK-NEXT: RET_ReallyLR implicit $d01304 %0:_(<2 x s64>) = COPY $q01305 %1:_(<2 x s64>) = COPY $q11306 %2:_(<2 x s1>) = G_ICMP intpred(sge), %0(<2 x s64>), %11307 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)1308 $d0 = COPY %3(<2 x s32>)1309 RET_ReallyLR implicit $d01310 1311...1312---1313name: test_v4i32_sge1314alignment: 41315tracksRegLiveness: true1316registers:1317 - { id: 0, class: _ }1318 - { id: 1, class: _ }1319 - { id: 2, class: _ }1320 - { id: 3, class: _ }1321machineFunctionInfo: {}1322body: |1323 bb.1:1324 liveins: $q0, $q11325 1326 ; CHECK-LABEL: name: test_v4i32_sge1327 ; CHECK: liveins: $q0, $q11328 ; CHECK-NEXT: {{ $}}1329 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q01330 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q11331 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sge), [[COPY]](<4 x s32>), [[COPY1]]1332 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)1333 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)1334 ; CHECK-NEXT: RET_ReallyLR implicit $d01335 %0:_(<4 x s32>) = COPY $q01336 %1:_(<4 x s32>) = COPY $q11337 %2:_(<4 x s1>) = G_ICMP intpred(sge), %0(<4 x s32>), %11338 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)1339 $d0 = COPY %3(<4 x s16>)1340 RET_ReallyLR implicit $d01341 1342...1343---1344name: test_v2i32_sge1345alignment: 41346tracksRegLiveness: true1347registers:1348 - { id: 0, class: _ }1349 - { id: 1, class: _ }1350 - { id: 2, class: _ }1351 - { id: 3, class: _ }1352machineFunctionInfo: {}1353body: |1354 bb.1:1355 liveins: $d0, $d11356 1357 ; CHECK-LABEL: name: test_v2i32_sge1358 ; CHECK: liveins: $d0, $d11359 ; CHECK-NEXT: {{ $}}1360 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d01361 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d11362 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sge), [[COPY]](<2 x s32>), [[COPY1]]1363 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>)1364 ; CHECK-NEXT: RET_ReallyLR implicit $d01365 %0:_(<2 x s32>) = COPY $d01366 %1:_(<2 x s32>) = COPY $d11367 %2:_(<2 x s1>) = G_ICMP intpred(sge), %0(<2 x s32>), %11368 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)1369 $d0 = COPY %3(<2 x s32>)1370 RET_ReallyLR implicit $d01371 1372...1373---1374name: test_v8i16_sge1375alignment: 41376tracksRegLiveness: true1377registers:1378 - { id: 0, class: _ }1379 - { id: 1, class: _ }1380 - { id: 2, class: _ }1381 - { id: 3, class: _ }1382machineFunctionInfo: {}1383body: |1384 bb.1:1385 liveins: $q0, $q11386 1387 ; CHECK-LABEL: name: test_v8i16_sge1388 ; CHECK: liveins: $q0, $q11389 ; CHECK-NEXT: {{ $}}1390 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q01391 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q11392 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sge), [[COPY]](<8 x s16>), [[COPY1]]1393 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)1394 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>)1395 ; CHECK-NEXT: RET_ReallyLR implicit $d01396 %0:_(<8 x s16>) = COPY $q01397 %1:_(<8 x s16>) = COPY $q11398 %2:_(<8 x s1>) = G_ICMP intpred(sge), %0(<8 x s16>), %11399 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)1400 $d0 = COPY %3(<8 x s8>)1401 RET_ReallyLR implicit $d01402 1403...1404---1405name: test_v4i16_sge1406alignment: 41407tracksRegLiveness: true1408registers:1409 - { id: 0, class: _ }1410 - { id: 1, class: _ }1411 - { id: 2, class: _ }1412 - { id: 3, class: _ }1413machineFunctionInfo: {}1414body: |1415 bb.1:1416 liveins: $d0, $d11417 1418 ; CHECK-LABEL: name: test_v4i16_sge1419 ; CHECK: liveins: $d0, $d11420 ; CHECK-NEXT: {{ $}}1421 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d01422 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d11423 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sge), [[COPY]](<4 x s16>), [[COPY1]]1424 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>)1425 ; CHECK-NEXT: RET_ReallyLR implicit $d01426 %0:_(<4 x s16>) = COPY $d01427 %1:_(<4 x s16>) = COPY $d11428 %2:_(<4 x s1>) = G_ICMP intpred(sge), %0(<4 x s16>), %11429 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)1430 $d0 = COPY %3(<4 x s16>)1431 RET_ReallyLR implicit $d01432 1433...1434---1435name: test_v16i8_sge1436alignment: 41437tracksRegLiveness: true1438registers:1439 - { id: 0, class: _ }1440 - { id: 1, class: _ }1441 - { id: 2, class: _ }1442 - { id: 3, class: _ }1443machineFunctionInfo: {}1444body: |1445 bb.1:1446 liveins: $q0, $q11447 1448 ; CHECK-LABEL: name: test_v16i8_sge1449 ; CHECK: liveins: $q0, $q11450 ; CHECK-NEXT: {{ $}}1451 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q01452 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q11453 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sge), [[COPY]](<16 x s8>), [[COPY1]]1454 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>)1455 ; CHECK-NEXT: RET_ReallyLR implicit $q01456 %0:_(<16 x s8>) = COPY $q01457 %1:_(<16 x s8>) = COPY $q11458 %2:_(<16 x s1>) = G_ICMP intpred(sge), %0(<16 x s8>), %11459 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)1460 $q0 = COPY %3(<16 x s8>)1461 RET_ReallyLR implicit $q01462 1463...1464---1465name: test_v8i8_sge1466alignment: 41467tracksRegLiveness: true1468registers:1469 - { id: 0, class: _ }1470 - { id: 1, class: _ }1471 - { id: 2, class: _ }1472 - { id: 3, class: _ }1473machineFunctionInfo: {}1474body: |1475 bb.1:1476 liveins: $d0, $d11477 1478 ; CHECK-LABEL: name: test_v8i8_sge1479 ; CHECK: liveins: $d0, $d11480 ; CHECK-NEXT: {{ $}}1481 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d01482 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d11483 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sge), [[COPY]](<8 x s8>), [[COPY1]]1484 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>)1485 ; CHECK-NEXT: RET_ReallyLR implicit $d01486 %0:_(<8 x s8>) = COPY $d01487 %1:_(<8 x s8>) = COPY $d11488 %2:_(<8 x s1>) = G_ICMP intpred(sge), %0(<8 x s8>), %11489 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)1490 $d0 = COPY %3(<8 x s8>)1491 RET_ReallyLR implicit $d01492 1493...1494---1495name: test_v2i64_slt1496alignment: 41497tracksRegLiveness: true1498registers:1499 - { id: 0, class: _ }1500 - { id: 1, class: _ }1501 - { id: 2, class: _ }1502 - { id: 3, class: _ }1503machineFunctionInfo: {}1504body: |1505 bb.1:1506 liveins: $q0, $q11507 1508 ; CHECK-LABEL: name: test_v2i64_slt1509 ; CHECK: liveins: $q0, $q11510 ; CHECK-NEXT: {{ $}}1511 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q01512 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q11513 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[COPY]](<2 x s64>), [[COPY1]]1514 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)1515 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)1516 ; CHECK-NEXT: RET_ReallyLR implicit $d01517 %0:_(<2 x s64>) = COPY $q01518 %1:_(<2 x s64>) = COPY $q11519 %2:_(<2 x s1>) = G_ICMP intpred(slt), %0(<2 x s64>), %11520 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)1521 $d0 = COPY %3(<2 x s32>)1522 RET_ReallyLR implicit $d01523 1524...1525---1526name: test_v4i32_slt1527alignment: 41528tracksRegLiveness: true1529registers:1530 - { id: 0, class: _ }1531 - { id: 1, class: _ }1532 - { id: 2, class: _ }1533 - { id: 3, class: _ }1534machineFunctionInfo: {}1535body: |1536 bb.1:1537 liveins: $q0, $q11538 1539 ; CHECK-LABEL: name: test_v4i32_slt1540 ; CHECK: liveins: $q0, $q11541 ; CHECK-NEXT: {{ $}}1542 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q01543 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q11544 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(slt), [[COPY]](<4 x s32>), [[COPY1]]1545 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)1546 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)1547 ; CHECK-NEXT: RET_ReallyLR implicit $d01548 %0:_(<4 x s32>) = COPY $q01549 %1:_(<4 x s32>) = COPY $q11550 %2:_(<4 x s1>) = G_ICMP intpred(slt), %0(<4 x s32>), %11551 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)1552 $d0 = COPY %3(<4 x s16>)1553 RET_ReallyLR implicit $d01554 1555...1556---1557name: test_v2i32_slt1558alignment: 41559tracksRegLiveness: true1560registers:1561 - { id: 0, class: _ }1562 - { id: 1, class: _ }1563 - { id: 2, class: _ }1564 - { id: 3, class: _ }1565machineFunctionInfo: {}1566body: |1567 bb.1:1568 liveins: $d0, $d11569 1570 ; CHECK-LABEL: name: test_v2i32_slt1571 ; CHECK: liveins: $d0, $d11572 ; CHECK-NEXT: {{ $}}1573 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d01574 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d11575 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(slt), [[COPY]](<2 x s32>), [[COPY1]]1576 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>)1577 ; CHECK-NEXT: RET_ReallyLR implicit $d01578 %0:_(<2 x s32>) = COPY $d01579 %1:_(<2 x s32>) = COPY $d11580 %2:_(<2 x s1>) = G_ICMP intpred(slt), %0(<2 x s32>), %11581 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)1582 $d0 = COPY %3(<2 x s32>)1583 RET_ReallyLR implicit $d01584 1585...1586---1587name: test_v8i16_slt1588alignment: 41589tracksRegLiveness: true1590registers:1591 - { id: 0, class: _ }1592 - { id: 1, class: _ }1593 - { id: 2, class: _ }1594 - { id: 3, class: _ }1595machineFunctionInfo: {}1596body: |1597 bb.1:1598 liveins: $q0, $q11599 1600 ; CHECK-LABEL: name: test_v8i16_slt1601 ; CHECK: liveins: $q0, $q11602 ; CHECK-NEXT: {{ $}}1603 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q01604 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q11605 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(slt), [[COPY]](<8 x s16>), [[COPY1]]1606 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)1607 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>)1608 ; CHECK-NEXT: RET_ReallyLR implicit $d01609 %0:_(<8 x s16>) = COPY $q01610 %1:_(<8 x s16>) = COPY $q11611 %2:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s16>), %11612 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)1613 $d0 = COPY %3(<8 x s8>)1614 RET_ReallyLR implicit $d01615 1616...1617---1618name: test_v4i16_slt1619alignment: 41620tracksRegLiveness: true1621registers:1622 - { id: 0, class: _ }1623 - { id: 1, class: _ }1624 - { id: 2, class: _ }1625 - { id: 3, class: _ }1626machineFunctionInfo: {}1627body: |1628 bb.1:1629 liveins: $d0, $d11630 1631 ; CHECK-LABEL: name: test_v4i16_slt1632 ; CHECK: liveins: $d0, $d11633 ; CHECK-NEXT: {{ $}}1634 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d01635 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d11636 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(slt), [[COPY]](<4 x s16>), [[COPY1]]1637 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>)1638 ; CHECK-NEXT: RET_ReallyLR implicit $d01639 %0:_(<4 x s16>) = COPY $d01640 %1:_(<4 x s16>) = COPY $d11641 %2:_(<4 x s1>) = G_ICMP intpred(slt), %0(<4 x s16>), %11642 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)1643 $d0 = COPY %3(<4 x s16>)1644 RET_ReallyLR implicit $d01645 1646...1647---1648name: test_v16i8_slt1649alignment: 41650tracksRegLiveness: true1651registers:1652 - { id: 0, class: _ }1653 - { id: 1, class: _ }1654 - { id: 2, class: _ }1655 - { id: 3, class: _ }1656machineFunctionInfo: {}1657body: |1658 bb.1:1659 liveins: $q0, $q11660 1661 ; CHECK-LABEL: name: test_v16i8_slt1662 ; CHECK: liveins: $q0, $q11663 ; CHECK-NEXT: {{ $}}1664 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q01665 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q11666 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(slt), [[COPY]](<16 x s8>), [[COPY1]]1667 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>)1668 ; CHECK-NEXT: RET_ReallyLR implicit $q01669 %0:_(<16 x s8>) = COPY $q01670 %1:_(<16 x s8>) = COPY $q11671 %2:_(<16 x s1>) = G_ICMP intpred(slt), %0(<16 x s8>), %11672 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)1673 $q0 = COPY %3(<16 x s8>)1674 RET_ReallyLR implicit $q01675 1676...1677---1678name: test_v8i8_slt1679alignment: 41680tracksRegLiveness: true1681registers:1682 - { id: 0, class: _ }1683 - { id: 1, class: _ }1684 - { id: 2, class: _ }1685 - { id: 3, class: _ }1686machineFunctionInfo: {}1687body: |1688 bb.1:1689 liveins: $d0, $d11690 1691 ; CHECK-LABEL: name: test_v8i8_slt1692 ; CHECK: liveins: $d0, $d11693 ; CHECK-NEXT: {{ $}}1694 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d01695 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d11696 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(slt), [[COPY]](<8 x s8>), [[COPY1]]1697 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>)1698 ; CHECK-NEXT: RET_ReallyLR implicit $d01699 %0:_(<8 x s8>) = COPY $d01700 %1:_(<8 x s8>) = COPY $d11701 %2:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s8>), %11702 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)1703 $d0 = COPY %3(<8 x s8>)1704 RET_ReallyLR implicit $d01705 1706...1707---1708name: test_v2i64_sle1709alignment: 41710tracksRegLiveness: true1711registers:1712 - { id: 0, class: _ }1713 - { id: 1, class: _ }1714 - { id: 2, class: _ }1715 - { id: 3, class: _ }1716machineFunctionInfo: {}1717body: |1718 bb.1:1719 liveins: $q0, $q11720 1721 ; CHECK-LABEL: name: test_v2i64_sle1722 ; CHECK: liveins: $q0, $q11723 ; CHECK-NEXT: {{ $}}1724 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q01725 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q11726 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sle), [[COPY]](<2 x s64>), [[COPY1]]1727 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)1728 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)1729 ; CHECK-NEXT: RET_ReallyLR implicit $d01730 %0:_(<2 x s64>) = COPY $q01731 %1:_(<2 x s64>) = COPY $q11732 %2:_(<2 x s1>) = G_ICMP intpred(sle), %0(<2 x s64>), %11733 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)1734 $d0 = COPY %3(<2 x s32>)1735 RET_ReallyLR implicit $d01736 1737...1738---1739name: test_v4i32_sle1740alignment: 41741tracksRegLiveness: true1742registers:1743 - { id: 0, class: _ }1744 - { id: 1, class: _ }1745 - { id: 2, class: _ }1746 - { id: 3, class: _ }1747machineFunctionInfo: {}1748body: |1749 bb.1:1750 liveins: $q0, $q11751 1752 ; CHECK-LABEL: name: test_v4i32_sle1753 ; CHECK: liveins: $q0, $q11754 ; CHECK-NEXT: {{ $}}1755 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q01756 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q11757 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sle), [[COPY]](<4 x s32>), [[COPY1]]1758 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)1759 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)1760 ; CHECK-NEXT: RET_ReallyLR implicit $d01761 %0:_(<4 x s32>) = COPY $q01762 %1:_(<4 x s32>) = COPY $q11763 %2:_(<4 x s1>) = G_ICMP intpred(sle), %0(<4 x s32>), %11764 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)1765 $d0 = COPY %3(<4 x s16>)1766 RET_ReallyLR implicit $d01767 1768...1769---1770name: test_v2i32_sle1771alignment: 41772tracksRegLiveness: true1773registers:1774 - { id: 0, class: _ }1775 - { id: 1, class: _ }1776 - { id: 2, class: _ }1777 - { id: 3, class: _ }1778machineFunctionInfo: {}1779body: |1780 bb.1:1781 liveins: $d0, $d11782 1783 ; CHECK-LABEL: name: test_v2i32_sle1784 ; CHECK: liveins: $d0, $d11785 ; CHECK-NEXT: {{ $}}1786 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d01787 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d11788 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sle), [[COPY]](<2 x s32>), [[COPY1]]1789 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>)1790 ; CHECK-NEXT: RET_ReallyLR implicit $d01791 %0:_(<2 x s32>) = COPY $d01792 %1:_(<2 x s32>) = COPY $d11793 %2:_(<2 x s1>) = G_ICMP intpred(sle), %0(<2 x s32>), %11794 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)1795 $d0 = COPY %3(<2 x s32>)1796 RET_ReallyLR implicit $d01797 1798...1799---1800name: test_v8i16_sle1801alignment: 41802tracksRegLiveness: true1803registers:1804 - { id: 0, class: _ }1805 - { id: 1, class: _ }1806 - { id: 2, class: _ }1807 - { id: 3, class: _ }1808machineFunctionInfo: {}1809body: |1810 bb.1:1811 liveins: $q0, $q11812 1813 ; CHECK-LABEL: name: test_v8i16_sle1814 ; CHECK: liveins: $q0, $q11815 ; CHECK-NEXT: {{ $}}1816 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q01817 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q11818 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sle), [[COPY]](<8 x s16>), [[COPY1]]1819 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)1820 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>)1821 ; CHECK-NEXT: RET_ReallyLR implicit $d01822 %0:_(<8 x s16>) = COPY $q01823 %1:_(<8 x s16>) = COPY $q11824 %2:_(<8 x s1>) = G_ICMP intpred(sle), %0(<8 x s16>), %11825 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)1826 $d0 = COPY %3(<8 x s8>)1827 RET_ReallyLR implicit $d01828 1829...1830---1831name: test_v4i16_sle1832alignment: 41833tracksRegLiveness: true1834registers:1835 - { id: 0, class: _ }1836 - { id: 1, class: _ }1837 - { id: 2, class: _ }1838 - { id: 3, class: _ }1839machineFunctionInfo: {}1840body: |1841 bb.1:1842 liveins: $d0, $d11843 1844 ; CHECK-LABEL: name: test_v4i16_sle1845 ; CHECK: liveins: $d0, $d11846 ; CHECK-NEXT: {{ $}}1847 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d01848 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d11849 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sle), [[COPY]](<4 x s16>), [[COPY1]]1850 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>)1851 ; CHECK-NEXT: RET_ReallyLR implicit $d01852 %0:_(<4 x s16>) = COPY $d01853 %1:_(<4 x s16>) = COPY $d11854 %2:_(<4 x s1>) = G_ICMP intpred(sle), %0(<4 x s16>), %11855 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)1856 $d0 = COPY %3(<4 x s16>)1857 RET_ReallyLR implicit $d01858 1859...1860---1861name: test_v16i8_sle1862alignment: 41863tracksRegLiveness: true1864registers:1865 - { id: 0, class: _ }1866 - { id: 1, class: _ }1867 - { id: 2, class: _ }1868 - { id: 3, class: _ }1869machineFunctionInfo: {}1870body: |1871 bb.1:1872 liveins: $q0, $q11873 1874 ; CHECK-LABEL: name: test_v16i8_sle1875 ; CHECK: liveins: $q0, $q11876 ; CHECK-NEXT: {{ $}}1877 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q01878 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q11879 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sle), [[COPY]](<16 x s8>), [[COPY1]]1880 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>)1881 ; CHECK-NEXT: RET_ReallyLR implicit $q01882 %0:_(<16 x s8>) = COPY $q01883 %1:_(<16 x s8>) = COPY $q11884 %2:_(<16 x s1>) = G_ICMP intpred(sle), %0(<16 x s8>), %11885 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)1886 $q0 = COPY %3(<16 x s8>)1887 RET_ReallyLR implicit $q01888 1889...1890---1891name: test_v8i8_sle1892alignment: 41893tracksRegLiveness: true1894registers:1895 - { id: 0, class: _ }1896 - { id: 1, class: _ }1897 - { id: 2, class: _ }1898 - { id: 3, class: _ }1899machineFunctionInfo: {}1900body: |1901 bb.1:1902 liveins: $d0, $d11903 1904 ; CHECK-LABEL: name: test_v8i8_sle1905 ; CHECK: liveins: $d0, $d11906 ; CHECK-NEXT: {{ $}}1907 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d01908 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d11909 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sle), [[COPY]](<8 x s8>), [[COPY1]]1910 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>)1911 ; CHECK-NEXT: RET_ReallyLR implicit $d01912 %0:_(<8 x s8>) = COPY $d01913 %1:_(<8 x s8>) = COPY $d11914 %2:_(<8 x s1>) = G_ICMP intpred(sle), %0(<8 x s8>), %11915 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)1916 $d0 = COPY %3(<8 x s8>)1917 RET_ReallyLR implicit $d01918 1919...1920---1921name: test_v2p0_eq1922alignment: 41923tracksRegLiveness: true1924registers:1925 - { id: 0, class: _ }1926 - { id: 1, class: _ }1927 - { id: 2, class: _ }1928 - { id: 3, class: _ }1929machineFunctionInfo: {}1930body: |1931 bb.1:1932 liveins: $q0, $q11933 1934 ; CHECK-LABEL: name: test_v2p0_eq1935 ; CHECK: liveins: $q0, $q11936 ; CHECK-NEXT: {{ $}}1937 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q01938 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $q11939 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x p0>), [[COPY1]]1940 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)1941 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>)1942 ; CHECK-NEXT: RET_ReallyLR implicit $d01943 %0:_(<2 x p0>) = COPY $q01944 %1:_(<2 x p0>) = COPY $q11945 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x p0>), %11946 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)1947 $d0 = COPY %3(<2 x s32>)1948 RET_ReallyLR implicit $d01949 1950...1951---1952name: icmp_8xs11953alignment: 41954tracksRegLiveness: true1955liveins:1956 - { reg: '$q0' }1957 - { reg: '$q1' }1958 - { reg: '$q2' }1959 - { reg: '$q3' }1960body: |1961 bb.1:1962 liveins: $q0, $q1, $q2, $q31963 1964 ; CHECK-LABEL: name: icmp_8xs11965 ; CHECK: liveins: $q0, $q1, $q2, $q31966 ; CHECK-NEXT: {{ $}}1967 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q01968 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q11969 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q21970 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q31971 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY2]]1972 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY1]](<4 x s32>), [[COPY3]]1973 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)1974 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)1975 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)1976 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)1977 ; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<8 x s8>)1978 ; CHECK-NEXT: RET_ReallyLR implicit $d01979 %2:_(<4 x s32>) = COPY $q01980 %3:_(<4 x s32>) = COPY $q11981 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)1982 %4:_(<4 x s32>) = COPY $q21983 %5:_(<4 x s32>) = COPY $q31984 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)1985 %6:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s32>), %11986 %7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>)1987 $d0 = COPY %7(<8 x s8>)1988 RET_ReallyLR implicit $d01989...1990---1991name: icmp_8xs321992alignment: 41993tracksRegLiveness: true1994liveins:1995 - { reg: '$q0' }1996 - { reg: '$q1' }1997 - { reg: '$q2' }1998 - { reg: '$q3' }1999body: |2000 bb.1:2001 liveins: $q0, $q1, $q2, $q32002 2003 ; CHECK-LABEL: name: icmp_8xs322004 ; CHECK: liveins: $q0, $q1, $q2, $q32005 ; CHECK-NEXT: {{ $}}2006 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q02007 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q12008 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q22009 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q32010 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY2]]2011 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY1]](<4 x s32>), [[COPY3]]2012 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)2013 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)2014 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)2015 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)2016 ; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<8 x s8>)2017 ; CHECK-NEXT: RET_ReallyLR implicit $d02018 %2:_(<4 x s32>) = COPY $q02019 %3:_(<4 x s32>) = COPY $q12020 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)2021 %4:_(<4 x s32>) = COPY $q22022 %5:_(<4 x s32>) = COPY $q32023 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)2024 %6:_(<8 x s32>) = G_ICMP intpred(eq), %0(<8 x s32>), %12025 %7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>)2026 $d0 = COPY %7(<8 x s8>)2027 RET_ReallyLR implicit $d02028...2029---2030name: fcmp_8xs12031alignment: 42032tracksRegLiveness: true2033liveins:2034 - { reg: '$q0' }2035 - { reg: '$q1' }2036 - { reg: '$q2' }2037 - { reg: '$q3' }2038body: |2039 bb.1:2040 liveins: $q0, $q1, $q2, $q32041 2042 ; CHECK-LABEL: name: fcmp_8xs12043 ; CHECK: liveins: $q0, $q1, $q2, $q32044 ; CHECK-NEXT: {{ $}}2045 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q02046 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q12047 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q22048 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q32049 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY]](<4 x s32>), [[COPY2]]2050 ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY1]](<4 x s32>), [[COPY3]]2051 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)2052 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>)2053 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)2054 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)2055 ; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<8 x s8>)2056 ; CHECK-NEXT: RET_ReallyLR implicit $d02057 %2:_(<4 x s32>) = COPY $q02058 %3:_(<4 x s32>) = COPY $q12059 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)2060 %4:_(<4 x s32>) = COPY $q22061 %5:_(<4 x s32>) = COPY $q32062 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)2063 %6:_(<8 x s1>) = G_FCMP floatpred(one), %0(<8 x s32>), %12064 %7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>)2065 $d0 = COPY %7(<8 x s8>)2066 RET_ReallyLR implicit $d02067...2068---2069name: fcmp_8xs322070alignment: 42071tracksRegLiveness: true2072liveins:2073 - { reg: '$q0' }2074 - { reg: '$q1' }2075 - { reg: '$q2' }2076 - { reg: '$q3' }2077body: |2078 bb.1:2079 liveins: $q0, $q1, $q2, $q32080 2081 ; CHECK-LABEL: name: fcmp_8xs322082 ; CHECK: liveins: $q0, $q1, $q2, $q32083 ; CHECK-NEXT: {{ $}}2084 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q02085 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q12086 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q22087 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q32088 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY]](<4 x s32>), [[COPY2]]2089 ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY1]](<4 x s32>), [[COPY3]]2090 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)2091 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>)2092 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)2093 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)2094 ; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<8 x s8>)2095 ; CHECK-NEXT: RET_ReallyLR implicit $d02096 %2:_(<4 x s32>) = COPY $q02097 %3:_(<4 x s32>) = COPY $q12098 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)2099 %4:_(<4 x s32>) = COPY $q22100 %5:_(<4 x s32>) = COPY $q32101 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)2102 %6:_(<8 x s32>) = G_FCMP floatpred(oeq), %0(<8 x s32>), %12103 %7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>)2104 $d0 = COPY %7(<8 x s8>)2105 RET_ReallyLR implicit $d02106...2107---2108name: fcmp_v4s322109alignment: 42110tracksRegLiveness: true2111registers:2112 - { id: 0, class: _ }2113 - { id: 1, class: _ }2114 - { id: 2, class: _ }2115 - { id: 3, class: _ }2116machineFunctionInfo: {}2117body: |2118 bb.1:2119 liveins: $q0, $q12120 2121 ; CHECK-LABEL: name: fcmp_v4s322122 ; CHECK: liveins: $q0, $q12123 ; CHECK-NEXT: {{ $}}2124 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q02125 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q12126 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(olt), [[COPY]](<4 x s32>), [[COPY1]]2127 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)2128 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>)2129 ; CHECK-NEXT: RET_ReallyLR implicit $d02130 %0:_(<4 x s32>) = COPY $q02131 %1:_(<4 x s32>) = COPY $q12132 %2:_(<4 x s1>) = G_FCMP floatpred(olt), %0(<4 x s32>), %12133 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)2134 $d0 = COPY %3(<4 x s16>)2135 RET_ReallyLR implicit $d02136 2137...2138