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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FAST --allow-unused-prefixes3# RUN: llc -mtriple=aarch64-unknown-unknown -mattr=+addr-lsl-slow-14 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SLOW --allow-unused-prefixes4 5--- |6 define void @ldrxrox_breg_oreg(ptr %addr) { ret void }7 define void @ldrdrox_breg_oreg(ptr %addr) { ret void }8 define void @more_than_one_use(ptr %addr) { ret void }9 define void @ldrhrox_shl(ptr %addr) { ret void }10 define void @ldrwrox_shl(ptr %addr) { ret void }11 define void @ldrxrox_shl(ptr %addr) { ret void }12 define void @ldrdrox_shl(ptr %addr) { ret void }13 define void @ldrqrox_shl(ptr %addr) { ret void }14 define void @ldrxrox_mul_rhs(ptr %addr) { ret void }15 define void @ldrdrox_mul_rhs(ptr %addr) { ret void }16 define void @ldrxrox_mul_lhs(ptr %addr) { ret void }17 define void @ldrdrox_mul_lhs(ptr %addr) { ret void }18 define void @mul_not_pow_2(ptr %addr) { ret void }19 define void @mul_wrong_pow_2(ptr %addr) { ret void }20 define void @more_than_one_use_shl_fallback(ptr %addr) { ret void }21 define void @ldrxrox_more_than_one_mem_use_shl(ptr %addr) { ret void }22 define void @ldrxrox_more_than_one_use_shl(ptr %addr) { ret void }23 define void @ldrhrox_more_than_one_mem_use_shl(ptr %addr) { ret void }24 define void @ldrhrox_more_than_one_use_shl(ptr %addr) { ret void }25 define void @ldrwrox_more_than_one_use_shl(ptr %addr) { ret void }26 define void @ldrqrox_more_than_one_use_shl(ptr %addr) { ret void }27 define void @more_than_one_use_shl_lsl(ptr %addr) { ret void }28 define void @more_than_one_use_shl_minsize(ptr %addr) #0 { ret void }29 define void @ldrwrox(ptr %addr) { ret void }30 define void @ldrsrox(ptr %addr) { ret void }31 define void @ldrhrox(ptr %addr) { ret void }32 define void @ldbbrox(ptr %addr) { ret void }33 define void @ldrqrox(ptr %addr) { ret void }34 attributes #0 = { optsize }35...36 37---38name: ldrxrox_breg_oreg39alignment: 440legalized: true41regBankSelected: true42tracksRegLiveness: true43machineFunctionInfo: {}44body: |45 bb.0:46 liveins: $x0, $x147 48 ; CHECK-LABEL: name: ldrxrox_breg_oreg49 ; CHECK: liveins: $x0, $x150 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x052 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x153 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY]], [[COPY1]], 0, 0 :: (load (s64) from %ir.addr)54 ; CHECK-NEXT: $x0 = COPY [[LDRXroX]]55 ; CHECK-NEXT: RET_ReallyLR implicit $x056 %0:gpr(p0) = COPY $x057 %1:gpr(s64) = COPY $x158 %2:gpr(p0) = G_PTR_ADD %0, %159 %4:gpr(s64) = G_LOAD %2(p0) :: (load (s64) from %ir.addr)60 $x0 = COPY %4(s64)61 RET_ReallyLR implicit $x062...63 64---65name: ldrdrox_breg_oreg66alignment: 467legalized: true68regBankSelected: true69tracksRegLiveness: true70machineFunctionInfo: {}71body: |72 bb.0:73 liveins: $d0, $x174 ; CHECK-LABEL: name: ldrdrox_breg_oreg75 ; CHECK: liveins: $d0, $x176 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $d078 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x179 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY]], [[COPY1]], 0, 0 :: (load (s64) from %ir.addr)80 ; CHECK-NEXT: $d0 = COPY [[LDRDroX]]81 ; CHECK-NEXT: RET_ReallyLR implicit $d082 %0:gpr(p0) = COPY $d083 %1:gpr(s64) = COPY $x184 %2:gpr(p0) = G_PTR_ADD %0, %185 %4:fpr(s64) = G_LOAD %2(p0) :: (load (s64) from %ir.addr)86 $d0 = COPY %4(s64)87 RET_ReallyLR implicit $d088...89---90# This shouldn't be folded, since we reuse the result of the G_PTR_ADD outside91# the G_LOAD92 93name: more_than_one_use94alignment: 495legalized: true96regBankSelected: true97tracksRegLiveness: true98machineFunctionInfo: {}99body: |100 bb.0:101 liveins: $x0, $x1102 ; CHECK-LABEL: name: more_than_one_use103 ; CHECK: liveins: $x0, $x1104 ; CHECK-NEXT: {{ $}}105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0106 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1107 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr [[COPY]], [[COPY1]]108 ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADDXrr]], 0 :: (load (s64) from %ir.addr)109 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[ADDXrr]]110 ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[LDRXui]]111 ; CHECK-NEXT: $x0 = COPY [[ADDXrr1]]112 ; CHECK-NEXT: RET_ReallyLR implicit $x0113 %0:gpr(p0) = COPY $x0114 %1:gpr(s64) = COPY $x1115 %2:gpr(p0) = G_PTR_ADD %0, %1116 %4:gpr(s64) = G_LOAD %2(p0) :: (load (s64) from %ir.addr)117 %5:gpr(s64) = G_PTRTOINT %2118 %6:gpr(s64) = G_ADD %5, %4119 $x0 = COPY %6(s64)120 RET_ReallyLR implicit $x0121 122...123---124name: ldrhrox_shl125alignment: 4126legalized: true127regBankSelected: true128tracksRegLiveness: true129machineFunctionInfo: {}130body: |131 bb.0:132 liveins: $x0, $x1, $x2133 liveins: $w1, $x0134 135 ; CHECK-LABEL: name: ldrhrox_shl136 ; CHECK: liveins: $x0, $x1, $x2, $w1, $x0137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0139 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1140 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31141 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0142 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32143 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103144 ; CHECK-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16))145 ; CHECK-NEXT: RET_ReallyLR implicit [[LDRHHroX]]146 %0:gpr(p0) = COPY $x0147 %1:gpr(s32) = COPY $w1148 %15:gpr(s64) = G_CONSTANT i64 9149 %3:gpr(s32) = G_LSHR %1, %15(s64)150 %4:gpr(s64) = G_ZEXT %3(s32)151 %5:gpr(s64) = G_CONSTANT i64 255152 %6:gpr(s64) = G_AND %4, %5153 %13:gpr(s64) = G_CONSTANT i64 1154 %8:gpr(s64) = G_SHL %6, %13(s64)155 %9:gpr(p0) = G_PTR_ADD %0, %8(s64)156 %12:gpr(s32) = G_LOAD %9(p0) :: (load (s16))157 RET_ReallyLR implicit %12158...159---160name: ldrwrox_shl161alignment: 4162legalized: true163regBankSelected: true164tracksRegLiveness: true165machineFunctionInfo: {}166body: |167 bb.0:168 liveins: $x0, $x1, $x2169 ; CHECK-LABEL: name: ldrwrox_shl170 ; CHECK: liveins: $x0, $x1, $x2171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0173 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1174 ; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[COPY1]], [[COPY]], 0, 1 :: (load (s32) from %ir.addr)175 ; CHECK-NEXT: RET_ReallyLR implicit [[LDRWroX]]176 %0:gpr(s64) = COPY $x0177 %1:gpr(s64) = G_CONSTANT i64 2178 %2:gpr(s64) = G_SHL %0, %1(s64)179 %3:gpr(p0) = COPY $x1180 %4:gpr(p0) = G_PTR_ADD %3, %2181 %5:gpr(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.addr)182 RET_ReallyLR implicit %5183...184---185name: ldrxrox_shl186alignment: 4187legalized: true188regBankSelected: true189tracksRegLiveness: true190machineFunctionInfo: {}191body: |192 bb.0:193 liveins: $x0, $x1, $x2194 ; CHECK-LABEL: name: ldrxrox_shl195 ; CHECK: liveins: $x0, $x1, $x2196 ; CHECK-NEXT: {{ $}}197 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0198 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1199 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)200 ; CHECK-NEXT: $x2 = COPY [[LDRXroX]]201 ; CHECK-NEXT: RET_ReallyLR implicit $x2202 %0:gpr(s64) = COPY $x0203 %1:gpr(s64) = G_CONSTANT i64 3204 %2:gpr(s64) = G_SHL %0, %1(s64)205 %3:gpr(p0) = COPY $x1206 %4:gpr(p0) = G_PTR_ADD %3, %2207 %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)208 $x2 = COPY %5(s64)209 RET_ReallyLR implicit $x2210 211...212---213name: ldrdrox_shl214alignment: 4215legalized: true216regBankSelected: true217tracksRegLiveness: true218machineFunctionInfo: {}219body: |220 bb.0:221 liveins: $x0, $x1, $d2222 ; CHECK-LABEL: name: ldrdrox_shl223 ; CHECK: liveins: $x0, $x1, $d2224 ; CHECK-NEXT: {{ $}}225 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0226 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1227 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)228 ; CHECK-NEXT: $d2 = COPY [[LDRDroX]]229 ; CHECK-NEXT: RET_ReallyLR implicit $d2230 %0:gpr(s64) = COPY $x0231 %1:gpr(s64) = G_CONSTANT i64 3232 %2:gpr(s64) = G_SHL %0, %1(s64)233 %3:gpr(p0) = COPY $x1234 %4:gpr(p0) = G_PTR_ADD %3, %2235 %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)236 $d2 = COPY %5(s64)237 RET_ReallyLR implicit $d2238 239...240---241name: ldrqrox_shl242alignment: 4243legalized: true244regBankSelected: true245tracksRegLiveness: true246machineFunctionInfo: {}247body: |248 bb.0:249 liveins: $x0, $x1, $d2250 ; CHECK-LABEL: name: ldrqrox_shl251 ; CHECK: liveins: $x0, $x1, $d2252 ; CHECK-NEXT: {{ $}}253 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0254 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1255 ; CHECK-NEXT: [[LDRQroX:%[0-9]+]]:fpr128 = LDRQroX [[COPY1]], [[COPY]], 0, 1 :: (load (s128) from %ir.addr)256 ; CHECK-NEXT: RET_ReallyLR implicit [[LDRQroX]]257 %0:gpr(s64) = COPY $x0258 %1:gpr(s64) = G_CONSTANT i64 4259 %2:gpr(s64) = G_SHL %0, %1(s64)260 %3:gpr(p0) = COPY $x1261 %4:gpr(p0) = G_PTR_ADD %3, %2262 %5:fpr(s128) = G_LOAD %4(p0) :: (load (s128) from %ir.addr)263 RET_ReallyLR implicit %5264 265...266---267name: ldrxrox_mul_rhs268alignment: 4269legalized: true270regBankSelected: true271tracksRegLiveness: true272machineFunctionInfo: {}273body: |274 bb.0:275 liveins: $x0, $x1, $x2276 ; CHECK-LABEL: name: ldrxrox_mul_rhs277 ; CHECK: liveins: $x0, $x1, $x2278 ; CHECK-NEXT: {{ $}}279 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0280 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1281 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)282 ; CHECK-NEXT: $x2 = COPY [[LDRXroX]]283 ; CHECK-NEXT: RET_ReallyLR implicit $x2284 %0:gpr(s64) = COPY $x0285 %1:gpr(s64) = G_CONSTANT i64 8286 %2:gpr(s64) = G_MUL %0, %1(s64)287 %3:gpr(p0) = COPY $x1288 %4:gpr(p0) = G_PTR_ADD %3, %2289 %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)290 $x2 = COPY %5(s64)291 RET_ReallyLR implicit $x2292 293...294---295name: ldrdrox_mul_rhs296alignment: 4297legalized: true298regBankSelected: true299tracksRegLiveness: true300machineFunctionInfo: {}301body: |302 bb.0:303 liveins: $x0, $x1, $d2304 ; CHECK-LABEL: name: ldrdrox_mul_rhs305 ; CHECK: liveins: $x0, $x1, $d2306 ; CHECK-NEXT: {{ $}}307 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0308 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1309 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)310 ; CHECK-NEXT: $d2 = COPY [[LDRDroX]]311 ; CHECK-NEXT: RET_ReallyLR implicit $d2312 %0:gpr(s64) = COPY $x0313 %1:gpr(s64) = G_CONSTANT i64 8314 %2:gpr(s64) = G_MUL %0, %1(s64)315 %3:gpr(p0) = COPY $x1316 %4:gpr(p0) = G_PTR_ADD %3, %2317 %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)318 $d2 = COPY %5(s64)319 RET_ReallyLR implicit $d2320 321...322---323name: ldrxrox_mul_lhs324alignment: 4325legalized: true326regBankSelected: true327tracksRegLiveness: true328machineFunctionInfo: {}329body: |330 bb.0:331 liveins: $x0, $x1, $x2332 ; CHECK-LABEL: name: ldrxrox_mul_lhs333 ; CHECK: liveins: $x0, $x1, $x2334 ; CHECK-NEXT: {{ $}}335 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0336 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1337 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)338 ; CHECK-NEXT: $x2 = COPY [[LDRXroX]]339 ; CHECK-NEXT: RET_ReallyLR implicit $x2340 %0:gpr(s64) = COPY $x0341 %1:gpr(s64) = G_CONSTANT i64 8342 %2:gpr(s64) = G_MUL %1, %0(s64)343 %3:gpr(p0) = COPY $x1344 %4:gpr(p0) = G_PTR_ADD %3, %2345 %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)346 $x2 = COPY %5(s64)347 RET_ReallyLR implicit $x2348 349...350---351name: ldrdrox_mul_lhs352alignment: 4353legalized: true354regBankSelected: true355tracksRegLiveness: true356machineFunctionInfo: {}357body: |358 bb.0:359 liveins: $x0, $x1, $d2360 ; CHECK-LABEL: name: ldrdrox_mul_lhs361 ; CHECK: liveins: $x0, $x1, $d2362 ; CHECK-NEXT: {{ $}}363 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0364 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1365 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)366 ; CHECK-NEXT: $d2 = COPY [[LDRDroX]]367 ; CHECK-NEXT: RET_ReallyLR implicit $d2368 %0:gpr(s64) = COPY $x0369 %1:gpr(s64) = G_CONSTANT i64 8370 %2:gpr(s64) = G_MUL %1, %0(s64)371 %3:gpr(p0) = COPY $x1372 %4:gpr(p0) = G_PTR_ADD %3, %2373 %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)374 $d2 = COPY %5(s64)375 RET_ReallyLR implicit $d2376 377...378---379# Show that we don't get a shifted load from a mul when we don't have a380# power of 2. (The bit isn't set on the load.)381 382name: mul_not_pow_2383alignment: 4384legalized: true385regBankSelected: true386tracksRegLiveness: true387machineFunctionInfo: {}388body: |389 bb.0:390 liveins: $x0, $x1, $d2391 ; CHECK-LABEL: name: mul_not_pow_2392 ; CHECK: liveins: $x0, $x1, $d2393 ; CHECK-NEXT: {{ $}}394 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0395 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7396 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32397 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr398 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1399 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load (s64) from %ir.addr)400 ; CHECK-NEXT: $d2 = COPY [[LDRDroX]]401 ; CHECK-NEXT: RET_ReallyLR implicit $d2402 %0:gpr(s64) = COPY $x0403 %1:gpr(s64) = G_CONSTANT i64 7404 %2:gpr(s64) = G_MUL %1, %0(s64)405 %3:gpr(p0) = COPY $x1406 %4:gpr(p0) = G_PTR_ADD %3, %2407 %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)408 $d2 = COPY %5(s64)409 RET_ReallyLR implicit $d2410 411...412---413# Show that we don't get a shifted load from a mul when we don't have414# the right power of 2. (The bit isn't set on the load.)415 416name: mul_wrong_pow_2417alignment: 4418legalized: true419regBankSelected: true420tracksRegLiveness: true421machineFunctionInfo: {}422body: |423 bb.0:424 liveins: $x0, $x1, $d2425 ; CHECK-LABEL: name: mul_wrong_pow_2426 ; CHECK: liveins: $x0, $x1, $d2427 ; CHECK-NEXT: {{ $}}428 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0429 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16430 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32431 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr432 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1433 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load (s64) from %ir.addr)434 ; CHECK-NEXT: $d2 = COPY [[LDRDroX]]435 ; CHECK-NEXT: RET_ReallyLR implicit $d2436 %0:gpr(s64) = COPY $x0437 %1:gpr(s64) = G_CONSTANT i64 16438 %2:gpr(s64) = G_MUL %1, %0(s64)439 %3:gpr(p0) = COPY $x1440 %4:gpr(p0) = G_PTR_ADD %3, %2441 %5:fpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)442 $d2 = COPY %5(s64)443 RET_ReallyLR implicit $d2444 445...446---447# Show that we can still fall back to the register-register addressing448# mode when we fail to pull in the shift.449 450name: more_than_one_use_shl_fallback451alignment: 4452legalized: true453regBankSelected: true454tracksRegLiveness: true455machineFunctionInfo: {}456body: |457 bb.0:458 liveins: $x0, $x1, $x2459 ; CHECK-LABEL: name: more_than_one_use_shl_fallback460 ; CHECK: liveins: $x0, $x1, $x2461 ; CHECK-NEXT: {{ $}}462 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0463 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 62, 61464 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1465 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[UBFMXri]], 0, 0 :: (load (s64) from %ir.addr)466 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 2, 0467 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[ADDXri]]468 ; CHECK-NEXT: $x2 = COPY [[ADDXrr]]469 ; CHECK-NEXT: RET_ReallyLR implicit $x2470 %0:gpr(s64) = COPY $x0471 %1:gpr(s64) = G_CONSTANT i64 2472 %2:gpr(s64) = G_SHL %0, %1(s64)473 %3:gpr(p0) = COPY $x1474 %4:gpr(p0) = G_PTR_ADD %3, %2475 %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)476 %6:gpr(s64) = G_ADD %2, %1477 %7:gpr(s64) = G_ADD %5, %6478 $x2 = COPY %7(s64)479 RET_ReallyLR implicit $x2480 481...482---483name: ldrxrox_more_than_one_mem_use_shl484alignment: 4485legalized: true486regBankSelected: true487tracksRegLiveness: true488machineFunctionInfo: {}489body: |490 bb.0:491 liveins: $x0, $x1, $x2492 ; CHECK-LABEL: name: ldrxrox_more_than_one_mem_use_shl493 ; CHECK: liveins: $x0, $x1, $x2494 ; CHECK-NEXT: {{ $}}495 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0496 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1497 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31498 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0499 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32500 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103501 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s64))502 ; CHECK-NEXT: [[LDRXroX1:%[0-9]+]]:gpr64 = LDRXroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s64))503 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[LDRXroX1]]504 ; CHECK-NEXT: RET_ReallyLR implicit [[ADDXrr]]505 %0:gpr(p0) = COPY $x0506 %1:gpr(s32) = COPY $w1507 %15:gpr(s64) = G_CONSTANT i64 9508 %3:gpr(s32) = G_LSHR %1, %15(s64)509 %4:gpr(s64) = G_ZEXT %3(s32)510 %5:gpr(s64) = G_CONSTANT i64 255511 %6:gpr(s64) = G_AND %4, %5512 %13:gpr(s64) = G_CONSTANT i64 3513 %8:gpr(s64) = G_SHL %6, %13(s64)514 %9:gpr(p0) = G_PTR_ADD %0, %8(s64)515 %12:gpr(s64) = G_LOAD %9(p0) :: (load (s64))516 %17:gpr(s64) = G_LOAD %9(p0) :: (load (s64))517 %18:gpr(s64) = G_ADD %12, %17518 RET_ReallyLR implicit %18519 520...521---522# Show that when the GEP is used both inside and outside a memory op, we only fold the memory op.523 524name: ldrxrox_more_than_one_use_shl525alignment: 4526legalized: true527regBankSelected: true528tracksRegLiveness: true529machineFunctionInfo: {}530body: |531 bb.0:532 liveins: $x0, $x1, $x2533 ; CHECK-LABEL: name: ldrxrox_more_than_one_use_shl534 ; CHECK: liveins: $x0, $x1, $x2535 ; CHECK-NEXT: {{ $}}536 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0537 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 61, 60538 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1539 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]540 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[UBFMXri]]541 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)542 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 3, 0543 ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[ADDXri]]544 ; CHECK-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[ADDXrr1]]545 ; CHECK-NEXT: $x2 = COPY [[ADDXrr2]]546 ; CHECK-NEXT: RET_ReallyLR implicit $x2547 %0:gpr(s64) = COPY $x0548 %1:gpr(s64) = G_CONSTANT i64 3549 %2:gpr(s64) = G_SHL %0, %1(s64)550 %3:gpr(p0) = COPY $x1551 %4:gpr(p0) = G_PTR_ADD %3, %2552 %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)553 %6:gpr(s64) = G_ADD %2, %1554 %7:gpr(s64) = G_ADD %5, %6555 %8:gpr(s64) = G_PTRTOINT %4556 %9:gpr(s64) = G_ADD %8, %7557 $x2 = COPY %9(s64)558 RET_ReallyLR implicit $x2559 560...561---562# Fold SHL into LSL for mem ops. Do not fold if the target has LSLSLOW14.563name: ldrhrox_more_than_one_mem_use_shl564alignment: 4565legalized: true566regBankSelected: true567tracksRegLiveness: true568machineFunctionInfo: {}569body: |570 bb.0:571 liveins: $x0, $x1, $x2572 liveins: $w1, $x0573 574 ; CHECK-FAST-LABEL: name: ldrhrox_more_than_one_mem_use_shl575 ; CHECK-FAST: liveins: $x0, $x1, $x2, $w1, $x0576 ; CHECK-FAST-NEXT: {{ $}}577 ; CHECK-FAST-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0578 ; CHECK-FAST-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1579 ; CHECK-FAST-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31580 ; CHECK-FAST-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0581 ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32582 ; CHECK-FAST-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103583 ; CHECK-FAST-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16))584 ; CHECK-FAST-NEXT: [[LDRHHroX1:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16))585 ; CHECK-FAST-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRHHroX]], [[LDRHHroX1]]586 ; CHECK-FAST-NEXT: RET_ReallyLR implicit [[ADDWrr]]587 ;588 ; CHECK-SLOW-LABEL: name: ldrhrox_more_than_one_mem_use_shl589 ; CHECK-SLOW: liveins: $x0, $x1, $x2, $w1, $x0590 ; CHECK-SLOW-NEXT: {{ $}}591 ; CHECK-SLOW-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0592 ; CHECK-SLOW-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1593 ; CHECK-SLOW-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31594 ; CHECK-SLOW-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0595 ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32596 ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]].sub_32597 ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]598 ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY [[COPY]]599 ; CHECK-SLOW-NEXT: [[ADDXrx:%[0-9]+]]:gpr64sp = ADDXrx [[COPY4]], [[COPY3]], 1600 ; CHECK-SLOW-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[ADDXrx]], 0 :: (load (s16))601 ; CHECK-SLOW-NEXT: [[LDRHHui1:%[0-9]+]]:gpr32 = LDRHHui [[ADDXrx]], 0 :: (load (s16))602 ; CHECK-SLOW-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRHHui]], [[LDRHHui1]]603 ; CHECK-SLOW-NEXT: RET_ReallyLR implicit [[ADDWrr]]604 %0:gpr(p0) = COPY $x0605 %1:gpr(s32) = COPY $w1606 %15:gpr(s64) = G_CONSTANT i64 9607 %3:gpr(s32) = G_LSHR %1, %15(s64)608 %4:gpr(s64) = G_ZEXT %3(s32)609 %5:gpr(s64) = G_CONSTANT i64 255610 %6:gpr(s64) = G_AND %4, %5611 %13:gpr(s64) = G_CONSTANT i64 1612 %8:gpr(s64) = G_SHL %6, %13(s64)613 %9:gpr(p0) = G_PTR_ADD %0, %8(s64)614 %12:gpr(s32) = G_LOAD %9(p0) :: (load (s16))615 %17:gpr(s32) = G_LOAD %9(p0) :: (load (s16))616 %18:gpr(s32) = G_ADD %12, %17617 RET_ReallyLR implicit %18618...619---620# Fold SHL into LSL for memory ops. Do not fold if the target has LSLSLOW14.621name: ldrhrox_more_than_one_use_shl622alignment: 4623legalized: true624regBankSelected: true625tracksRegLiveness: true626machineFunctionInfo: {}627body: |628 bb.0:629 liveins: $x0, $x1, $x2630 liveins: $w1, $x0631 632 ; CHECK-FAST-LABEL: name: ldrhrox_more_than_one_use_shl633 ; CHECK-FAST: liveins: $x0, $x1, $x2, $w1, $x0634 ; CHECK-FAST-NEXT: {{ $}}635 ; CHECK-FAST-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0636 ; CHECK-FAST-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1637 ; CHECK-FAST-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31638 ; CHECK-FAST-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0639 ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32640 ; CHECK-FAST-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103641 ; CHECK-FAST-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16))642 ; CHECK-FAST-NEXT: [[LDRHHroX1:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16))643 ; CHECK-FAST-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRHHroX]], [[LDRHHroX1]]644 ; CHECK-FAST-NEXT: RET_ReallyLR implicit [[ADDWrr]]645 ;646 ; CHECK-SLOW-LABEL: name: ldrhrox_more_than_one_use_shl647 ; CHECK-SLOW: liveins: $x0, $x1, $x2, $w1, $x0648 ; CHECK-SLOW-NEXT: {{ $}}649 ; CHECK-SLOW-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0650 ; CHECK-SLOW-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1651 ; CHECK-SLOW-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31652 ; CHECK-SLOW-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0653 ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32654 ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]].sub_32655 ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]656 ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY [[COPY]]657 ; CHECK-SLOW-NEXT: [[ADDXrx:%[0-9]+]]:gpr64sp = ADDXrx [[COPY4]], [[COPY3]], 1658 ; CHECK-SLOW-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[ADDXrx]], 0 :: (load (s16))659 ; CHECK-SLOW-NEXT: [[LDRHHui1:%[0-9]+]]:gpr32 = LDRHHui [[ADDXrx]], 0 :: (load (s16))660 ; CHECK-SLOW-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRHHui]], [[LDRHHui1]]661 ; CHECK-SLOW-NEXT: RET_ReallyLR implicit [[ADDWrr]]662 %0:gpr(p0) = COPY $x0663 %1:gpr(s32) = COPY $w1664 %15:gpr(s64) = G_CONSTANT i64 9665 %3:gpr(s32) = G_LSHR %1, %15(s64)666 %4:gpr(s64) = G_ZEXT %3(s32)667 %5:gpr(s64) = G_CONSTANT i64 255668 %6:gpr(s64) = G_AND %4, %5669 %13:gpr(s64) = G_CONSTANT i64 1670 %8:gpr(s64) = G_SHL %6, %13(s64)671 %9:gpr(p0) = G_PTR_ADD %0, %8(s64)672 %12:gpr(s32) = G_LOAD %9(p0) :: (load (s16))673 %17:gpr(s32) = G_LOAD %9(p0) :: (load (s16))674 %18:gpr(s32) = G_ADD %12, %17675 RET_ReallyLR implicit %18676...677---678# Fold SHL into LSL for memory ops.679name: ldrwrox_more_than_one_use_shl680alignment: 4681legalized: true682regBankSelected: true683tracksRegLiveness: true684machineFunctionInfo: {}685body: |686 bb.0:687 liveins: $x0, $x1, $x2688 ; CHECK-LABEL: name: ldrwrox_more_than_one_use_shl689 ; CHECK: liveins: $x0, $x1, $x2690 ; CHECK-NEXT: {{ $}}691 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0692 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 62, 61693 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1694 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]695 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[UBFMXri]]696 ; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[COPY1]], [[COPY]], 0, 1 :: (load (s32) from %ir.addr)697 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[LDRWroX]], 0698 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32699 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 2, 0700 ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[SUBREG_TO_REG]], [[ADDXri]]701 ; CHECK-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[ADDXrr1]]702 ; CHECK-NEXT: $x2 = COPY [[ADDXrr2]]703 ; CHECK-NEXT: RET_ReallyLR implicit $x2704 %0:gpr(s64) = COPY $x0705 %1:gpr(s64) = G_CONSTANT i64 2706 %2:gpr(s64) = G_SHL %0, %1(s64)707 %3:gpr(p0) = COPY $x1708 %4:gpr(p0) = G_PTR_ADD %3, %2709 %20:gpr(s32) = G_LOAD %4(p0) :: (load (s32) from %ir.addr)710 %5:gpr(s64) = G_ZEXT %20711 %6:gpr(s64) = G_ADD %2, %1712 %7:gpr(s64) = G_ADD %5, %6713 %8:gpr(s64) = G_PTRTOINT %4714 %9:gpr(s64) = G_ADD %8, %7715 $x2 = COPY %9(s64)716 RET_ReallyLR implicit $x2717...718---719# Fold SHL into LSL for memory ops. Do not fold if the target has LSLSLOW14.720name: ldrqrox_more_than_one_use_shl721alignment: 4722legalized: true723regBankSelected: true724tracksRegLiveness: true725machineFunctionInfo: {}726body: |727 bb.0:728 liveins: $x0, $x1, $x2729 ; CHECK-FAST-LABEL: name: ldrqrox_more_than_one_use_shl730 ; CHECK-FAST: liveins: $x0, $x1, $x2731 ; CHECK-FAST-NEXT: {{ $}}732 ; CHECK-FAST-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0733 ; CHECK-FAST-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 60, 59734 ; CHECK-FAST-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1735 ; CHECK-FAST-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]736 ; CHECK-FAST-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[UBFMXri]]737 ; CHECK-FAST-NEXT: [[LDRQroX:%[0-9]+]]:fpr128 = LDRQroX [[COPY1]], [[COPY]], 0, 1 :: (load (s128) from %ir.addr)738 ; CHECK-FAST-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 4, 0739 ; CHECK-FAST-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[LDRQroX]].dsub740 ; CHECK-FAST-NEXT: [[COPY4:%[0-9]+]]:gpr64 = COPY [[COPY3]]741 ; CHECK-FAST-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[COPY4]], [[ADDXri]]742 ; CHECK-FAST-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[ADDXrr1]]743 ; CHECK-FAST-NEXT: RET_ReallyLR implicit [[ADDXrr2]]744 ;745 ; CHECK-SLOW-LABEL: name: ldrqrox_more_than_one_use_shl746 ; CHECK-SLOW: liveins: $x0, $x1, $x2747 ; CHECK-SLOW-NEXT: {{ $}}748 ; CHECK-SLOW-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0749 ; CHECK-SLOW-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 60, 59750 ; CHECK-SLOW-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1751 ; CHECK-SLOW-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr [[COPY1]], [[UBFMXri]]752 ; CHECK-SLOW-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADDXrr]], 0 :: (load (s128) from %ir.addr)753 ; CHECK-SLOW-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 4, 0754 ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[LDRQui]].dsub755 ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]756 ; CHECK-SLOW-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[COPY3]], [[ADDXri]]757 ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64 = COPY [[ADDXrr]]758 ; CHECK-SLOW-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[COPY4]], [[ADDXrr1]]759 ; CHECK-SLOW-NEXT: RET_ReallyLR implicit [[ADDXrr2]]760 %0:gpr(s64) = COPY $x0761 %1:gpr(s64) = G_CONSTANT i64 4762 %2:gpr(s64) = G_SHL %0, %1(s64)763 %3:gpr(p0) = COPY $x1764 %4:gpr(p0) = G_PTR_ADD %3, %2765 %20:fpr(s128) = G_LOAD %4(p0) :: (load (s128) from %ir.addr)766 %6:gpr(s64) = G_ADD %2, %1767 %200:fpr(s64) = G_TRUNC %20768 %2000:gpr(s64) = COPY %200769 %7:gpr(s64) = G_ADD %2000, %6770 %8:gpr(s64) = G_PTRTOINT %4771 %9:gpr(s64) = G_ADD %8, %7772 RET_ReallyLR implicit %9773...774---775# Show that when we have a fastpath for shift-left, we perform the folding776# if it has more than one use.777 778name: more_than_one_use_shl_lsl779alignment: 4780legalized: true781regBankSelected: true782tracksRegLiveness: true783machineFunctionInfo: {}784body: |785 bb.0:786 liveins: $x0, $x1, $x2787 ; CHECK-LABEL: name: more_than_one_use_shl_lsl788 ; CHECK: liveins: $x0, $x1, $x2789 ; CHECK-NEXT: {{ $}}790 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0791 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1792 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)793 ; CHECK-NEXT: [[LDRXroX1:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)794 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[LDRXroX1]]795 ; CHECK-NEXT: $x2 = COPY [[ADDXrr]]796 ; CHECK-NEXT: RET_ReallyLR implicit $x2797 %0:gpr(s64) = COPY $x0798 %1:gpr(s64) = G_CONSTANT i64 3799 %2:gpr(s64) = G_SHL %0, %1(s64)800 %3:gpr(p0) = COPY $x1801 %4:gpr(p0) = G_PTR_ADD %3, %2802 %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)803 %6:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)804 %7:gpr(s64) = G_ADD %5, %6805 $x2 = COPY %7(s64)806 RET_ReallyLR implicit $x2807 808...809---810# Show that when we're optimizing for size, we'll do the folding no matter811# what.812 813name: more_than_one_use_shl_minsize814alignment: 4815legalized: true816regBankSelected: true817tracksRegLiveness: true818machineFunctionInfo: {}819body: |820 bb.0:821 liveins: $x0, $x1, $x2822 ; CHECK-LABEL: name: more_than_one_use_shl_minsize823 ; CHECK: liveins: $x0, $x1, $x2824 ; CHECK-NEXT: {{ $}}825 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0826 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 61, 60827 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1828 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]829 ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY2]], [[COPY]], 3830 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)831 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 3, 0832 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[ADDXri]]833 ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrs]], [[ADDXrr]]834 ; CHECK-NEXT: $x2 = COPY [[ADDXrr1]]835 ; CHECK-NEXT: RET_ReallyLR implicit $x2836 %0:gpr(s64) = COPY $x0837 %1:gpr(s64) = G_CONSTANT i64 3838 %2:gpr(s64) = G_SHL %0, %1(s64)839 %3:gpr(p0) = COPY $x1840 %4:gpr(p0) = G_PTR_ADD %3, %2841 %5:gpr(s64) = G_LOAD %4(p0) :: (load (s64) from %ir.addr)842 %6:gpr(s64) = G_ADD %2, %1843 %7:gpr(s64) = G_ADD %5, %6844 %8:gpr(s64) = G_PTRTOINT %4845 %9:gpr(s64) = G_ADD %8, %7846 $x2 = COPY %9(s64)847 RET_ReallyLR implicit $x2848...849---850name: ldrwrox851alignment: 4852legalized: true853regBankSelected: true854tracksRegLiveness: true855machineFunctionInfo: {}856body: |857 bb.0:858 liveins: $x0, $x1859 ; CHECK-LABEL: name: ldrwrox860 ; CHECK: liveins: $x0, $x1861 ; CHECK-NEXT: {{ $}}862 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0863 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1864 ; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[COPY]], [[COPY1]], 0, 0 :: (load (s32) from %ir.addr)865 ; CHECK-NEXT: $w2 = COPY [[LDRWroX]]866 ; CHECK-NEXT: RET_ReallyLR implicit $w2867 %0:gpr(p0) = COPY $x0868 %1:gpr(s64) = COPY $x1869 %2:gpr(p0) = G_PTR_ADD %0, %1870 %4:gpr(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.addr)871 $w2 = COPY %4(s32)872 RET_ReallyLR implicit $w2873...874---875name: ldrsrox876alignment: 4877legalized: true878regBankSelected: true879tracksRegLiveness: true880machineFunctionInfo: {}881body: |882 bb.0:883 liveins: $d0, $x1884 ; CHECK-LABEL: name: ldrsrox885 ; CHECK: liveins: $d0, $x1886 ; CHECK-NEXT: {{ $}}887 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $d0888 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1889 ; CHECK-NEXT: [[LDRSroX:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], [[COPY1]], 0, 0 :: (load (s32) from %ir.addr)890 ; CHECK-NEXT: $s2 = COPY [[LDRSroX]]891 ; CHECK-NEXT: RET_ReallyLR implicit $h2892 %0:gpr(p0) = COPY $d0893 %1:gpr(s64) = COPY $x1894 %2:gpr(p0) = G_PTR_ADD %0, %1895 %4:fpr(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.addr)896 $s2 = COPY %4(s32)897 RET_ReallyLR implicit $h2898...899---900name: ldrhrox901alignment: 4902legalized: true903regBankSelected: true904tracksRegLiveness: true905machineFunctionInfo: {}906body: |907 bb.0:908 liveins: $x0, $x1909 ; CHECK-LABEL: name: ldrhrox910 ; CHECK: liveins: $x0, $x1911 ; CHECK-NEXT: {{ $}}912 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0913 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1914 ; CHECK-NEXT: [[LDRHroX:%[0-9]+]]:fpr16 = LDRHroX [[COPY]], [[COPY1]], 0, 0 :: (load (s16) from %ir.addr)915 ; CHECK-NEXT: $h2 = COPY [[LDRHroX]]916 ; CHECK-NEXT: RET_ReallyLR implicit $h2917 %0:gpr(p0) = COPY $x0918 %1:gpr(s64) = COPY $x1919 %2:gpr(p0) = G_PTR_ADD %0, %1920 %4:fpr(s16) = G_LOAD %2(p0) :: (load (s16) from %ir.addr)921 $h2 = COPY %4(s16)922 RET_ReallyLR implicit $h2923...924---925name: ldbbrox926alignment: 4927legalized: true928regBankSelected: true929tracksRegLiveness: true930machineFunctionInfo: {}931body: |932 bb.0:933 liveins: $x0, $x1934 ; CHECK-LABEL: name: ldbbrox935 ; CHECK: liveins: $x0, $x1936 ; CHECK-NEXT: {{ $}}937 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0938 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1939 ; CHECK-NEXT: [[LDRBBroX:%[0-9]+]]:gpr32 = LDRBBroX [[COPY]], [[COPY1]], 0, 0 :: (load (s8) from %ir.addr)940 ; CHECK-NEXT: $w2 = COPY [[LDRBBroX]]941 ; CHECK-NEXT: RET_ReallyLR implicit $w2942 %0:gpr(p0) = COPY $x0943 %1:gpr(s64) = COPY $x1944 %2:gpr(p0) = G_PTR_ADD %0, %1945 %4:gpr(s32) = G_LOAD %2(p0) :: (load (s8) from %ir.addr)946 $w2 = COPY %4(s32)947 RET_ReallyLR implicit $w2948...949---950name: ldrqrox951alignment: 4952legalized: true953regBankSelected: true954tracksRegLiveness: true955machineFunctionInfo: {}956body: |957 bb.0:958 liveins: $d0, $x1959 ; CHECK-LABEL: name: ldrqrox960 ; CHECK: liveins: $d0, $x1961 ; CHECK-NEXT: {{ $}}962 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $d0963 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1964 ; CHECK-NEXT: [[LDRQroX:%[0-9]+]]:fpr128 = LDRQroX [[COPY]], [[COPY1]], 0, 0 :: (load (<2 x s64>) from %ir.addr)965 ; CHECK-NEXT: $q0 = COPY [[LDRQroX]]966 ; CHECK-NEXT: RET_ReallyLR implicit $q0967 %0:gpr(p0) = COPY $d0968 %1:gpr(s64) = COPY $x1969 %2:gpr(p0) = G_PTR_ADD %0, %1970 %4:fpr(<2 x s64>) = G_LOAD %2(p0) :: (load (<2 x s64>) from %ir.addr)971 $q0 = COPY %4(<2 x s64>)972 RET_ReallyLR implicit $q0973