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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=localizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK3 4# Test the localizer.5 6--- |7 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"8 9 define void @local_use() { ret void }10 define void @non_local_1use() { ret void }11 define void @non_local_2uses() { ret void }12 define void @non_local_phi_use() { ret void }13 define void @non_local_phi_use_followed_by_use() { ret void }14 define void @non_local_phi_use_followed_by_use_fi() { ret void }15 define void @float_non_local_phi_use_followed_by_use_fi() { ret void }16 define void @non_local_phi() { ret void }17 define void @non_local_label() { ret void }18 19 @var1 = common global i32 0, align 420 @var2 = common global i32 0, align 421 @var3 = common global i32 0, align 422 @var4 = common global i32 0, align 423 24 define i32 @intrablock_with_globalvalue() {25 entry:26 %0 = load i32, ptr @var1, align 427 %cmp = icmp eq i32 %0, 128 br i1 %cmp, label %if.then, label %if.end29 30 if.then:31 store i32 2, ptr @var2, align 432 store i32 3, ptr @var1, align 433 store i32 2, ptr @var3, align 434 store i32 3, ptr @var1, align 435 br label %if.end36 37 if.end:38 ret i32 039 }40 define i32 @adrp_add() {41 entry:42 %0 = load i32, ptr @var1, align 443 %cmp = icmp eq i32 %0, 144 br i1 %cmp, label %if.then, label %if.end45 46 if.then:47 store i32 2, ptr @var2, align 448 store i32 3, ptr @var1, align 449 store i32 2, ptr @var3, align 450 store i32 3, ptr @var1, align 451 br label %if.end52 53 if.end:54 ret i32 055 }56 57 define void @test_inttoptr() { ret void }58 define void @many_local_use_intra_block() { ret void }59 define void @non_local_phi_single_use() { ret void }60 define void @non_local_phi_three_uses() { ret void }61 62...63 64---65name: local_use66legalized: true67regBankSelected: true68body: |69 bb.0:70 ; CHECK-LABEL: name: local_use71 ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 172 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]73 %0:gpr(s32) = G_CONSTANT i32 174 %1:gpr(s32) = G_ADD %0, %075...76 77---78name: non_local_1use79legalized: true80regBankSelected: true81body: |82 ; CHECK-LABEL: name: non_local_1use83 ; CHECK: bb.0:84 ; CHECK-NEXT: successors: %bb.1(0x80000000)85 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 187 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]88 ; CHECK-NEXT: {{ $}}89 ; CHECK-NEXT: bb.1:90 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 191 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[ADD]]92 93 ; Existing registers should be left untouched94 ; The newly created reg should be on the same regbank/regclass as its origin.95 96 bb.0:97 successors: %bb.198 99 %0:gpr(s32) = G_CONSTANT i32 1100 %1:gpr(s32) = G_ADD %0, %0101 102 bb.1:103 %2:gpr(s32) = G_ADD %0, %1104...105 106---107name: non_local_2uses108legalized: true109regBankSelected: true110body: |111 ; CHECK-LABEL: name: non_local_2uses112 ; CHECK: bb.0:113 ; CHECK-NEXT: successors: %bb.1(0x80000000)114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1116 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: bb.1:119 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1120 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[C1]]121 122 ; Existing registers should be left untouched123 ; The newly created reg should be on the same regbank/regclass as its origin.124 125 bb.0:126 successors: %bb.1127 128 %0:gpr(s32) = G_CONSTANT i32 1129 %1:gpr(s32) = G_ADD %0, %0130 131 bb.1:132 %2:gpr(s32) = G_ADD %0, %0133...134 135---136name: non_local_phi_use137legalized: true138regBankSelected: true139tracksRegLiveness: true140body: |141 ; CHECK-LABEL: name: non_local_phi_use142 ; CHECK: bb.0:143 ; CHECK-NEXT: successors: %bb.1(0x80000000)144 ; CHECK-NEXT: {{ $}}145 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1146 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: bb.1:149 ; CHECK-NEXT: successors: %bb.2(0x80000000)150 ; CHECK-NEXT: {{ $}}151 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1152 ; CHECK-NEXT: {{ $}}153 ; CHECK-NEXT: bb.2:154 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1155 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[PHI]]156 157 ; Existing registers should be left untouched158 ; The newly created reg should be on the same regbank/regclass as its origin.159 160 bb.0:161 successors: %bb.1162 163 %0:gpr(s32) = G_CONSTANT i32 1164 %1:gpr(s32) = G_ADD %0, %0165 166 bb.1:167 successors: %bb.2168 169 bb.2:170 %3:gpr(s32) = PHI %0(s32), %bb.1171 %2:gpr(s32) = G_ADD %3, %3172...173 174---175name: non_local_phi_use_followed_by_use176legalized: true177regBankSelected: true178tracksRegLiveness: true179body: |180 ; CHECK-LABEL: name: non_local_phi_use_followed_by_use181 ; CHECK: bb.0:182 ; CHECK-NEXT: successors: %bb.1(0x80000000)183 ; CHECK-NEXT: {{ $}}184 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1185 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]186 ; CHECK-NEXT: {{ $}}187 ; CHECK-NEXT: bb.1:188 ; CHECK-NEXT: successors: %bb.2(0x80000000)189 ; CHECK-NEXT: {{ $}}190 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1191 ; CHECK-NEXT: {{ $}}192 ; CHECK-NEXT: bb.2:193 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1194 ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1195 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[C2]]196 197 ; Existing registers should be left untouched198 ; The newly created reg should be on the same regbank/regclass as its origin.199 200 bb.0:201 successors: %bb.1202 203 %0:gpr(s32) = G_CONSTANT i32 1204 %1:gpr(s32) = G_ADD %0, %0205 206 bb.1:207 successors: %bb.2208 209 bb.2:210 %3:gpr(s32) = PHI %0(s32), %bb.1211 %2:gpr(s32) = G_ADD %3, %0212...213 214---215name: non_local_phi_use_followed_by_use_fi216legalized: true217regBankSelected: true218tracksRegLiveness: true219body: |220 ; CHECK-LABEL: name: non_local_phi_use_followed_by_use_fi221 ; CHECK: bb.0:222 ; CHECK-NEXT: successors: %bb.1(0x80000000)223 ; CHECK-NEXT: {{ $}}224 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1225 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[FRAME_INDEX]], [[FRAME_INDEX]]226 ; CHECK-NEXT: {{ $}}227 ; CHECK-NEXT: bb.1:228 ; CHECK-NEXT: successors: %bb.2(0x80000000)229 ; CHECK-NEXT: {{ $}}230 ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1231 ; CHECK-NEXT: {{ $}}232 ; CHECK-NEXT: bb.2:233 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = PHI [[FRAME_INDEX1]](s32), %bb.1234 ; CHECK-NEXT: [[FRAME_INDEX2:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1235 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[FRAME_INDEX2]]236 237 ; Existing registers should be left untouched238 ; The newly created reg should be on the same regbank/regclass as its origin.239 240 bb.0:241 successors: %bb.1242 243 %0:gpr(s32) = G_FRAME_INDEX 1244 %1:gpr(s32) = G_ADD %0, %0245 246 bb.1:247 successors: %bb.2248 249 bb.2:250 %3:gpr(s32) = PHI %0(s32), %bb.1251 %2:gpr(s32) = G_ADD %3, %0252...253 254---255name: float_non_local_phi_use_followed_by_use_fi256legalized: true257regBankSelected: true258tracksRegLiveness: true259body: |260 ; CHECK-LABEL: name: float_non_local_phi_use_followed_by_use_fi261 ; CHECK: bb.0:262 ; CHECK-NEXT: successors: %bb.1(0x80000000)263 ; CHECK-NEXT: {{ $}}264 ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00265 ; CHECK-NEXT: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[C]], [[C]]266 ; CHECK-NEXT: {{ $}}267 ; CHECK-NEXT: bb.1:268 ; CHECK-NEXT: successors: %bb.2(0x80000000)269 ; CHECK-NEXT: {{ $}}270 ; CHECK-NEXT: [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00271 ; CHECK-NEXT: {{ $}}272 ; CHECK-NEXT: bb.2:273 ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr(s32) = PHI [[C1]](s32), %bb.1274 ; CHECK-NEXT: [[C2:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00275 ; CHECK-NEXT: [[FADD1:%[0-9]+]]:fpr(s32) = G_FADD [[PHI]], [[C2]]276 277 ; Existing registers should be left untouched278 ; The newly created reg should be on the same regbank/regclass as its origin.279 280 bb.0:281 successors: %bb.1282 283 %0:fpr(s32) = G_FCONSTANT float 1.0284 %1:fpr(s32) = G_FADD %0, %0285 286 bb.1:287 successors: %bb.2288 289 bb.2:290 %3:fpr(s32) = PHI %0(s32), %bb.1291 %2:fpr(s32) = G_FADD %3, %0292...293 294---295# Make sure we don't insert a constant before PHIs.296# This used to happen for loops of one basic block.297name: non_local_phi298legalized: true299regBankSelected: true300tracksRegLiveness: true301body: |302 ; CHECK-LABEL: name: non_local_phi303 ; CHECK: bb.0:304 ; CHECK-NEXT: successors: %bb.1(0x80000000)305 ; CHECK-NEXT: {{ $}}306 ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00307 ; CHECK-NEXT: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[C]], [[C]]308 ; CHECK-NEXT: {{ $}}309 ; CHECK-NEXT: bb.1:310 ; CHECK-NEXT: successors: %bb.1(0x80000000)311 ; CHECK-NEXT: {{ $}}312 ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr(s32) = PHI [[FADD]](s32), %bb.0, %4(s32), %bb.1313 ; CHECK-NEXT: [[FADD1:%[0-9]+]]:fpr(s32) = G_FADD [[PHI]], [[FADD]]314 ; CHECK-NEXT: [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00315 ; CHECK-NEXT: G_BR %bb.1316 317 ; Existing registers should be left untouched318 ; The newly created reg should be on the same regbank/regclass as its origin.319 320 bb.0:321 successors: %bb.1322 323 %0:fpr(s32) = G_FCONSTANT float 1.0324 %1:fpr(s32) = G_FADD %0, %0325 326 bb.1:327 successors: %bb.1328 329 %3:fpr(s32) = PHI %1(s32), %bb.0, %0(s32), %bb.1330 %2:fpr(s32) = G_FADD %3, %1331 G_BR %bb.1332...333 334---335# Make sure we don't insert a constant before EH_LABELs.336name: non_local_label337legalized: true338regBankSelected: true339tracksRegLiveness: true340body: |341 ; CHECK-LABEL: name: non_local_label342 ; CHECK: bb.0:343 ; CHECK-NEXT: successors: %bb.1(0x80000000)344 ; CHECK-NEXT: liveins: $s0345 ; CHECK-NEXT: {{ $}}346 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0347 ; CHECK-NEXT: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00348 ; CHECK-NEXT: {{ $}}349 ; CHECK-NEXT: bb.1:350 ; CHECK-NEXT: successors: %bb.1(0x80000000)351 ; CHECK-NEXT: {{ $}}352 ; CHECK-NEXT: EH_LABEL 1353 ; CHECK-NEXT: [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00354 ; CHECK-NEXT: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[COPY]], [[C1]]355 ; CHECK-NEXT: G_BR %bb.1356 357 ; Existing registers should be left untouched358 ; The newly created reg should be on the same regbank/regclass as its origin.359 360 bb.0:361 liveins: $s0362 successors: %bb.1363 364 %0:fpr(s32) = COPY $s0365 %1:fpr(s32) = G_FCONSTANT float 1.0366 367 bb.1:368 successors: %bb.1369 370 EH_LABEL 1371 %2:fpr(s32) = G_FADD %0, %1372 G_BR %bb.1373...374---375name: intrablock_with_globalvalue376legalized: true377regBankSelected: true378tracksRegLiveness: true379body: |380 ; CHECK-LABEL: name: intrablock_with_globalvalue381 ; CHECK: bb.0.entry:382 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)383 ; CHECK-NEXT: {{ $}}384 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2385 ; CHECK-NEXT: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2386 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3387 ; CHECK-NEXT: [[GV1:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3388 ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0389 ; CHECK-NEXT: [[GV2:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1390 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[GV2]](p0) :: (load (s32) from @var1)391 ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1392 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]393 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)394 ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1395 ; CHECK-NEXT: G_BR %bb.2396 ; CHECK-NEXT: {{ $}}397 ; CHECK-NEXT: bb.1.if.then:398 ; CHECK-NEXT: successors: %bb.2(0x80000000)399 ; CHECK-NEXT: {{ $}}400 ; CHECK-NEXT: [[GV3:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var2401 ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2402 ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV3]](p0) :: (store (s32) into @var2)403 ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3404 ; CHECK-NEXT: [[GV4:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var1405 ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV4]](p0) :: (store (s32) into @var1)406 ; CHECK-NEXT: [[GV5:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @var3407 ; CHECK-NEXT: G_STORE [[C4]](s32), [[GV5]](p0) :: (store (s32) into @var3)408 ; CHECK-NEXT: G_STORE [[C5]](s32), [[GV4]](p0) :: (store (s32) into @var1)409 ; CHECK-NEXT: {{ $}}410 ; CHECK-NEXT: bb.2.if.end:411 ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0412 ; CHECK-NEXT: $w0 = COPY [[C6]](s32)413 ; CHECK-NEXT: RET_ReallyLR implicit $w0414 415 ; Some of these instructions are dead. We're checking that the other instructions are416 ; sunk immediately before their first user in the if.then block or as close as possible.417 bb.1.entry:418 %1:gpr(p0) = G_GLOBAL_VALUE @var1419 %2:gpr(s32) = G_CONSTANT i32 1420 %4:gpr(s32) = G_CONSTANT i32 2421 %5:gpr(p0) = G_GLOBAL_VALUE @var2422 %6:gpr(s32) = G_CONSTANT i32 3423 %7:gpr(p0) = G_GLOBAL_VALUE @var3424 %8:gpr(s32) = G_CONSTANT i32 0425 %0:gpr(s32) = G_LOAD %1(p0) :: (load (s32) from @var1)426 %9:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2427 %3:gpr(s1) = G_TRUNC %9(s32)428 G_BRCOND %3(s1), %bb.2429 G_BR %bb.3430 431 bb.2.if.then:432 G_STORE %4(s32), %5(p0) :: (store (s32) into @var2)433 G_STORE %6(s32), %1(p0) :: (store (s32) into @var1)434 G_STORE %4(s32), %7(p0) :: (store (s32) into @var3)435 G_STORE %6(s32), %1(p0) :: (store (s32) into @var1)436 437 bb.3.if.end:438 $w0 = COPY %8(s32)439 RET_ReallyLR implicit $w0440 441...442---443name: adrp_add444legalized: true445regBankSelected: true446tracksRegLiveness: true447body: |448 ; CHECK-LABEL: name: adrp_add449 ; CHECK: bb.0.entry:450 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)451 ; CHECK-NEXT: {{ $}}452 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var1453 ; CHECK-NEXT: %addlow1:gpr(p0) = G_ADD_LOW [[ADRP]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var1454 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2455 ; CHECK-NEXT: [[ADRP1:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var2456 ; CHECK-NEXT: %addlow2:gpr(p0) = G_ADD_LOW [[ADRP1]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var2457 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3458 ; CHECK-NEXT: [[ADRP2:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var3459 ; CHECK-NEXT: %addlow3:gpr(p0) = G_ADD_LOW [[ADRP2]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var3460 ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0461 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[ADRP]](p0) :: (load (s32) from @var1)462 ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1463 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]464 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)465 ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1466 ; CHECK-NEXT: G_BR %bb.2467 ; CHECK-NEXT: {{ $}}468 ; CHECK-NEXT: bb.1.if.then:469 ; CHECK-NEXT: successors: %bb.2(0x80000000)470 ; CHECK-NEXT: {{ $}}471 ; CHECK-NEXT: [[ADRP3:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var2472 ; CHECK-NEXT: [[ADD_LOW:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP3]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var2473 ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2474 ; CHECK-NEXT: G_STORE [[C4]](s32), [[ADD_LOW]](p0) :: (store (s32) into @var2)475 ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 3476 ; CHECK-NEXT: [[ADRP4:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var1477 ; CHECK-NEXT: [[ADD_LOW1:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP4]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var1478 ; CHECK-NEXT: G_STORE [[C5]](s32), [[ADD_LOW1]](p0) :: (store (s32) into @var1)479 ; CHECK-NEXT: [[ADRP5:%[0-9]+]]:gpr64(p0) = ADRP target-flags(aarch64-page) @var3480 ; CHECK-NEXT: [[ADD_LOW2:%[0-9]+]]:gpr(p0) = G_ADD_LOW [[ADRP5]](p0), target-flags(aarch64-pageoff, aarch64-nc) @var3481 ; CHECK-NEXT: G_STORE [[C4]](s32), [[ADD_LOW2]](p0) :: (store (s32) into @var3)482 ; CHECK-NEXT: G_STORE [[C5]](s32), [[ADD_LOW1]](p0) :: (store (s32) into @var1)483 ; CHECK-NEXT: {{ $}}484 ; CHECK-NEXT: bb.2.if.end:485 ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0486 ; CHECK-NEXT: $w0 = COPY [[C6]](s32)487 ; CHECK-NEXT: RET_ReallyLR implicit $w0488 489 ; Some of these instructions are dead.490 bb.1.entry:491 %1:gpr64(p0) = ADRP target-flags(aarch64-page) @var1492 %addlow1:gpr(p0) = G_ADD_LOW %1(p0), target-flags(aarch64-pageoff, aarch64-nc) @var1493 %2:gpr(s32) = G_CONSTANT i32 1494 %4:gpr(s32) = G_CONSTANT i32 2495 %5:gpr64(p0) = ADRP target-flags(aarch64-page) @var2496 %addlow2:gpr(p0) = G_ADD_LOW %5(p0), target-flags(aarch64-pageoff, aarch64-nc) @var2497 %6:gpr(s32) = G_CONSTANT i32 3498 %7:gpr64(p0) = ADRP target-flags(aarch64-page) @var3499 %addlow3:gpr(p0) = G_ADD_LOW %7(p0), target-flags(aarch64-pageoff, aarch64-nc) @var3500 %8:gpr(s32) = G_CONSTANT i32 0501 %0:gpr(s32) = G_LOAD %1(p0) :: (load (s32) from @var1)502 %9:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2503 %3:gpr(s1) = G_TRUNC %9(s32)504 G_BRCOND %3(s1), %bb.2505 G_BR %bb.3506 507 bb.2.if.then:508 G_STORE %4(s32), %addlow2(p0) :: (store (s32) into @var2)509 G_STORE %6(s32), %addlow1(p0) :: (store (s32) into @var1)510 G_STORE %4(s32), %addlow3(p0) :: (store (s32) into @var3)511 G_STORE %6(s32), %addlow1(p0) :: (store (s32) into @var1)512 513 bb.3.if.end:514 $w0 = COPY %8(s32)515 RET_ReallyLR implicit $w0516 517...518---519name: test_inttoptr520alignment: 4521legalized: true522regBankSelected: true523tracksRegLiveness: true524body: |525 ; CHECK-LABEL: name: test_inttoptr526 ; CHECK: bb.0:527 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)528 ; CHECK-NEXT: liveins: $w0, $x1529 ; CHECK-NEXT: {{ $}}530 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0531 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $x1532 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0533 ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C]](s64)534 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 128535 ; CHECK-NEXT: [[INTTOPTR1:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C1]](s64)536 ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0537 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C2]]538 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)539 ; CHECK-NEXT: G_BRCOND [[TRUNC]](s1), %bb.1540 ; CHECK-NEXT: G_BR %bb.2541 ; CHECK-NEXT: {{ $}}542 ; CHECK-NEXT: bb.1:543 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY]]544 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[COPY1]](p0) :: (store (s32))545 ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 128546 ; CHECK-NEXT: [[INTTOPTR2:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C3]](s64)547 ; CHECK-NEXT: $x0 = COPY [[INTTOPTR2]](p0)548 ; CHECK-NEXT: RET_ReallyLR implicit $x0549 ; CHECK-NEXT: {{ $}}550 ; CHECK-NEXT: bb.2:551 ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0552 ; CHECK-NEXT: [[INTTOPTR3:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[C4]](s64)553 ; CHECK-NEXT: $x0 = COPY [[INTTOPTR3]](p0)554 ; CHECK-NEXT: RET_ReallyLR implicit $x0555 bb.1:556 liveins: $w0, $x1557 558 %0:gpr(s32) = COPY $w0559 %1:gpr(p0) = COPY $x1560 %2:gpr(s64) = G_CONSTANT i64 128561 %4:gpr(s32) = G_CONSTANT i32 0562 %7:gpr(s64) = G_CONSTANT i64 0563 %6:gpr(p0) = G_INTTOPTR %7(s64)564 %3:gpr(p0) = G_INTTOPTR %2(s64)565 %9:gpr(s32) = G_ICMP intpred(eq), %0(s32), %4566 %5:gpr(s1) = G_TRUNC %9(s32)567 G_BRCOND %5(s1), %bb.2568 G_BR %bb.3569 570 bb.2:571 %8:gpr(s32) = G_ADD %0, %0572 G_STORE %8(s32), %1(p0) :: (store (s32))573 $x0 = COPY %3(p0)574 RET_ReallyLR implicit $x0575 576 bb.3:577 $x0 = COPY %6(p0)578 RET_ReallyLR implicit $x0579 580...581 582---583name: many_local_use_intra_block584legalized: true585regBankSelected: true586body: |587 bb.0:588 ; CHECK-LABEL: name: many_local_use_intra_block589 ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1590 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]591 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]592 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]593 ; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]594 ; CHECK-NEXT: [[ADD4:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]595 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 2596 ; CHECK-NEXT: [[ADD5:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[C1]]597 %0:gpr(s32) = G_CONSTANT i32 1598 %1:gpr(s32) = G_CONSTANT i32 2599 %2:gpr(s32) = G_ADD %0, %0600 %3:gpr(s32) = G_ADD %0, %0601 %4:gpr(s32) = G_ADD %0, %0602 %5:gpr(s32) = G_ADD %0, %0603 %6:gpr(s32) = G_ADD %0, %0604 %7:gpr(s32) = G_ADD %1, %1605...606 607---608name: non_local_phi_single_use609legalized: true610regBankSelected: true611tracksRegLiveness: true612body: |613 ; CHECK-LABEL: name: non_local_phi_single_use614 ; CHECK: bb.0:615 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)616 ; CHECK-NEXT: {{ $}}617 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1618 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]619 ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[ADD]](s32), [[C]]620 ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cmp(s32)621 ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1622 ; CHECK-NEXT: G_BR %bb.2623 ; CHECK-NEXT: {{ $}}624 ; CHECK-NEXT: bb.1:625 ; CHECK-NEXT: successors: %bb.2(0x80000000)626 ; CHECK-NEXT: {{ $}}627 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1628 ; CHECK-NEXT: {{ $}}629 ; CHECK-NEXT: bb.2:630 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[C1]](s32), %bb.1, [[C]](s32), %bb.0631 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[PHI]]632 633 ; Localize the 1 into bb.1, since the number of uses is under the threshold.634 635 bb.0:636 successors: %bb.1, %bb.2637 638 %0:gpr(s32) = G_CONSTANT i32 1639 %1:gpr(s32) = G_ADD %0, %0640 %cmp:gpr(s32) = G_ICMP intpred(eq), %1(s32), %0641 %cond:gpr(s1) = G_TRUNC %cmp(s32)642 G_BRCOND %cond(s1), %bb.1643 G_BR %bb.2644 645 bb.1:646 successors: %bb.2647 648 bb.2:649 %3:gpr(s32) = G_PHI %0(s32), %bb.1, %0(s32), %bb.0650 %2:gpr(s32) = G_ADD %3, %3651...652---653name: non_local_phi_three_uses654legalized: true655regBankSelected: true656tracksRegLiveness: true657body: |658 ; CHECK-LABEL: name: non_local_phi_three_uses659 ; CHECK: bb.0:660 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)661 ; CHECK-NEXT: {{ $}}662 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1663 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]664 ; CHECK-NEXT: %cmp:gpr(s32) = G_ICMP intpred(eq), [[ADD]](s32), [[C]]665 ; CHECK-NEXT: %cond:gpr(s1) = G_TRUNC %cmp(s32)666 ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1667 ; CHECK-NEXT: G_BR %bb.2668 ; CHECK-NEXT: {{ $}}669 ; CHECK-NEXT: bb.1:670 ; CHECK-NEXT: successors: %bb.2(0x80000000)671 ; CHECK-NEXT: {{ $}}672 ; CHECK-NEXT: bb.2:673 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[C]](s32), %bb.1, [[C]](s32), %bb.0, [[C]](s32), %bb.0, [[C]](s32), %bb.0674 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[PHI]]675 676 ; Don't localize the 1 into bb.1, above the thresold of uses in the phi.677 678 bb.0:679 successors: %bb.1, %bb.2680 681 %0:gpr(s32) = G_CONSTANT i32 1682 %1:gpr(s32) = G_ADD %0, %0683 %cmp:gpr(s32) = G_ICMP intpred(eq), %1(s32), %0684 %cond:gpr(s1) = G_TRUNC %cmp(s32)685 G_BRCOND %cond(s1), %bb.1686 G_BR %bb.2687 688 bb.1:689 successors: %bb.2690 691 bb.2:692 %3:gpr(s32) = G_PHI %0(s32), %bb.1, %0(s32), %bb.0, %0(s32), %bb.0, %0(s32), %bb.0693 %2:gpr(s32) = G_ADD %3, %3694...695