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1# RUN: llc -run-pass machine-cse -verify-machineinstrs -mtriple aarch64-apple-ios %s -o - | FileCheck %s2# RUN: llc -passes machine-cse -mtriple aarch64-apple-ios %s -o - | FileCheck %s3---4name: irtranslated5legalized: false6regBankSelected: false7selected: false8body: |9 ; CHECK-LABEL: name: irtranslated10 ; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 111 ; CHECK-NEXT: %[[TWO:[0-9]+]]:_(s32) = G_ADD %[[ONE]], %[[ONE]]12 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]]13 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)14 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]15 bb.0:16 %0:_(s32) = G_CONSTANT i32 117 %1:_(s32) = G_ADD %0, %018 %2:_(s32) = G_ADD %0, %019 %3:_(s32) = G_ADD %1, %220 $w0 = COPY %3(s32)21 RET_ReallyLR implicit $w022...23---24name: regbankselected25legalized: true26regBankSelected: true27selected: false28body: |29 ; CHECK-LABEL: name: regbankselected30 ; CHECK: %[[ONE:[0-9]+]]:gpr(s32) = G_CONSTANT i32 131 ; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]]32 ; CHECK-NEXT: %[[SUM:[0-9]+]]:gpr(s32) = G_ADD %[[TWO]], %[[TWO]]33 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)34 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]35 bb.0:36 %0:gpr(s32) = G_CONSTANT i32 137 %1:gpr(s32) = G_ADD %0, %038 %2:gpr(s32) = G_ADD %0, %039 %3:gpr(s32) = G_ADD %1, %240 $w0 = COPY %3(s32)41 RET_ReallyLR implicit $w042...43---44name: legalized45legalized: true46regBankSelected: false47selected: false48body: |49 ; CHECK-LABEL: name: legalized50 ; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 151 ; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]]52 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]]53 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)54 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]55 bb.0:56 %0:_(s32) = G_CONSTANT i32 157 %1:_(s32) = G_ADD %0, %058 %2:gpr(s32) = G_ADD %0, %059 %3:_(s32) = G_ADD %1, %260 $w0 = COPY %3(s32)61 RET_ReallyLR implicit $w062...63---64name: legalized_sym65legalized: true66regBankSelected: false67selected: false68body: |69 ; CHECK-LABEL: name: legalized_sym70 ; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 171 ; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]]72 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]]73 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)74 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]75 bb.0:76 %0:_(s32) = G_CONSTANT i32 177 %1:gpr(s32) = G_ADD %0, %078 %2:_(s32) = G_ADD %0, %079 %3:_(s32) = G_ADD %1, %280 $w0 = COPY %3(s32)81 RET_ReallyLR implicit $w082...83---84name: int_extensions85alignment: 486legalized: false87regBankSelected: false88selected: false89body: |90 ; CHECK-LABEL: name: int_extensions91 ; CHECK: %[[ONE:[0-9]+]]:_(s8) = G_CONSTANT i8 192 ; CHECK-NEXT: %[[S16:[0-9]+]]:_(s16) = G_SEXT %[[ONE]](s8)93 ; CHECK-NEXT: %[[S32:[0-9]+]]:_(s32) = G_SEXT %[[ONE]](s8)94 ; CHECK-NEXT: %[[S16_Z64:[0-9]+]]:_(s64) = G_ZEXT %[[S16]](s16)95 ; CHECK-NEXT: %[[S32_Z64:[0-9]+]]:_(s64) = G_ZEXT %[[S32]](s32)96 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s64) = G_ADD %[[S16_Z64]], %[[S32_Z64]]97 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s64)98 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]99 bb.0.entry:100 %0:_(s8) = G_CONSTANT i8 1101 %1:_(s16) = G_SEXT %0(s8)102 %2:_(s32) = G_SEXT %0(s8)103 %3:_(s64) = G_ZEXT %1(s16)104 %4:_(s64) = G_ZEXT %2(s32)105 %5:_(s64) = G_ADD %3, %4106 $x0 = COPY %5(s64)107 RET_ReallyLR implicit $x0108...109---110name: generic111legalized: true112regBankSelected: false113selected: false114body: |115 ; CHECK-LABEL: name: generic116 ; CHECK: %[[SG:[0-9]+]]:_(s32) = G_ADD %{{[0-9]+}}, %{{[0-9]+}}117 ; CHECK-NEXT: %{{[0-9]+}}:_(s32) = G_ADD %[[SG]], %[[SG]]118 bb.0:119 %0:_(s32) = COPY $w0120 %1:_(s32) = COPY $w1121 %2:_(s32) = G_ADD %0, %1122 %3:_(s32) = COPY %2(s32)123 %4:_(s32) = G_ADD %3, %3124 $w0 = COPY %4(s32)125 RET_ReallyLR implicit $w0126...127---128name: generic_to_concrete_copy129legalized: true130regBankSelected: false131selected: false132body: |133 ; CHECK-LABEL: name: generic_to_concrete_copy134 ; CHECK: %[[S1:[0-9]+]]:gpr32(s32) = G_ADD %{{[0-9]+}}, %{{[0-9]+}}135 ; CHECK-NEXT: %{{[0-9]+}}:gpr32 = ADDWrr %[[S1]](s32), %[[S1]](s32)136 bb.0:137 %0:_(s32) = COPY $w0138 %1:_(s32) = COPY $w1139 %2:_(s32) = G_ADD %0, %1140 %3:gpr32 = COPY %2(s32)141 %4:gpr32 = ADDWrr %3, %3142 $w0 = COPY %4143 RET_ReallyLR implicit $w0144...145---146name: concrete_to_generic_copy147legalized: true148regBankSelected: false149selected: false150body: |151 ; CHECK-LABEL: name: concrete_to_generic_copy152 ; CHECK: %[[S1:[0-9]+]]:gpr32(s32) = ADDWrr %{{[0-9]+}}, %{{[0-9]+}}153 ; CHECK-NEXT: %{{[0-9]+}}:_(s32) = G_ADD %[[S1]], %[[S1]]154 bb.0:155 %0:gpr32 = COPY $w0156 %1:gpr32 = COPY $w1157 %2:gpr32 = ADDWrr %0, %1158 %3:_(s32) = COPY %2159 %4:_(s32) = G_ADD %3, %3160 $w0 = COPY %4(s32)161 RET_ReallyLR implicit $w0162...163---164name: concrete165legalized: true166regBankSelected: false167selected: false168body: |169 ; CHECK-LABEL: name: concrete170 ; CHECK: %[[SC:[0-9]+]]:gpr32 = ADDWrr %{{[0-9]+}}, %{{[0-9]+}}171 ; CHECK-NEXT: %{{[0-9]+}}:gpr32 = ADDWrr %[[SC]], %[[SC]]172 bb.0:173 %0:gpr32 = COPY $w0174 %1:gpr32 = COPY $w1175 %2:gpr32 = ADDWrr %0, %1176 %3:gpr32 = COPY %2177 %4:gpr32 = ADDWrr %3, %3178 $w0 = COPY %4179 RET_ReallyLR implicit $w0180...181---182name: variadic_defs_unmerge_vector183legalized: true184regBankSelected: false185selected: false186body: |187 ; CHECK-LABEL: name: variadic_defs_unmerge_vector188 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0189 ; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)190 ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16)191 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)192 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)193 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)194 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]]195 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]]196 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]197 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)198 ; CHECK-NEXT: RET_ReallyLR implicit $w0199 bb.0:200 %0 :_(<4 x s16>) = COPY $d0201 %1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)202 %5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)203 %9 :_(s16), %10:_(s16), %11:_(s16), %12:_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)204 %13:_(s16), %14:_(s16), %15:_(s16), %16:_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)205 %17:_(s32) = G_ANYEXT %1 (s16)206 %18:_(s32) = G_ANYEXT %6 (s16)207 %19:_(s32) = G_ANYEXT %11(s16)208 %20:_(s32) = G_ANYEXT %16(s16)209 %21:_(s32) = G_ADD %17, %18210 %22:_(s32) = G_ADD %19, %20211 %23:_(s32) = G_ADD %21, %22212 $w0 = COPY %23(s32)213 RET_ReallyLR implicit $w0214...215---216name: variadic_defs_unmerge_scalar217legalized: true218regBankSelected: false219selected: false220body: |221 ; CHECK-LABEL: name: variadic_defs_unmerge_scalar222 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0223 ; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s64)224 ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16)225 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)226 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)227 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)228 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]]229 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]]230 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]231 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)232 ; CHECK-NEXT: RET_ReallyLR implicit $w0233 bb.0:234 %0 :_(s64) = COPY $d0235 %1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(s64)236 %5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(s64)237 %9 :_(s16), %10:_(s16), %11:_(s16), %12:_(s16) = G_UNMERGE_VALUES %0(s64)238 %13:_(s16), %14:_(s16), %15:_(s16), %16:_(s16) = G_UNMERGE_VALUES %0(s64)239 %17:_(s32) = G_ANYEXT %1 (s16)240 %18:_(s32) = G_ANYEXT %6 (s16)241 %19:_(s32) = G_ANYEXT %11(s16)242 %20:_(s32) = G_ANYEXT %16(s16)243 %21:_(s32) = G_ADD %17, %18244 %22:_(s32) = G_ADD %19, %20245 %23:_(s32) = G_ADD %21, %22246 $w0 = COPY %23(s32)247 RET_ReallyLR implicit $w0248...249---250name: variadic_defs_unmerge_scalar_asym251legalized: true252regBankSelected: false253selected: false254body: |255 ; CHECK-LABEL: name: variadic_defs_unmerge_scalar_asym256 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0257 ; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s64)258 ; CHECK-NEXT: [[UV01:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)259 ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16)260 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)261 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]]262 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV01]], [[UV23]]263 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]264 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)265 ; CHECK-NEXT: RET_ReallyLR implicit $w0266 bb.0:267 %0 :_(s64) = COPY $d0268 %1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(s64)269 %9 :_(s32), %10:_(s32) = G_UNMERGE_VALUES %0(s64)270 %5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(s64)271 %11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %0(s64)272 %17:_(s32) = G_ANYEXT %1 (s16)273 %18:_(s32) = G_ANYEXT %6 (s16)274 %21:_(s32) = G_ADD %17, %18275 %22:_(s32) = G_ADD %9, %12276 %23:_(s32) = G_ADD %21, %22277 $w0 = COPY %23(s32)278 RET_ReallyLR implicit $w0279...280---281name: variadic_defs_unmerge_vector_constraints_mix282legalized: true283regBankSelected: false284selected: false285body: |286 ; CHECK-LABEL: name: variadic_defs_unmerge_vector_constraints_mix287 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0288 ; CHECK-NEXT: [[UV0:%[0-9]+]]:gpr(s32), [[UV1:%[0-9]+]]:gpr(s32), [[UV2:%[0-9]+]]:gpr32(s32), [[UV3:%[0-9]+]]:gpr32(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)289 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[UV0]], [[UV1]]290 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr32(s32) = ADDWrr [[UV2]](s32), [[UV3]](s32)291 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]292 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)293 ; CHECK-NEXT: RET_ReallyLR implicit $w0294 bb.0:295 %0 :_(<4 x s32>) = COPY $q0296 %1 :_(s32), %2 : _ (s32), %3 :_(s32), %4 : _ (s32) = G_UNMERGE_VALUES %0(<4 x s32>)297 %5 :_(s32), %6 :gpr(s32), %7 :_(s32), %8 : _ (s32) = G_UNMERGE_VALUES %0(<4 x s32>)298 %9 :_(s32), %10: _ (s32), %11:_(s32), %12: _ (s32) = G_UNMERGE_VALUES %0(<4 x s32>)299 %13:_(s32), %14: _ (s32), %15:_(s32), %16:gpr32(s32) = G_UNMERGE_VALUES %0(<4 x s32>)300 %21:gpr(s32) = COPY %1(s32)301 %17:_(s32) = G_ADD %21, %6302 %18:gpr32 = COPY %11(s32)303 %19:gpr32(s32) = ADDWrr %18, %16304 %20:_(s32) = G_ADD %17, %19305 $w0 = COPY %20(s32)306 RET_ReallyLR implicit $w0307...308