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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s3--- |4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5 target triple = "aarch64"6 7 define i32 @ld_zext_i24(ptr %ptr, ptr %ptr2) {8 %load = load i24, ptr %ptr, align 19 %ext = zext i24 %load to i3210 ret i32 %ext11 }12 13...14---15name: ld_zext_i2416alignment: 417tracksRegLiveness: true18machineFunctionInfo: {}19body: |20 bb.1 (%ir-block.0):21 liveins: $x0, $x122 23 ; CHECK-LABEL: name: ld_zext_i2424 ; CHECK: liveins: $x0, $x125 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x027 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s24) = G_LOAD [[COPY]](p0) :: (load (s24) from %ir.ptr, align 1)28 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s24)29 ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)30 ; CHECK-NEXT: RET_ReallyLR implicit $w031 %0:_(p0) = COPY $x032 %1:_(p0) = COPY $x133 %2:_(s24) = G_LOAD %0(p0) :: (load (s24) from %ir.ptr, align 1)34 %3:_(s32) = G_ZEXT %2(s24)35 $w0 = COPY %3(s32)36 RET_ReallyLR implicit $w037 38...39