267 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3#4# Verify that we can fold G_AND into G_BRCOND when all of the following hold:5# 1. We have a ne/eq G_ICMP feeding into the G_BRCOND6# 2. The G_ICMP is being compared against 07# 3. One of the operands of the G_AND is a power of 28#9# If all of these hold, we should produce a tbnz or a tbz.10...11---12name: tbnzx_and13alignment: 414legalized: true15regBankSelected: true16body: |17 ; CHECK-LABEL: name: tbnzx_and18 ; CHECK: bb.0:19 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)20 ; CHECK-NEXT: liveins: $x021 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x023 ; CHECK-NEXT: TBNZX [[COPY]], 33, %bb.124 ; CHECK-NEXT: B %bb.025 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: bb.1:27 ; CHECK-NEXT: RET_ReallyLR28 bb.0:29 successors: %bb.0, %bb.130 liveins: $x031 %0:gpr(s64) = COPY $x032 %1:gpr(s64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX33 %3:gpr(s64) = G_CONSTANT i64 034 %2:gpr(s64) = G_AND %0, %135 %5:gpr(s32) = G_ICMP intpred(ne), %2(s64), %336 G_BRCOND %5, %bb.137 G_BR %bb.038 bb.1:39 RET_ReallyLR40 41...42---43name: tbzx_and44alignment: 445legalized: true46regBankSelected: true47tracksRegLiveness: true48body: |49 ; CHECK-LABEL: name: tbzx_and50 ; CHECK: bb.0:51 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)52 ; CHECK-NEXT: liveins: $x053 ; CHECK-NEXT: {{ $}}54 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x055 ; CHECK-NEXT: TBZX [[COPY]], 33, %bb.156 ; CHECK-NEXT: B %bb.057 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: bb.1:59 ; CHECK-NEXT: RET_ReallyLR60 bb.0:61 successors: %bb.0, %bb.162 liveins: $x063 %0:gpr(s64) = COPY $x064 %1:gpr(s64) = G_CONSTANT i64 8589934592 ; Bit number 33 => TBNZX65 %3:gpr(s64) = G_CONSTANT i64 066 %2:gpr(s64) = G_AND %0, %167 %5:gpr(s32) = G_ICMP intpred(eq), %2(s64), %368 G_BRCOND %5, %bb.169 G_BR %bb.070 bb.1:71 RET_ReallyLR72 73...74---75name: tbnzw_and76alignment: 477legalized: true78regBankSelected: true79tracksRegLiveness: true80body: |81 ; CHECK-LABEL: name: tbnzw_and82 ; CHECK: bb.0:83 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)84 ; CHECK-NEXT: liveins: $w085 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w087 ; CHECK-NEXT: TBNZW [[COPY]], 0, %bb.188 ; CHECK-NEXT: B %bb.089 ; CHECK-NEXT: {{ $}}90 ; CHECK-NEXT: bb.1:91 ; CHECK-NEXT: RET_ReallyLR92 bb.0:93 successors: %bb.0, %bb.194 liveins: $w095 %0:gpr(s32) = COPY $w096 %1:gpr(s32) = G_CONSTANT i32 197 %3:gpr(s32) = G_CONSTANT i32 098 %2:gpr(s32) = G_AND %0, %199 %5:gpr(s32) = G_ICMP intpred(ne), %2(s32), %3100 G_BRCOND %5, %bb.1101 G_BR %bb.0102 bb.1:103 RET_ReallyLR104 105...106---107name: tbzw_and108alignment: 4109legalized: true110regBankSelected: true111tracksRegLiveness: true112body: |113 ; CHECK-LABEL: name: tbzw_and114 ; CHECK: bb.0:115 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)116 ; CHECK-NEXT: liveins: $w0117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0119 ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.1120 ; CHECK-NEXT: B %bb.0121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: bb.1:123 ; CHECK-NEXT: RET_ReallyLR124 bb.0:125 successors: %bb.0, %bb.1126 liveins: $w0127 %0:gpr(s32) = COPY $w0128 %1:gpr(s32) = G_CONSTANT i32 1129 %3:gpr(s32) = G_CONSTANT i32 0130 %2:gpr(s32) = G_AND %0, %1131 %5:gpr(s32) = G_ICMP intpred(eq), %2(s32), %3132 G_BRCOND %5, %bb.1133 G_BR %bb.0134 bb.1:135 RET_ReallyLR136 137...138---139name: dont_fold_and_lt140alignment: 4141legalized: true142regBankSelected: true143tracksRegLiveness: true144body: |145 ; CHECK-LABEL: name: dont_fold_and_lt146 ; CHECK: bb.0:147 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)148 ; CHECK-NEXT: liveins: $w0149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0151 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv152 ; CHECK-NEXT: Bcc 4, %bb.1, implicit $nzcv153 ; CHECK-NEXT: B %bb.0154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: bb.1:156 ; CHECK-NEXT: RET_ReallyLR157 bb.0:158 successors: %bb.0, %bb.1159 liveins: $w0160 %0:gpr(s32) = COPY $w0161 %1:gpr(s32) = G_CONSTANT i32 1162 %3:gpr(s32) = G_CONSTANT i32 0163 %2:gpr(s32) = G_AND %0, %1164 %5:gpr(s32) = G_ICMP intpred(slt), %2(s32), %3165 G_BRCOND %5, %bb.1166 G_BR %bb.0167 bb.1:168 RET_ReallyLR169 170...171---172name: dont_fold_and_gt173alignment: 4174legalized: true175regBankSelected: true176tracksRegLiveness: true177body: |178 ; CHECK-LABEL: name: dont_fold_and_gt179 ; CHECK: bb.0:180 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)181 ; CHECK-NEXT: liveins: $w0182 ; CHECK-NEXT: {{ $}}183 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0184 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv185 ; CHECK-NEXT: Bcc 12, %bb.1, implicit $nzcv186 ; CHECK-NEXT: B %bb.0187 ; CHECK-NEXT: {{ $}}188 ; CHECK-NEXT: bb.1:189 ; CHECK-NEXT: RET_ReallyLR190 bb.0:191 successors: %bb.0, %bb.1192 liveins: $w0193 %0:gpr(s32) = COPY $w0194 %1:gpr(s32) = G_CONSTANT i32 1195 %3:gpr(s32) = G_CONSTANT i32 0196 %2:gpr(s32) = G_AND %0, %1197 %5:gpr(s32) = G_ICMP intpred(sgt), %2(s32), %3198 G_BRCOND %5, %bb.1199 G_BR %bb.0200 bb.1:201 RET_ReallyLR202 203...204---205name: dont_fold_and_not_power_of_2206alignment: 4207legalized: true208regBankSelected: true209body: |210 ; CHECK-LABEL: name: dont_fold_and_not_power_of_2211 ; CHECK: bb.0:212 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)213 ; CHECK-NEXT: liveins: $x0214 ; CHECK-NEXT: {{ $}}215 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0216 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[COPY]], 4098217 ; CHECK-NEXT: CBNZX [[ANDXri]], %bb.1218 ; CHECK-NEXT: B %bb.0219 ; CHECK-NEXT: {{ $}}220 ; CHECK-NEXT: bb.1:221 ; CHECK-NEXT: RET_ReallyLR222 bb.0:223 successors: %bb.0, %bb.1224 liveins: $x0225 %0:gpr(s64) = COPY $x0226 %1:gpr(s64) = G_CONSTANT i64 7227 %3:gpr(s64) = G_CONSTANT i64 0228 %2:gpr(s64) = G_AND %0, %1229 %5:gpr(s32) = G_ICMP intpred(ne), %2(s64), %3230 G_BRCOND %5, %bb.1231 G_BR %bb.0232 bb.1:233 RET_ReallyLR234 235...236---237name: dont_fold_cmp_not_0238alignment: 4239legalized: true240regBankSelected: true241body: |242 ; CHECK-LABEL: name: dont_fold_cmp_not_0243 ; CHECK: bb.0:244 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)245 ; CHECK-NEXT: liveins: $x0246 ; CHECK-NEXT: {{ $}}247 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0248 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 8064249 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[ANDXri]], 4, 0, implicit-def $nzcv250 ; CHECK-NEXT: Bcc 1, %bb.1, implicit $nzcv251 ; CHECK-NEXT: B %bb.0252 ; CHECK-NEXT: {{ $}}253 ; CHECK-NEXT: bb.1:254 ; CHECK-NEXT: RET_ReallyLR255 bb.0:256 successors: %bb.0, %bb.1257 liveins: $x0258 %0:gpr(s64) = COPY $x0259 %1:gpr(s64) = G_CONSTANT i64 4260 %3:gpr(s64) = G_CONSTANT i64 4261 %2:gpr(s64) = G_AND %0, %1262 %5:gpr(s32) = G_ICMP intpred(ne), %2(s64), %3263 G_BRCOND %5, %bb.1264 G_BR %bb.0265 bb.1:266 RET_ReallyLR267