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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s3#4# Verify folding operations into G_ICMP.5#6# E.g cmn/adds folding:7#8# x = G_SUB 0, y9# G_ICMP intpred(something_safe) z, x10#11# Folds to:12# adds z, y13#14# Where "something_safe" is ne or eq.15#16# ands/tst folding:17#18# z = G_AND x, y19# G_ICMP z, 020#21# Folds to:22#23# tst x, y24#25# When we have signed comparisons.26#27# Tests whose names start with cmn_ should use ADDS for the G_ICMP. Tests whose28# names start with no_cmn should use SUBS. Similarly, tests whose names start29# with TST should use ANDS for the G_ICMP.30#31 32...33---34name: cmn_s32_rhs35alignment: 436legalized: true37regBankSelected: true38tracksRegLiveness: true39body: |40 bb.0:41 liveins: $w0, $w142 43 ; CHECK-LABEL: name: cmn_s32_rhs44 ; CHECK: liveins: $w0, $w145 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w047 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w148 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr49 ; CHECK-NEXT: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv50 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv51 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]52 ; CHECK-NEXT: RET_ReallyLR implicit $w053 %0:gpr(s32) = COPY $w054 %1:gpr(s32) = COPY $w155 %2:gpr(s32) = G_CONSTANT i32 056 %6:gpr(s32) = G_CONSTANT i32 157 %3:gpr(s32) = G_SUB %2, %158 %7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %359 %5:gpr(s32) = G_SELECT %7, %6, %260 $w0 = COPY %5(s32)61 RET_ReallyLR implicit $w062 63...64---65name: cmn_s32_lhs66alignment: 467legalized: true68regBankSelected: true69tracksRegLiveness: true70body: |71 bb.0:72 liveins: $w0, $w173 74 ; CHECK-LABEL: name: cmn_s32_lhs75 ; CHECK: liveins: $w0, $w176 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w078 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w179 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr80 ; CHECK-NEXT: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv81 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv82 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]83 ; CHECK-NEXT: RET_ReallyLR implicit $w084 %0:gpr(s32) = COPY $w085 %1:gpr(s32) = COPY $w186 %2:gpr(s32) = G_CONSTANT i32 087 %6:gpr(s32) = G_CONSTANT i32 188 %3:gpr(s32) = G_SUB %2, %089 %7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %190 %5:gpr(s32) = G_SELECT %7, %6, %291 $w0 = COPY %5(s32)92 RET_ReallyLR implicit $w093 94...95---96name: no_cmn_s32_rhs97alignment: 498legalized: true99regBankSelected: true100tracksRegLiveness: true101body: |102 bb.0:103 liveins: $w0, $w1104 105 ; CHECK-LABEL: name: no_cmn_s32_rhs106 ; CHECK: liveins: $w0, $w1107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0109 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1110 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr111 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def dead $nzcv112 ; CHECK-NEXT: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv113 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv114 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]115 ; CHECK-NEXT: RET_ReallyLR implicit $w0116 %0:gpr(s32) = COPY $w0117 %1:gpr(s32) = COPY $w1118 %2:gpr(s32) = G_CONSTANT i32 0119 %6:gpr(s32) = G_CONSTANT i32 1120 %3:gpr(s32) = G_SUB %2, %1121 %7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3122 %5:gpr(s32) = G_SELECT %7, %6, %2123 $w0 = COPY %5(s32)124 RET_ReallyLR implicit $w0125 126...127---128name: no_cmn_s32_lhs129alignment: 4130legalized: true131regBankSelected: true132tracksRegLiveness: true133body: |134 bb.0:135 liveins: $w0, $w1136 137 ; CHECK-LABEL: name: no_cmn_s32_lhs138 ; CHECK: liveins: $w0, $w1139 ; CHECK-NEXT: {{ $}}140 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0141 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1142 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr143 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY]], implicit-def dead $nzcv144 ; CHECK-NEXT: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv145 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv146 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]147 ; CHECK-NEXT: RET_ReallyLR implicit $w0148 %0:gpr(s32) = COPY $w0149 %1:gpr(s32) = COPY $w1150 %2:gpr(s32) = G_CONSTANT i32 0151 %6:gpr(s32) = G_CONSTANT i32 1152 %3:gpr(s32) = G_SUB %2, %0153 %7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1154 %5:gpr(s32) = G_SELECT %7, %6, %2155 $w0 = COPY %5(s32)156 RET_ReallyLR implicit $w0157 158...159---160name: cmn_s64_rhs161alignment: 4162legalized: true163regBankSelected: true164tracksRegLiveness: true165body: |166 bb.0:167 liveins: $x0, $x1168 169 ; CHECK-LABEL: name: cmn_s64_rhs170 ; CHECK: liveins: $x0, $x1171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0173 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1174 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr175 ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv176 ; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv177 ; CHECK-NEXT: $x0 = COPY [[CSINCXr]]178 ; CHECK-NEXT: RET_ReallyLR implicit $x0179 %0:gpr(s64) = COPY $x0180 %1:gpr(s64) = COPY $x1181 %2:gpr(s64) = G_CONSTANT i64 0182 %6:gpr(s64) = G_CONSTANT i64 1183 %3:gpr(s64) = G_SUB %2, %1184 %7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3185 %5:gpr(s64) = G_SELECT %7, %6, %2186 $x0 = COPY %5(s64)187 RET_ReallyLR implicit $x0188 189...190---191name: cmn_s64_lhs192alignment: 4193legalized: true194regBankSelected: true195tracksRegLiveness: true196body: |197 bb.0:198 liveins: $x0, $x1199 200 ; CHECK-LABEL: name: cmn_s64_lhs201 ; CHECK: liveins: $x0, $x1202 ; CHECK-NEXT: {{ $}}203 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0204 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1205 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr206 ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv207 ; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv208 ; CHECK-NEXT: $x0 = COPY [[CSINCXr]]209 ; CHECK-NEXT: RET_ReallyLR implicit $x0210 %0:gpr(s64) = COPY $x0211 %1:gpr(s64) = COPY $x1212 %2:gpr(s64) = G_CONSTANT i64 0213 %6:gpr(s64) = G_CONSTANT i64 1214 %3:gpr(s64) = G_SUB %2, %0215 %7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1216 %5:gpr(s64) = G_SELECT %7, %6, %2217 $x0 = COPY %5(s64)218 RET_ReallyLR implicit $x0219 220...221---222name: no_cmn_s64_rhs223alignment: 4224legalized: true225regBankSelected: true226tracksRegLiveness: true227body: |228 bb.0:229 liveins: $x0, $x1230 231 ; CHECK-LABEL: name: no_cmn_s64_rhs232 ; CHECK: liveins: $x0, $x1233 ; CHECK-NEXT: {{ $}}234 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0235 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1236 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr237 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY1]], implicit-def dead $nzcv238 ; CHECK-NEXT: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv239 ; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv240 ; CHECK-NEXT: $x0 = COPY [[CSINCXr]]241 ; CHECK-NEXT: RET_ReallyLR implicit $x0242 %0:gpr(s64) = COPY $x0243 %1:gpr(s64) = COPY $x1244 %2:gpr(s64) = G_CONSTANT i64 0245 %6:gpr(s64) = G_CONSTANT i64 1246 %3:gpr(s64) = G_SUB %2, %1247 %7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3248 %5:gpr(s64) = G_SELECT %7, %6, %2249 $x0 = COPY %5(s64)250 RET_ReallyLR implicit $x0251 252...253---254name: no_cmn_s64_lhs255alignment: 4256legalized: true257regBankSelected: true258tracksRegLiveness: true259body: |260 bb.0:261 liveins: $x0, $x1262 263 ; CHECK-LABEL: name: no_cmn_s64_lhs264 ; CHECK: liveins: $x0, $x1265 ; CHECK-NEXT: {{ $}}266 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0267 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1268 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr269 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY]], implicit-def dead $nzcv270 ; CHECK-NEXT: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv271 ; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv272 ; CHECK-NEXT: $x0 = COPY [[CSINCXr]]273 ; CHECK-NEXT: RET_ReallyLR implicit $x0274 %0:gpr(s64) = COPY $x0275 %1:gpr(s64) = COPY $x1276 %2:gpr(s64) = G_CONSTANT i64 0277 %6:gpr(s64) = G_CONSTANT i64 1278 %3:gpr(s64) = G_SUB %2, %0279 %7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1280 %5:gpr(s64) = G_SELECT %7, %6, %2281 $x0 = COPY %5(s64)282 RET_ReallyLR implicit $x0283 284...285---286name: tst_s32287alignment: 4288legalized: true289regBankSelected: true290tracksRegLiveness: true291body: |292 bb.0:293 liveins: $w0, $w1294 ; CHECK-LABEL: name: tst_s32295 ; CHECK: liveins: $w0, $w1296 ; CHECK-NEXT: {{ $}}297 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1298 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr299 ; CHECK-NEXT: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv300 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 1, implicit $nzcv301 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]302 ; CHECK-NEXT: RET_ReallyLR implicit $w0303 %0:gpr(s32) = COPY $w0304 %1:gpr(s32) = COPY $w1305 %2:gpr(s32) = G_CONSTANT i32 0306 %6:gpr(s32) = G_CONSTANT i32 1307 %3:gpr(s32) = G_AND %2, %1308 %8:gpr(s32) = G_CONSTANT i32 0309 %7:gpr(s32) = G_ICMP intpred(eq), %3(s32), %8310 %5:gpr(s32) = G_SELECT %7, %6, %2311 $w0 = COPY %5(s32)312 RET_ReallyLR implicit $w0313 314...315---316name: tst_s64317alignment: 4318legalized: true319regBankSelected: true320tracksRegLiveness: true321body: |322 bb.0:323 liveins: $x0, $x1324 ; CHECK-LABEL: name: tst_s64325 ; CHECK: liveins: $x0, $x1326 ; CHECK-NEXT: {{ $}}327 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1328 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr329 ; CHECK-NEXT: [[ANDSXrr:%[0-9]+]]:gpr64 = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv330 ; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY1]], $xzr, 1, implicit $nzcv331 ; CHECK-NEXT: $x0 = COPY [[CSINCXr]]332 ; CHECK-NEXT: RET_ReallyLR implicit $x0333 %0:gpr(s64) = COPY $x0334 %1:gpr(s64) = COPY $x1335 %2:gpr(s64) = G_CONSTANT i64 0336 %6:gpr(s64) = G_CONSTANT i64 1337 %3:gpr(s64) = G_AND %2, %1338 %8:gpr(s64) = G_CONSTANT i64 0339 %7:gpr(s32) = G_ICMP intpred(eq), %3(s64), %8340 %5:gpr(s64) = G_SELECT %7, %6, %2341 $x0 = COPY %5(s64)342 RET_ReallyLR implicit $x0343 344...345---346name: no_tst_unsigned_compare347alignment: 4348legalized: true349regBankSelected: true350tracksRegLiveness: true351body: |352 bb.0:353 liveins: $w0, $w1354 ; CHECK-LABEL: name: no_tst_unsigned_compare355 ; CHECK: liveins: $w0, $w1356 ; CHECK-NEXT: {{ $}}357 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1358 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr359 ; CHECK-NEXT: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]360 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv361 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv362 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]363 ; CHECK-NEXT: RET_ReallyLR implicit $w0364 %0:gpr(s32) = COPY $w0365 %1:gpr(s32) = COPY $w1366 %2:gpr(s32) = G_CONSTANT i32 0367 %6:gpr(s32) = G_CONSTANT i32 1368 %3:gpr(s32) = G_AND %2, %1369 %8:gpr(s32) = G_CONSTANT i32 0370 %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8371 %5:gpr(s32) = G_SELECT %7, %6, %2372 $w0 = COPY %5(s32)373 RET_ReallyLR implicit $w0374 375...376---377name: no_tst_nonzero378alignment: 4379legalized: true380regBankSelected: true381tracksRegLiveness: true382body: |383 bb.0:384 liveins: $w0, $w1385 ; CHECK-LABEL: name: no_tst_nonzero386 ; CHECK: liveins: $w0, $w1387 ; CHECK-NEXT: {{ $}}388 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1389 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr390 ; CHECK-NEXT: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]391 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv392 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv393 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]394 ; CHECK-NEXT: RET_ReallyLR implicit $w0395 %0:gpr(s32) = COPY $w0396 %1:gpr(s32) = COPY $w1397 %2:gpr(s32) = G_CONSTANT i32 0398 %6:gpr(s32) = G_CONSTANT i32 1399 %3:gpr(s32) = G_AND %2, %1400 %8:gpr(s32) = G_CONSTANT i32 42401 %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8402 %5:gpr(s32) = G_SELECT %7, %6, %2403 $w0 = COPY %5(s32)404 RET_ReallyLR implicit $w0405 406...407---408name: imm_tst409alignment: 4410legalized: true411regBankSelected: true412tracksRegLiveness: true413body: |414 bb.0:415 liveins: $w0, $w1416 ; CHECK-LABEL: name: imm_tst417 ; CHECK: liveins: $w0, $w1418 ; CHECK-NEXT: {{ $}}419 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1420 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 1, implicit-def $nzcv421 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv422 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]423 ; CHECK-NEXT: RET_ReallyLR implicit $w0424 %0:gpr(s32) = COPY $w0425 %1:gpr(s32) = COPY $w1426 %2:gpr(s32) = G_CONSTANT i32 0427 %3:gpr(s32) = G_CONSTANT i32 1428 429 ; This can be represented as a logical immediate, so we can pull it into430 ; the ANDS. We should get ANDSWri.431 %4:gpr(s32) = G_CONSTANT i32 3432 433 %5:gpr(s32) = G_AND %1, %4434 %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2435 $w0 = COPY %6(s32)436 RET_ReallyLR implicit $w0437 438 439...440---441name: no_imm_tst_not_logical_imm442alignment: 4443legalized: true444regBankSelected: true445tracksRegLiveness: true446body: |447 bb.0:448 liveins: $w0, $w1449 ; CHECK-LABEL: name: no_imm_tst_not_logical_imm450 ; CHECK: liveins: $w0, $w1451 ; CHECK-NEXT: {{ $}}452 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1453 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1454 ; CHECK-NEXT: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv455 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv456 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]457 ; CHECK-NEXT: RET_ReallyLR implicit $w0458 %0:gpr(s32) = COPY $w0459 %1:gpr(s32) = COPY $w1460 %2:gpr(s32) = G_CONSTANT i32 0461 %3:gpr(s32) = G_CONSTANT i32 1462 463 ; This immediate can't be represented as a logical immediate. We shouldn't464 ; select ANDSWri.465 %4:gpr(s32) = G_CONSTANT i32 -1466 467 %5:gpr(s32) = G_AND %1, %4468 %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2469 $w0 = COPY %6(s32)470 RET_ReallyLR implicit $w0471 472...473---474name: test_physreg_copy475alignment: 4476legalized: true477regBankSelected: true478tracksRegLiveness: true479body: |480 bb.0:481 liveins: $x0, $x1482 ; CHECK-LABEL: name: test_physreg_copy483 ; CHECK: liveins: $x0, $x1484 ; CHECK-NEXT: {{ $}}485 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0486 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1487 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv488 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv489 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]490 ; CHECK-NEXT: RET_ReallyLR implicit $x0491 %0:gpr(s64) = COPY $x0492 %1:gpr(s64) = COPY $x1493 ; When we find the defs of the LHS and RHS of the compare, we walk over494 ; copies. Make sure that we don't crash when we hit a copy from a physical495 ; register.496 %7:gpr(s32) = G_ICMP intpred(eq), %0, %1497 $w0 = COPY %7(s32)498 RET_ReallyLR implicit $x0499 500...501---502name: tst_fold_shift_s64503alignment: 4504legalized: true505regBankSelected: true506tracksRegLiveness: true507body: |508 bb.0:509 liveins: $x0, $x1510 ; We should fold the G_SHL into the ANDS to get ANDSXrs.511 ; CHECK-LABEL: name: tst_fold_shift_s64512 ; CHECK: liveins: $x0, $x1513 ; CHECK-NEXT: {{ $}}514 ; CHECK-NEXT: %copy:gpr64 = COPY $x1515 ; CHECK-NEXT: %zero:gpr64 = COPY $xzr516 ; CHECK-NEXT: [[ANDSXrs:%[0-9]+]]:gpr64 = ANDSXrs %zero, %copy, 16, implicit-def $nzcv517 ; CHECK-NEXT: %select:gpr64 = CSINCXr %zero, $xzr, 1, implicit $nzcv518 ; CHECK-NEXT: $x0 = COPY %select519 ; CHECK-NEXT: RET_ReallyLR implicit $x0520 %copy:gpr(s64) = COPY $x1521 %zero:gpr(s64) = G_CONSTANT i64 0522 %one:gpr(s64) = G_CONSTANT i64 1523 %cst:gpr(s64) = G_CONSTANT i64 16524 %shift:gpr(s64) = G_SHL %copy(s64), %cst(s64)525 %and:gpr(s64) = G_AND %zero, %shift526 %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero527 %select:gpr(s64) = G_SELECT %cmp, %one, %zero528 $x0 = COPY %select(s64)529 RET_ReallyLR implicit $x0530 531...532---533name: tst_fold_shift_s32534alignment: 4535legalized: true536regBankSelected: true537tracksRegLiveness: true538body: |539 bb.0:540 liveins: $w0, $w1541 ; We should fold the G_SHL into the ANDS to get ANDSWrs.542 ; CHECK-LABEL: name: tst_fold_shift_s32543 ; CHECK: liveins: $w0, $w1544 ; CHECK-NEXT: {{ $}}545 ; CHECK-NEXT: %copy:gpr32 = COPY $w1546 ; CHECK-NEXT: %zero:gpr32 = COPY $wzr547 ; CHECK-NEXT: [[ANDSWrs:%[0-9]+]]:gpr32 = ANDSWrs %zero, %copy, 16, implicit-def $nzcv548 ; CHECK-NEXT: %select:gpr32 = CSINCWr %zero, $wzr, 1, implicit $nzcv549 ; CHECK-NEXT: $w0 = COPY %select550 ; CHECK-NEXT: RET_ReallyLR implicit $w0551 %copy:gpr(s32) = COPY $w1552 %zero:gpr(s32) = G_CONSTANT i32 0553 %one:gpr(s32) = G_CONSTANT i32 1554 %cst:gpr(s32) = G_CONSTANT i32 16555 %shift:gpr(s32) = G_SHL %copy(s32), %cst(s32)556 %and:gpr(s32) = G_AND %zero, %shift557 %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s32), %zero558 %select:gpr(s32) = G_SELECT %cmp, %one, %zero559 $w0 = COPY %select(s32)560 RET_ReallyLR implicit $w0561 562...563---564name: cmn_s32_neg_imm565alignment: 4566legalized: true567regBankSelected: true568tracksRegLiveness: true569body: |570 bb.0:571 liveins: $w0, $w1572 573 ; CHECK-LABEL: name: cmn_s32_neg_imm574 ; CHECK: liveins: $w0, $w1575 ; CHECK-NEXT: {{ $}}576 ; CHECK-NEXT: %reg0:gpr32sp = COPY $w0577 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg0, 1, 0, implicit-def $nzcv578 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv579 ; CHECK-NEXT: $w0 = COPY %cmp580 ; CHECK-NEXT: RET_ReallyLR implicit $w0581 %reg0:gpr(s32) = COPY $w0582 %negative_one:gpr(s32) = G_CONSTANT i32 -1583 %zero:gpr(s32) = G_CONSTANT i32 0584 %sub:gpr(s32) = G_SUB %zero, %negative_one585 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %sub586 $w0 = COPY %cmp(s32)587 RET_ReallyLR implicit $w0588 589...590---591name: cmn_arith_extended_shl592alignment: 4593legalized: true594regBankSelected: true595tracksRegLiveness: true596body: |597 bb.0:598 liveins: $w0, $x0, $x1599 ; We should be able to fold away the extend + shift and select ADDSXrx.600 601 ; CHECK-LABEL: name: cmn_arith_extended_shl602 ; CHECK: liveins: $w0, $x0, $x1603 ; CHECK-NEXT: {{ $}}604 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0605 ; CHECK-NEXT: %reg1:gpr32 = COPY $w0606 ; CHECK-NEXT: [[ADDSXrx:%[0-9]+]]:gpr64 = ADDSXrx %reg0, %reg1, 50, implicit-def $nzcv607 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv608 ; CHECK-NEXT: $w0 = COPY %cmp609 ; CHECK-NEXT: RET_ReallyLR implicit $w0610 %reg0:gpr(s64) = COPY $x0611 %zero:gpr(s64) = G_CONSTANT i64 0612 %sub:gpr(s64) = G_SUB %zero, %reg0613 614 %reg1:gpr(s32) = COPY $w0615 %ext:gpr(s64) = G_SEXT %reg1(s32)616 %cst:gpr(s64) = G_CONSTANT i64 2617 %shift:gpr(s64) = G_SHL %ext, %cst(s64)618 619 %cmp:gpr(s32) = G_ICMP intpred(ne), %sub(s64), %shift620 $w0 = COPY %cmp(s32)621 RET_ReallyLR implicit $w0622