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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3#4# Verify that we can fold shifts into G_ICMP variants.5#6# Because these are selected as a SUBS, we can fold a shift into the addressing7# mode in the same way.8#9# We should not have shifts in any of the compares below. These should be10# folded into the SUBSWrs instruction.11 12...13---14name: eq_shl15legalized: true16regBankSelected: true17tracksRegLiveness: true18body: |19 bb.0:20 liveins: $w0, $w121 22 ; CHECK-LABEL: name: eq_shl23 ; CHECK: liveins: $w0, $w124 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: %copy0:gpr32 = COPY $w026 ; CHECK-NEXT: %copy1:gpr32 = COPY $w127 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv28 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv29 ; CHECK-NEXT: $w0 = COPY %cmp30 ; CHECK-NEXT: RET_ReallyLR implicit $w031 %copy0:gpr(s32) = COPY $w032 %copy1:gpr(s32) = COPY $w133 %three:gpr(s32) = G_CONSTANT i32 334 %shift:gpr(s32) = G_SHL %copy0, %three(s32)35 %cmp:gpr(s32) = G_ICMP intpred(eq), %copy1(s32), %shift36 $w0 = COPY %cmp(s32)37 RET_ReallyLR implicit $w038 39...40---41name: eq_ashr42legalized: true43regBankSelected: true44tracksRegLiveness: true45body: |46 bb.0:47 liveins: $w0, $w148 49 ; CHECK-LABEL: name: eq_ashr50 ; CHECK: liveins: $w0, $w151 ; CHECK-NEXT: {{ $}}52 ; CHECK-NEXT: %copy0:gpr32 = COPY $w053 ; CHECK-NEXT: %copy1:gpr32 = COPY $w154 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv55 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv56 ; CHECK-NEXT: $w0 = COPY %cmp57 ; CHECK-NEXT: RET_ReallyLR implicit $w058 %copy0:gpr(s32) = COPY $w059 %copy1:gpr(s32) = COPY $w160 %three:gpr(s32) = G_CONSTANT i32 361 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)62 %cmp:gpr(s32) = G_ICMP intpred(eq), %copy1(s32), %shift63 $w0 = COPY %cmp(s32)64 RET_ReallyLR implicit $w065 66...67---68name: eq_lshr69legalized: true70regBankSelected: true71tracksRegLiveness: true72body: |73 bb.0:74 liveins: $w0, $w175 76 ; CHECK-LABEL: name: eq_lshr77 ; CHECK: liveins: $w0, $w178 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: %copy0:gpr32 = COPY $w080 ; CHECK-NEXT: %copy1:gpr32 = COPY $w181 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv82 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv83 ; CHECK-NEXT: $w0 = COPY %cmp84 ; CHECK-NEXT: RET_ReallyLR implicit $w085 %copy0:gpr(s32) = COPY $w086 %copy1:gpr(s32) = COPY $w187 %three:gpr(s32) = G_CONSTANT i32 388 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)89 %cmp:gpr(s32) = G_ICMP intpred(eq), %copy1(s32), %shift90 $w0 = COPY %cmp(s32)91 RET_ReallyLR implicit $w092 93...94---95name: ne_shl96legalized: true97regBankSelected: true98tracksRegLiveness: true99body: |100 bb.0:101 liveins: $w0, $w1102 103 ; CHECK-LABEL: name: ne_shl104 ; CHECK: liveins: $w0, $w1105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0107 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1108 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv109 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv110 ; CHECK-NEXT: $w0 = COPY %cmp111 ; CHECK-NEXT: RET_ReallyLR implicit $w0112 %copy0:gpr(s32) = COPY $w0113 %copy1:gpr(s32) = COPY $w1114 %three:gpr(s32) = G_CONSTANT i32 3115 %shift:gpr(s32) = G_SHL %copy0, %three(s32)116 %cmp:gpr(s32) = G_ICMP intpred(ne), %copy1(s32), %shift117 $w0 = COPY %cmp(s32)118 RET_ReallyLR implicit $w0119 120...121---122name: ne_ashr123legalized: true124regBankSelected: true125tracksRegLiveness: true126body: |127 bb.0:128 liveins: $w0, $w1129 130 ; CHECK-LABEL: name: ne_ashr131 ; CHECK: liveins: $w0, $w1132 ; CHECK-NEXT: {{ $}}133 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0134 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1135 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv136 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv137 ; CHECK-NEXT: $w0 = COPY %cmp138 ; CHECK-NEXT: RET_ReallyLR implicit $w0139 %copy0:gpr(s32) = COPY $w0140 %copy1:gpr(s32) = COPY $w1141 %three:gpr(s32) = G_CONSTANT i32 3142 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)143 %cmp:gpr(s32) = G_ICMP intpred(ne), %copy1(s32), %shift144 $w0 = COPY %cmp(s32)145 RET_ReallyLR implicit $w0146 147...148---149name: ne_lshr150legalized: true151regBankSelected: true152tracksRegLiveness: true153body: |154 bb.0:155 liveins: $w0, $w1156 157 ; CHECK-LABEL: name: ne_lshr158 ; CHECK: liveins: $w0, $w1159 ; CHECK-NEXT: {{ $}}160 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0161 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1162 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv163 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv164 ; CHECK-NEXT: $w0 = COPY %cmp165 ; CHECK-NEXT: RET_ReallyLR implicit $w0166 %copy0:gpr(s32) = COPY $w0167 %copy1:gpr(s32) = COPY $w1168 %three:gpr(s32) = G_CONSTANT i32 3169 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)170 %cmp:gpr(s32) = G_ICMP intpred(ne), %copy1(s32), %shift171 $w0 = COPY %cmp(s32)172 RET_ReallyLR implicit $w0173 174...175---176name: ult_shl177legalized: true178regBankSelected: true179tracksRegLiveness: true180body: |181 bb.0:182 liveins: $w0, $w1183 184 ; CHECK-LABEL: name: ult_shl185 ; CHECK: liveins: $w0, $w1186 ; CHECK-NEXT: {{ $}}187 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0188 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1189 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv190 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv191 ; CHECK-NEXT: $w0 = COPY %cmp192 ; CHECK-NEXT: RET_ReallyLR implicit $w0193 %copy0:gpr(s32) = COPY $w0194 %copy1:gpr(s32) = COPY $w1195 %three:gpr(s32) = G_CONSTANT i32 3196 %shift:gpr(s32) = G_SHL %copy0, %three(s32)197 %cmp:gpr(s32) = G_ICMP intpred(ult), %copy1(s32), %shift198 $w0 = COPY %cmp(s32)199 RET_ReallyLR implicit $w0200...201---202name: ult_ashr203legalized: true204regBankSelected: true205tracksRegLiveness: true206body: |207 bb.0:208 liveins: $w0, $w1209 210 ; CHECK-LABEL: name: ult_ashr211 ; CHECK: liveins: $w0, $w1212 ; CHECK-NEXT: {{ $}}213 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0214 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1215 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv216 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv217 ; CHECK-NEXT: $w0 = COPY %cmp218 ; CHECK-NEXT: RET_ReallyLR implicit $w0219 %copy0:gpr(s32) = COPY $w0220 %copy1:gpr(s32) = COPY $w1221 %three:gpr(s32) = G_CONSTANT i32 3222 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)223 %cmp:gpr(s32) = G_ICMP intpred(ult), %copy1(s32), %shift224 $w0 = COPY %cmp(s32)225 RET_ReallyLR implicit $w0226...227---228name: ult_lshr229legalized: true230regBankSelected: true231tracksRegLiveness: true232body: |233 bb.0:234 liveins: $w0, $w1235 236 ; CHECK-LABEL: name: ult_lshr237 ; CHECK: liveins: $w0, $w1238 ; CHECK-NEXT: {{ $}}239 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0240 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1241 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv242 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv243 ; CHECK-NEXT: $w0 = COPY %cmp244 ; CHECK-NEXT: RET_ReallyLR implicit $w0245 %copy0:gpr(s32) = COPY $w0246 %copy1:gpr(s32) = COPY $w1247 %three:gpr(s32) = G_CONSTANT i32 3248 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)249 %cmp:gpr(s32) = G_ICMP intpred(ult), %copy1(s32), %shift250 $w0 = COPY %cmp(s32)251 RET_ReallyLR implicit $w0252...253---254name: ugt_shl255legalized: true256regBankSelected: true257tracksRegLiveness: true258body: |259 bb.0:260 liveins: $w0, $w1261 262 ; CHECK-LABEL: name: ugt_shl263 ; CHECK: liveins: $w0, $w1264 ; CHECK-NEXT: {{ $}}265 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0266 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1267 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv268 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv269 ; CHECK-NEXT: $w0 = COPY %cmp270 ; CHECK-NEXT: RET_ReallyLR implicit $w0271 %copy0:gpr(s32) = COPY $w0272 %copy1:gpr(s32) = COPY $w1273 %three:gpr(s32) = G_CONSTANT i32 3274 %shift:gpr(s32) = G_SHL %copy0, %three(s32)275 %cmp:gpr(s32) = G_ICMP intpred(ugt), %copy1(s32), %shift276 $w0 = COPY %cmp(s32)277 RET_ReallyLR implicit $w0278...279---280name: ugt_ashr281legalized: true282regBankSelected: true283tracksRegLiveness: true284body: |285 bb.0:286 liveins: $w0, $w1287 288 ; CHECK-LABEL: name: ugt_ashr289 ; CHECK: liveins: $w0, $w1290 ; CHECK-NEXT: {{ $}}291 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0292 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1293 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv294 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv295 ; CHECK-NEXT: $w0 = COPY %cmp296 ; CHECK-NEXT: RET_ReallyLR implicit $w0297 %copy0:gpr(s32) = COPY $w0298 %copy1:gpr(s32) = COPY $w1299 %three:gpr(s32) = G_CONSTANT i32 3300 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)301 %cmp:gpr(s32) = G_ICMP intpred(ugt), %copy1(s32), %shift302 $w0 = COPY %cmp(s32)303 RET_ReallyLR implicit $w0304...305---306name: ugt_lshr307legalized: true308regBankSelected: true309tracksRegLiveness: true310body: |311 bb.0:312 liveins: $w0, $w1313 314 ; CHECK-LABEL: name: ugt_lshr315 ; CHECK: liveins: $w0, $w1316 ; CHECK-NEXT: {{ $}}317 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0318 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1319 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv320 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv321 ; CHECK-NEXT: $w0 = COPY %cmp322 ; CHECK-NEXT: RET_ReallyLR implicit $w0323 %copy0:gpr(s32) = COPY $w0324 %copy1:gpr(s32) = COPY $w1325 %three:gpr(s32) = G_CONSTANT i32 3326 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)327 %cmp:gpr(s32) = G_ICMP intpred(ugt), %copy1(s32), %shift328 $w0 = COPY %cmp(s32)329 RET_ReallyLR implicit $w0330...331 332...333---334name: uge_shl335legalized: true336regBankSelected: true337tracksRegLiveness: true338body: |339 bb.0:340 liveins: $w0, $w1341 342 ; CHECK-LABEL: name: uge_shl343 ; CHECK: liveins: $w0, $w1344 ; CHECK-NEXT: {{ $}}345 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0346 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1347 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv348 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv349 ; CHECK-NEXT: $w0 = COPY %cmp350 ; CHECK-NEXT: RET_ReallyLR implicit $w0351 %copy0:gpr(s32) = COPY $w0352 %copy1:gpr(s32) = COPY $w1353 %three:gpr(s32) = G_CONSTANT i32 3354 %shift:gpr(s32) = G_SHL %copy0, %three(s32)355 %cmp:gpr(s32) = G_ICMP intpred(uge), %copy1(s32), %shift356 $w0 = COPY %cmp(s32)357 RET_ReallyLR implicit $w0358...359---360name: uge_ashr361legalized: true362regBankSelected: true363tracksRegLiveness: true364body: |365 bb.0:366 liveins: $w0, $w1367 368 ; CHECK-LABEL: name: uge_ashr369 ; CHECK: liveins: $w0, $w1370 ; CHECK-NEXT: {{ $}}371 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0372 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1373 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv374 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv375 ; CHECK-NEXT: $w0 = COPY %cmp376 ; CHECK-NEXT: RET_ReallyLR implicit $w0377 %copy0:gpr(s32) = COPY $w0378 %copy1:gpr(s32) = COPY $w1379 %three:gpr(s32) = G_CONSTANT i32 3380 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)381 %cmp:gpr(s32) = G_ICMP intpred(uge), %copy1(s32), %shift382 $w0 = COPY %cmp(s32)383 RET_ReallyLR implicit $w0384...385---386name: uge_lshr387legalized: true388regBankSelected: true389tracksRegLiveness: true390body: |391 bb.0:392 liveins: $w0, $w1393 394 ; CHECK-LABEL: name: uge_lshr395 ; CHECK: liveins: $w0, $w1396 ; CHECK-NEXT: {{ $}}397 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0398 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1399 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv400 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv401 ; CHECK-NEXT: $w0 = COPY %cmp402 ; CHECK-NEXT: RET_ReallyLR implicit $w0403 %copy0:gpr(s32) = COPY $w0404 %copy1:gpr(s32) = COPY $w1405 %three:gpr(s32) = G_CONSTANT i32 3406 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)407 %cmp:gpr(s32) = G_ICMP intpred(uge), %copy1(s32), %shift408 $w0 = COPY %cmp(s32)409 RET_ReallyLR implicit $w0410...411 412...413---414name: ule_shl415legalized: true416regBankSelected: true417tracksRegLiveness: true418body: |419 bb.0:420 liveins: $w0, $w1421 422 ; CHECK-LABEL: name: ule_shl423 ; CHECK: liveins: $w0, $w1424 ; CHECK-NEXT: {{ $}}425 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0426 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1427 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv428 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv429 ; CHECK-NEXT: $w0 = COPY %cmp430 ; CHECK-NEXT: RET_ReallyLR implicit $w0431 %copy0:gpr(s32) = COPY $w0432 %copy1:gpr(s32) = COPY $w1433 %three:gpr(s32) = G_CONSTANT i32 3434 %shift:gpr(s32) = G_SHL %copy0, %three(s32)435 %cmp:gpr(s32) = G_ICMP intpred(ule), %copy1(s32), %shift436 $w0 = COPY %cmp(s32)437 RET_ReallyLR implicit $w0438...439---440name: ule_ashr441legalized: true442regBankSelected: true443tracksRegLiveness: true444body: |445 bb.0:446 liveins: $w0, $w1447 448 ; CHECK-LABEL: name: ule_ashr449 ; CHECK: liveins: $w0, $w1450 ; CHECK-NEXT: {{ $}}451 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0452 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1453 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv454 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv455 ; CHECK-NEXT: $w0 = COPY %cmp456 ; CHECK-NEXT: RET_ReallyLR implicit $w0457 %copy0:gpr(s32) = COPY $w0458 %copy1:gpr(s32) = COPY $w1459 %three:gpr(s32) = G_CONSTANT i32 3460 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)461 %cmp:gpr(s32) = G_ICMP intpred(ule), %copy1(s32), %shift462 $w0 = COPY %cmp(s32)463 RET_ReallyLR implicit $w0464...465---466name: ule_lshr467legalized: true468regBankSelected: true469tracksRegLiveness: true470body: |471 bb.0:472 liveins: $w0, $w1473 474 ; CHECK-LABEL: name: ule_lshr475 ; CHECK: liveins: $w0, $w1476 ; CHECK-NEXT: {{ $}}477 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0478 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1479 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv480 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv481 ; CHECK-NEXT: $w0 = COPY %cmp482 ; CHECK-NEXT: RET_ReallyLR implicit $w0483 %copy0:gpr(s32) = COPY $w0484 %copy1:gpr(s32) = COPY $w1485 %three:gpr(s32) = G_CONSTANT i32 3486 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)487 %cmp:gpr(s32) = G_ICMP intpred(ule), %copy1(s32), %shift488 $w0 = COPY %cmp(s32)489 RET_ReallyLR implicit $w0490...491...492---493name: slt_shl494legalized: true495regBankSelected: true496tracksRegLiveness: true497body: |498 bb.0:499 liveins: $w0, $w1500 501 ; CHECK-LABEL: name: slt_shl502 ; CHECK: liveins: $w0, $w1503 ; CHECK-NEXT: {{ $}}504 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0505 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1506 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv507 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv508 ; CHECK-NEXT: $w0 = COPY %cmp509 ; CHECK-NEXT: RET_ReallyLR implicit $w0510 %copy0:gpr(s32) = COPY $w0511 %copy1:gpr(s32) = COPY $w1512 %three:gpr(s32) = G_CONSTANT i32 3513 %shift:gpr(s32) = G_SHL %copy0, %three(s32)514 %cmp:gpr(s32) = G_ICMP intpred(slt), %copy1(s32), %shift515 $w0 = COPY %cmp(s32)516 RET_ReallyLR implicit $w0517...518---519name: slt_ashr520legalized: true521regBankSelected: true522tracksRegLiveness: true523body: |524 bb.0:525 liveins: $w0, $w1526 527 ; CHECK-LABEL: name: slt_ashr528 ; CHECK: liveins: $w0, $w1529 ; CHECK-NEXT: {{ $}}530 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0531 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1532 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv533 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv534 ; CHECK-NEXT: $w0 = COPY %cmp535 ; CHECK-NEXT: RET_ReallyLR implicit $w0536 %copy0:gpr(s32) = COPY $w0537 %copy1:gpr(s32) = COPY $w1538 %three:gpr(s32) = G_CONSTANT i32 3539 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)540 %cmp:gpr(s32) = G_ICMP intpred(slt), %copy1(s32), %shift541 $w0 = COPY %cmp(s32)542 RET_ReallyLR implicit $w0543...544---545name: slt_lshr546legalized: true547regBankSelected: true548tracksRegLiveness: true549body: |550 bb.0:551 liveins: $w0, $w1552 553 ; CHECK-LABEL: name: slt_lshr554 ; CHECK: liveins: $w0, $w1555 ; CHECK-NEXT: {{ $}}556 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0557 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1558 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv559 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv560 ; CHECK-NEXT: $w0 = COPY %cmp561 ; CHECK-NEXT: RET_ReallyLR implicit $w0562 %copy0:gpr(s32) = COPY $w0563 %copy1:gpr(s32) = COPY $w1564 %three:gpr(s32) = G_CONSTANT i32 3565 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)566 %cmp:gpr(s32) = G_ICMP intpred(slt), %copy1(s32), %shift567 $w0 = COPY %cmp(s32)568 RET_ReallyLR implicit $w0569...570---571name: sgt_shl572legalized: true573regBankSelected: true574tracksRegLiveness: true575body: |576 bb.0:577 liveins: $w0, $w1578 579 ; CHECK-LABEL: name: sgt_shl580 ; CHECK: liveins: $w0, $w1581 ; CHECK-NEXT: {{ $}}582 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0583 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1584 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv585 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv586 ; CHECK-NEXT: $w0 = COPY %cmp587 ; CHECK-NEXT: RET_ReallyLR implicit $w0588 %copy0:gpr(s32) = COPY $w0589 %copy1:gpr(s32) = COPY $w1590 %three:gpr(s32) = G_CONSTANT i32 3591 %shift:gpr(s32) = G_SHL %copy0, %three(s32)592 %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy1(s32), %shift593 $w0 = COPY %cmp(s32)594 RET_ReallyLR implicit $w0595...596---597name: sgt_ashr598legalized: true599regBankSelected: true600tracksRegLiveness: true601body: |602 bb.0:603 liveins: $w0, $w1604 605 ; CHECK-LABEL: name: sgt_ashr606 ; CHECK: liveins: $w0, $w1607 ; CHECK-NEXT: {{ $}}608 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0609 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1610 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv611 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv612 ; CHECK-NEXT: $w0 = COPY %cmp613 ; CHECK-NEXT: RET_ReallyLR implicit $w0614 %copy0:gpr(s32) = COPY $w0615 %copy1:gpr(s32) = COPY $w1616 %three:gpr(s32) = G_CONSTANT i32 3617 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)618 %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy1(s32), %shift619 $w0 = COPY %cmp(s32)620 RET_ReallyLR implicit $w0621...622---623name: sgt_lshr624legalized: true625regBankSelected: true626tracksRegLiveness: true627body: |628 bb.0:629 liveins: $w0, $w1630 631 ; CHECK-LABEL: name: sgt_lshr632 ; CHECK: liveins: $w0, $w1633 ; CHECK-NEXT: {{ $}}634 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0635 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1636 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv637 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv638 ; CHECK-NEXT: $w0 = COPY %cmp639 ; CHECK-NEXT: RET_ReallyLR implicit $w0640 %copy0:gpr(s32) = COPY $w0641 %copy1:gpr(s32) = COPY $w1642 %three:gpr(s32) = G_CONSTANT i32 3643 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)644 %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy1(s32), %shift645 $w0 = COPY %cmp(s32)646 RET_ReallyLR implicit $w0647...648---649name: sge_shl650legalized: true651regBankSelected: true652tracksRegLiveness: true653body: |654 bb.0:655 liveins: $w0, $w1656 657 ; CHECK-LABEL: name: sge_shl658 ; CHECK: liveins: $w0, $w1659 ; CHECK-NEXT: {{ $}}660 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0661 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1662 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv663 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv664 ; CHECK-NEXT: $w0 = COPY %cmp665 ; CHECK-NEXT: RET_ReallyLR implicit $w0666 %copy0:gpr(s32) = COPY $w0667 %copy1:gpr(s32) = COPY $w1668 %three:gpr(s32) = G_CONSTANT i32 3669 %shift:gpr(s32) = G_SHL %copy0, %three(s32)670 %cmp:gpr(s32) = G_ICMP intpred(sge), %copy1(s32), %shift671 $w0 = COPY %cmp(s32)672 RET_ReallyLR implicit $w0673...674---675name: sge_ashr676legalized: true677regBankSelected: true678tracksRegLiveness: true679body: |680 bb.0:681 liveins: $w0, $w1682 683 ; CHECK-LABEL: name: sge_ashr684 ; CHECK: liveins: $w0, $w1685 ; CHECK-NEXT: {{ $}}686 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0687 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1688 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv689 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv690 ; CHECK-NEXT: $w0 = COPY %cmp691 ; CHECK-NEXT: RET_ReallyLR implicit $w0692 %copy0:gpr(s32) = COPY $w0693 %copy1:gpr(s32) = COPY $w1694 %three:gpr(s32) = G_CONSTANT i32 3695 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)696 %cmp:gpr(s32) = G_ICMP intpred(sge), %copy1(s32), %shift697 $w0 = COPY %cmp(s32)698 RET_ReallyLR implicit $w0699...700---701name: sge_lshr702legalized: true703regBankSelected: true704tracksRegLiveness: true705body: |706 bb.0:707 liveins: $w0, $w1708 709 ; CHECK-LABEL: name: sge_lshr710 ; CHECK: liveins: $w0, $w1711 ; CHECK-NEXT: {{ $}}712 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0713 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1714 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv715 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv716 ; CHECK-NEXT: $w0 = COPY %cmp717 ; CHECK-NEXT: RET_ReallyLR implicit $w0718 %copy0:gpr(s32) = COPY $w0719 %copy1:gpr(s32) = COPY $w1720 %three:gpr(s32) = G_CONSTANT i32 3721 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)722 %cmp:gpr(s32) = G_ICMP intpred(sge), %copy1(s32), %shift723 $w0 = COPY %cmp(s32)724 RET_ReallyLR implicit $w0725...726 727...728---729name: sle_shl730legalized: true731regBankSelected: true732tracksRegLiveness: true733body: |734 bb.0:735 liveins: $w0, $w1736 737 ; CHECK-LABEL: name: sle_shl738 ; CHECK: liveins: $w0, $w1739 ; CHECK-NEXT: {{ $}}740 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0741 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1742 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv743 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv744 ; CHECK-NEXT: $w0 = COPY %cmp745 ; CHECK-NEXT: RET_ReallyLR implicit $w0746 %copy0:gpr(s32) = COPY $w0747 %copy1:gpr(s32) = COPY $w1748 %three:gpr(s32) = G_CONSTANT i32 3749 %shift:gpr(s32) = G_SHL %copy0, %three(s32)750 %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %shift751 $w0 = COPY %cmp(s32)752 RET_ReallyLR implicit $w0753...754---755name: sle_ashr756legalized: true757regBankSelected: true758tracksRegLiveness: true759body: |760 bb.0:761 liveins: $w0, $w1762 763 ; CHECK-LABEL: name: sle_ashr764 ; CHECK: liveins: $w0, $w1765 ; CHECK-NEXT: {{ $}}766 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0767 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1768 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv769 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv770 ; CHECK-NEXT: $w0 = COPY %cmp771 ; CHECK-NEXT: RET_ReallyLR implicit $w0772 %copy0:gpr(s32) = COPY $w0773 %copy1:gpr(s32) = COPY $w1774 %three:gpr(s32) = G_CONSTANT i32 3775 %shift:gpr(s32) = G_ASHR %copy0, %three(s32)776 %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %shift777 $w0 = COPY %cmp(s32)778 RET_ReallyLR implicit $w0779...780---781name: sle_lshr782legalized: true783regBankSelected: true784tracksRegLiveness: true785body: |786 bb.0:787 liveins: $w0, $w1788 789 ; CHECK-LABEL: name: sle_lshr790 ; CHECK: liveins: $w0, $w1791 ; CHECK-NEXT: {{ $}}792 ; CHECK-NEXT: %copy0:gpr32 = COPY $w0793 ; CHECK-NEXT: %copy1:gpr32 = COPY $w1794 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv795 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv796 ; CHECK-NEXT: $w0 = COPY %cmp797 ; CHECK-NEXT: RET_ReallyLR implicit $w0798 %copy0:gpr(s32) = COPY $w0799 %copy1:gpr(s32) = COPY $w1800 %three:gpr(s32) = G_CONSTANT i32 3801 %shift:gpr(s32) = G_LSHR %copy0, %three(s32)802 %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %shift803 $w0 = COPY %cmp(s32)804 RET_ReallyLR implicit $w0805...806