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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=LOWER3# RUN: llc -mtriple aarch64 -O2 -start-before=aarch64-postlegalizer-lowering -stop-after=instruction-select -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=SELECT4...5---6name: same_reg7legalized: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $d012 ; LOWER-LABEL: name: same_reg13 ; LOWER: liveins: $d014 ; LOWER-NEXT: {{ $}}15 ; LOWER-NEXT: %r:_(s8) = G_IMPLICIT_DEF16 ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_DUP %r(s8)17 ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)18 ; LOWER-NEXT: RET_ReallyLR implicit $d019 ;20 ; SELECT-LABEL: name: same_reg21 ; SELECT: liveins: $d022 ; SELECT-NEXT: {{ $}}23 ; SELECT-NEXT: %r:gpr32 = IMPLICIT_DEF24 ; SELECT-NEXT: %build_vector:fpr64 = DUPv8i8gpr %r25 ; SELECT-NEXT: $d0 = COPY %build_vector26 ; SELECT-NEXT: RET_ReallyLR implicit $d027 %r:_(s8) = G_IMPLICIT_DEF28 %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r29 $d0 = COPY %build_vector(<8 x s8>)30 RET_ReallyLR implicit $d031 32...33---34name: dont_combine_different_reg35legalized: true36tracksRegLiveness: true37body: |38 bb.0:39 liveins: $d0, $w0, $w140 ; LOWER-LABEL: name: dont_combine_different_reg41 ; LOWER: liveins: $d0, $w0, $w142 ; LOWER-NEXT: {{ $}}43 ; LOWER-NEXT: %r:_(s32) = COPY $w044 ; LOWER-NEXT: %q:_(s32) = COPY $w145 ; LOWER-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF46 ; LOWER-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 047 ; LOWER-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], %r(s32), [[C]](s64)48 ; LOWER-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 149 ; LOWER-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], %q(s32), [[C1]](s64)50 ; LOWER-NEXT: %build_vector:_(<2 x s32>) = COPY [[IVEC1]](<2 x s32>)51 ; LOWER-NEXT: $d0 = COPY %build_vector(<2 x s32>)52 ; LOWER-NEXT: RET_ReallyLR implicit $d053 ;54 ; SELECT-LABEL: name: dont_combine_different_reg55 ; SELECT: liveins: $d0, $w0, $w156 ; SELECT-NEXT: {{ $}}57 ; SELECT-NEXT: %r:gpr32 = COPY $w058 ; SELECT-NEXT: %q:gpr32 = COPY $w159 ; SELECT-NEXT: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF60 ; SELECT-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr64 = INSERT_SUBREG [[DEF]], %r, %subreg.ssub61 ; SELECT-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF62 ; SELECT-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[INSERT_SUBREG]], %subreg.dsub63 ; SELECT-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, %q64 ; SELECT-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub65 ; SELECT-NEXT: $d0 = COPY [[COPY]]66 ; SELECT-NEXT: RET_ReallyLR implicit $d067 %r:_(s32) = COPY $w068 %q:_(s32) = COPY $w169 %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %r, %q70 $d0 = COPY %build_vector(<2 x s32>)71 RET_ReallyLR implicit $d072 73...74---75name: dont_combine_zero76legalized: true77tracksRegLiveness: true78body: |79 bb.0:80 liveins: $d081 82 ; LOWER-LABEL: name: dont_combine_zero83 ; LOWER: liveins: $d084 ; LOWER-NEXT: {{ $}}85 ; LOWER-NEXT: %r:_(s8) = G_CONSTANT i8 086 ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8)87 ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)88 ; LOWER-NEXT: RET_ReallyLR implicit $d089 ;90 ; SELECT-LABEL: name: dont_combine_zero91 ; SELECT: liveins: $d092 ; SELECT-NEXT: {{ $}}93 ; SELECT-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 094 ; SELECT-NEXT: %build_vector:fpr64 = COPY [[MOVIv2d_ns]].dsub95 ; SELECT-NEXT: $d0 = COPY %build_vector96 ; SELECT-NEXT: RET_ReallyLR implicit $d097 %r:_(s8) = G_CONSTANT i8 098 %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r99 $d0 = COPY %build_vector(<8 x s8>)100 RET_ReallyLR implicit $d0101 102...103---104name: dont_combine_all_ones105legalized: true106tracksRegLiveness: true107body: |108 bb.0:109 liveins: $d0110 111 ; LOWER-LABEL: name: dont_combine_all_ones112 ; LOWER: liveins: $d0113 ; LOWER-NEXT: {{ $}}114 ; LOWER-NEXT: %r:_(s8) = G_CONSTANT i8 -1115 ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8), %r(s8)116 ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)117 ; LOWER-NEXT: RET_ReallyLR implicit $d0118 ;119 ; SELECT-LABEL: name: dont_combine_all_ones120 ; SELECT: liveins: $d0121 ; SELECT-NEXT: {{ $}}122 ; SELECT-NEXT: %build_vector:fpr64 = MOVID 255123 ; SELECT-NEXT: $d0 = COPY %build_vector124 ; SELECT-NEXT: RET_ReallyLR implicit $d0125 %r:_(s8) = G_CONSTANT i8 -1126 %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r127 $d0 = COPY %build_vector(<8 x s8>)128 RET_ReallyLR implicit $d0129 130...131---132name: all_zeros_pat_example133legalized: true134tracksRegLiveness: true135body: |136 bb.0:137 liveins: $d0138 139 ; LOWER-LABEL: name: all_zeros_pat_example140 ; LOWER: liveins: $d0141 ; LOWER-NEXT: {{ $}}142 ; LOWER-NEXT: %v:_(<2 x s32>) = COPY $d0143 ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 0144 ; LOWER-NEXT: %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst(s32), %cst(s32)145 ; LOWER-NEXT: %sub:_(<2 x s32>) = G_SUB %build_vector, %v146 ; LOWER-NEXT: $d0 = COPY %sub(<2 x s32>)147 ; LOWER-NEXT: RET_ReallyLR implicit $d0148 ;149 ; SELECT-LABEL: name: all_zeros_pat_example150 ; SELECT: liveins: $d0151 ; SELECT-NEXT: {{ $}}152 ; SELECT-NEXT: %v:fpr64 = COPY $d0153 ; SELECT-NEXT: %sub:fpr64 = NEGv2i32 %v154 ; SELECT-NEXT: $d0 = COPY %sub155 ; SELECT-NEXT: RET_ReallyLR implicit $d0156 %v:_(<2 x s32>) = COPY $d0157 %cst:_(s32) = G_CONSTANT i32 0158 %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst159 %sub:_(<2 x s32>) = G_SUB %build_vector, %v160 $d0 = COPY %sub(<2 x s32>)161 RET_ReallyLR implicit $d0162 163...164---165name: all_ones_pat_example166legalized: true167tracksRegLiveness: true168body: |169 bb.0:170 liveins: $d0, $d1171 172 ; LOWER-LABEL: name: all_ones_pat_example173 ; LOWER: liveins: $d0, $d1174 ; LOWER-NEXT: {{ $}}175 ; LOWER-NEXT: %v0:_(<2 x s32>) = COPY $d0176 ; LOWER-NEXT: %v1:_(<2 x s32>) = COPY $d1177 ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 -1178 ; LOWER-NEXT: %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst(s32), %cst(s32)179 ; LOWER-NEXT: %xor:_(<2 x s32>) = G_XOR %v0, %build_vector180 ; LOWER-NEXT: %and:_(<2 x s32>) = G_AND %v1, %xor181 ; LOWER-NEXT: $d0 = COPY %and(<2 x s32>)182 ; LOWER-NEXT: RET_ReallyLR implicit $d0183 ;184 ; SELECT-LABEL: name: all_ones_pat_example185 ; SELECT: liveins: $d0, $d1186 ; SELECT-NEXT: {{ $}}187 ; SELECT-NEXT: %v0:fpr64 = COPY $d0188 ; SELECT-NEXT: %v1:fpr64 = COPY $d1189 ; SELECT-NEXT: %and:fpr64 = BICv8i8 %v1, %v0190 ; SELECT-NEXT: $d0 = COPY %and191 ; SELECT-NEXT: RET_ReallyLR implicit $d0192 %v0:_(<2 x s32>) = COPY $d0193 %v1:_(<2 x s32>) = COPY $d1194 %cst:_(s32) = G_CONSTANT i32 -1195 %build_vector:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst196 %xor:_(<2 x s32>) = G_XOR %v0, %build_vector197 %and:_(<2 x s32>) = G_AND %v1, %xor198 $d0 = COPY %and(<2 x s32>)199 RET_ReallyLR implicit $d0200