310 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=aarch64-postlegalizer-lowering --aarch64postlegalizerlowering-only-enable-rule="shuf_to_ins" -verify-machineinstrs %s -o - | FileCheck %s3# REQUIRES: asserts4 5# Check that we can recognize an ins mask for a shuffle vector.6 7...8---9name: v2s32_match_left_010legalized: true11tracksRegLiveness: true12body: |13 bb.0:14 liveins: $d0, $d115 16 ; 2 elts -> need 1 match.17 ; Matched M[0] = 0 -> G_INSERT_VECTOR_ELT should use %left.18 ; DstLane (G_INSERT_VECTOR_ELT) : 1, because M[1] != 1.19 ; SrcLane (G_EXTRACT_VECTOR_ELT) : M[DstLane] = 020 21 ; CHECK-LABEL: name: v2s32_match_left_022 ; CHECK: liveins: $d0, $d123 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d025 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 026 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)27 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 128 ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)29 ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)30 ; CHECK-NEXT: RET_ReallyLR implicit $d031 %left:_(<2 x s32>) = COPY $d032 %right:_(<2 x s32>) = COPY $d133 %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(0, 0)34 $d0 = COPY %shuf(<2 x s32>)35 RET_ReallyLR implicit $d036 37...38---39name: v2s32_match_left_140legalized: true41tracksRegLiveness: true42body: |43 bb.0:44 liveins: $d0, $d145 46 ; 2 elts -> need 1 match.47 ; Matched M[1] = 1 -> G_INSERT_VECTOR_ELT should use %left.48 ; DstLane (G_INSERT_VECTOR_ELT) : 0, because M[0] != 0.49 ; SrcLane (G_EXTRACT_VECTOR_ELT) : M[0] = 150 51 ; CHECK-LABEL: name: v2s32_match_left_152 ; CHECK: liveins: $d0, $d153 ; CHECK-NEXT: {{ $}}54 ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d055 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 156 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)57 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 058 ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)59 ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)60 ; CHECK-NEXT: RET_ReallyLR implicit $d061 %left:_(<2 x s32>) = COPY $d062 %right:_(<2 x s32>) = COPY $d163 %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(1, 1)64 $d0 = COPY %shuf(<2 x s32>)65 RET_ReallyLR implicit $d066 67...68---69name: v2s32_match_left_370legalized: true71tracksRegLiveness: true72body: |73 bb.0:74 liveins: $d0, $d175 76 ; 2 elts -> need 1 match.77 ; Matched M[0] = 1 -> G_INSERT_VECTOR_ELT should use %left.78 ; DstLane (G_INSERT_VECTOR_ELT) : 1, because M[1] != 1.79 ; SrcLane (G_EXTRACT_VECTOR_ELT) : M[1] = 3 - 2 = 180 81 ; CHECK-LABEL: name: v2s32_match_left_382 ; CHECK: liveins: $d0, $d183 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d085 ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d186 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 187 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)88 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 189 ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)90 ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)91 ; CHECK-NEXT: RET_ReallyLR implicit $d092 %left:_(<2 x s32>) = COPY $d093 %right:_(<2 x s32>) = COPY $d194 %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(0, 3)95 $d0 = COPY %shuf(<2 x s32>)96 RET_ReallyLR implicit $d097 98 99...100---101name: v2s32_match_right_3102legalized: true103tracksRegLiveness: true104body: |105 bb.0:106 liveins: $d0, $d1107 108 ; 2 elts -> need 1 match.109 ; Matched M[1] = 1 + 2 -> G_INSERT_VECTOR_ELT should use %right.110 ; DstLane (G_INSERT_VECTOR_ELT) : 0, because M[0] != 2.111 ; SrcLane (G_EXTRACT_VECTOR_ELT) : M[0] = 1112 113 ; CHECK-LABEL: name: v2s32_match_right_3114 ; CHECK: liveins: $d0, $d1115 ; CHECK-NEXT: {{ $}}116 ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0117 ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1118 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1119 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)120 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0121 ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](s64)122 ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)123 ; CHECK-NEXT: RET_ReallyLR implicit $d0124 %left:_(<2 x s32>) = COPY $d0125 %right:_(<2 x s32>) = COPY $d1126 %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(1, 3)127 $d0 = COPY %shuf(<2 x s32>)128 RET_ReallyLR implicit $d0129 130...131---132name: v2s32_match_right_2133legalized: true134tracksRegLiveness: true135body: |136 bb.0:137 liveins: $d0, $d1138 139 ; 2 elts -> need 1 match.140 ; Matched M[0] = 0 + 2 -> G_INSERT_VECTOR_ELT should use %right.141 ; DstLane (G_INSERT_VECTOR_ELT) : 1, because M[1] != 3.142 ; SrcLane (G_EXTRACT_VECTOR_ELT) : M[1] = 0143 144 ; CHECK-LABEL: name: v2s32_match_right_2145 ; CHECK: liveins: $d0, $d1146 ; CHECK-NEXT: {{ $}}147 ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0148 ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1149 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0150 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<2 x s32>), [[C]](s64)151 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1152 ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](s64)153 ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)154 ; CHECK-NEXT: RET_ReallyLR implicit $d0155 %left:_(<2 x s32>) = COPY $d0156 %right:_(<2 x s32>) = COPY $d1157 %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, 0)158 $d0 = COPY %shuf(<2 x s32>)159 RET_ReallyLR implicit $d0160 161...162---163name: dont_combine_too_many_matches_right164legalized: true165tracksRegLiveness: true166body: |167 bb.0:168 liveins: $d0, $d1169 170 ; 2 elts -> need 1 match.171 ; Matched M[0] = 0 + 2, M[1] = 1 + 2 -> too many matches.172 173 ; CHECK-LABEL: name: dont_combine_too_many_matches_right174 ; CHECK: liveins: $d0, $d1175 ; CHECK-NEXT: {{ $}}176 ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0177 ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1178 ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, 3)179 ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)180 ; CHECK-NEXT: RET_ReallyLR implicit $d0181 %left:_(<2 x s32>) = COPY $d0182 %right:_(<2 x s32>) = COPY $d1183 %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, 3)184 $d0 = COPY %shuf(<2 x s32>)185 RET_ReallyLR implicit $d0186 187...188---189name: tiebreaker190legalized: true191tracksRegLiveness: true192body: |193 bb.0:194 liveins: $d0, $d1195 196 ; Matched the correct amount on the left and right.197 ; Use left as a tiebreaker.198 ; Matched M[1] = 1 -> G_INSERT_VECTOR_ELT should use %left.199 ; DstLane (G_INSERT_VECTOR_ELT) : 0, because M[0] != 0.200 ; SrcLane (G_EXTRACT_VECTOR_ELT) : M[0] = 2 - 2 = 0201 202 ; CHECK-LABEL: name: tiebreaker203 ; CHECK: liveins: $d0, $d1204 ; CHECK-NEXT: {{ $}}205 ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0206 ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1207 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0208 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)209 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0210 ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)211 ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)212 ; CHECK-NEXT: RET_ReallyLR implicit $d0213 %left:_(<2 x s32>) = COPY $d0214 %right:_(<2 x s32>) = COPY $d1215 %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, 1)216 $d0 = COPY %shuf(<2 x s32>)217 RET_ReallyLR implicit $d0218 219...220---221name: tiebreaker_undef222legalized: true223tracksRegLiveness: true224body: |225 bb.0:226 liveins: $d0, $d1227 228 ; Undef counts as a match for left and right.229 ; Matched M[1] = -1 -> G_INSERT_VECTOR_ELT should use %left.230 ; DstLane (G_INSERT_VECTOR_ELT) : 0, because M[0] != 0.231 ; SrcLane (G_EXTRACT_VECTOR_ELT) : M[0] = 2 - 2 = 0232 233 ; CHECK-LABEL: name: tiebreaker_undef234 ; CHECK: liveins: $d0, $d1235 ; CHECK-NEXT: {{ $}}236 ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0237 ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1238 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0239 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)240 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0241 ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)242 ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)243 ; CHECK-NEXT: RET_ReallyLR implicit $d0244 %left:_(<2 x s32>) = COPY $d0245 %right:_(<2 x s32>) = COPY $d1246 %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(2, -1)247 $d0 = COPY %shuf(<2 x s32>)248 RET_ReallyLR implicit $d0249 250...251---252name: match_left_undef253legalized: true254tracksRegLiveness: true255body: |256 bb.0:257 liveins: $d0, $d1258 259 ; Undef counts as a match for left and right.260 ; Matched M[1] = -1 -> G_INSERT_VECTOR_ELT should use %left.261 ; DstLane (G_INSERT_VECTOR_ELT) : 0, because M[0] != 0.262 ; SrcLane (G_EXTRACT_VECTOR_ELT) : M[0] = 3 - 2 = 1263 264 ; CHECK-LABEL: name: match_left_undef265 ; CHECK: liveins: $d0, $d1266 ; CHECK-NEXT: {{ $}}267 ; CHECK-NEXT: %left:_(<2 x s32>) = COPY $d0268 ; CHECK-NEXT: %right:_(<2 x s32>) = COPY $d1269 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1270 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %right(<2 x s32>), [[C]](s64)271 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0272 ; CHECK-NEXT: %shuf:_(<2 x s32>) = G_INSERT_VECTOR_ELT %left, [[EVEC]](s32), [[C1]](s64)273 ; CHECK-NEXT: $d0 = COPY %shuf(<2 x s32>)274 ; CHECK-NEXT: RET_ReallyLR implicit $d0275 %left:_(<2 x s32>) = COPY $d0276 %right:_(<2 x s32>) = COPY $d1277 %shuf:_(<2 x s32>) = G_SHUFFLE_VECTOR %left(<2 x s32>), %right, shufflemask(3, -1)278 $d0 = COPY %shuf(<2 x s32>)279 RET_ReallyLR implicit $d0280 281...282---283name: match_right_undef284legalized: true285tracksRegLiveness: true286body: |287 bb.0:288 liveins: $q0, $q1289 290 ; Matched M[0] = 0 + 4, undef, undef => 3 matches on the right.291 ; DstLane (G_INSERT_VECTOR_ELT) : 3, because M[3] != 7.292 ; SrcLane (G_EXTRACT_VECTOR_ELT) : M[3] = 2293 294 ; CHECK-LABEL: name: match_right_undef295 ; CHECK: liveins: $q0, $q1296 ; CHECK-NEXT: {{ $}}297 ; CHECK-NEXT: %left:_(<4 x s32>) = COPY $q0298 ; CHECK-NEXT: %right:_(<4 x s32>) = COPY $q1299 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2300 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT %left(<4 x s32>), [[C]](s64)301 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3302 ; CHECK-NEXT: %shuf:_(<4 x s32>) = G_INSERT_VECTOR_ELT %right, [[EVEC]](s32), [[C1]](s64)303 ; CHECK-NEXT: $q0 = COPY %shuf(<4 x s32>)304 ; CHECK-NEXT: RET_ReallyLR implicit $q0305 %left:_(<4 x s32>) = COPY $q0306 %right:_(<4 x s32>) = COPY $q1307 %shuf:_(<4 x s32>) = G_SHUFFLE_VECTOR %left(<4 x s32>), %right, shufflemask(4, -1, -1, 2)308 $q0 = COPY %shuf(<4 x s32>)309 RET_ReallyLR implicit $q0310