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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s3 4...5---6name: ashr_v4s327alignment: 48legalized: true9tracksRegLiveness: true10body: |11 bb.1.entry:12 liveins: $d0, $d113 14 ; CHECK-LABEL: name: ashr_v4s3215 ; CHECK: liveins: $d0, $d116 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q018 ; CHECK-NEXT: [[VASHR:%[0-9]+]]:_(<4 x s32>) = G_VASHR [[COPY]], 519 ; CHECK-NEXT: $q0 = COPY [[VASHR]](<4 x s32>)20 ; CHECK-NEXT: RET_ReallyLR implicit $q021 %0:_(<4 x s32>) = COPY $q022 %1:_(s32) = G_CONSTANT i32 523 %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)24 %3:_(<4 x s32>) = G_ASHR %0, %2(<4 x s32>)25 $q0 = COPY %3(<4 x s32>)26 RET_ReallyLR implicit $q027...28---29name: lshr_v4s3230alignment: 431legalized: true32tracksRegLiveness: true33body: |34 bb.1.entry:35 liveins: $d0, $d136 37 ; CHECK-LABEL: name: lshr_v4s3238 ; CHECK: liveins: $d0, $d139 ; CHECK-NEXT: {{ $}}40 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q041 ; CHECK-NEXT: [[VLSHR:%[0-9]+]]:_(<4 x s32>) = G_VLSHR [[COPY]], 542 ; CHECK-NEXT: $q0 = COPY [[VLSHR]](<4 x s32>)43 ; CHECK-NEXT: RET_ReallyLR implicit $q044 %0:_(<4 x s32>) = COPY $q045 %1:_(s32) = G_CONSTANT i32 546 %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)47 %3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)48 $q0 = COPY %3(<4 x s32>)49 RET_ReallyLR implicit $q050...51---52name: lshr_v8s1653alignment: 454legalized: true55tracksRegLiveness: true56body: |57 bb.1.entry:58 liveins: $d0, $d159 60 ; CHECK-LABEL: name: lshr_v8s1661 ; CHECK: liveins: $d0, $d162 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q064 ; CHECK-NEXT: [[VLSHR:%[0-9]+]]:_(<8 x s16>) = G_VLSHR [[COPY]], 565 ; CHECK-NEXT: $q0 = COPY [[VLSHR]](<8 x s16>)66 ; CHECK-NEXT: RET_ReallyLR implicit $q067 %0:_(<8 x s16>) = COPY $q068 %1:_(s16) = G_CONSTANT i16 569 %2:_(<8 x s16>) = G_BUILD_VECTOR %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16)70 %3:_(<8 x s16>) = G_LSHR %0, %2(<8 x s16>)71 $q0 = COPY %3(<8 x s16>)72 RET_ReallyLR implicit $q073...74---75name: imm_too_large76alignment: 477legalized: true78tracksRegLiveness: true79body: |80 bb.1.entry:81 liveins: $d0, $d182 83 ; CHECK-LABEL: name: imm_too_large84 ; CHECK: liveins: $d0, $d185 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q087 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4088 ; CHECK-NEXT: [[DUP:%[0-9]+]]:_(<4 x s32>) = G_DUP [[C]](s32)89 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[DUP]](<4 x s32>)90 ; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x s32>)91 ; CHECK-NEXT: RET_ReallyLR implicit $q092 %0:_(<4 x s32>) = COPY $q093 %1:_(s32) = G_CONSTANT i32 4094 %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)95 %3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)96 $q0 = COPY %3(<4 x s32>)97 RET_ReallyLR implicit $q098...99---100name: imm_zero101alignment: 4102legalized: true103tracksRegLiveness: true104body: |105 bb.1.entry:106 liveins: $d0, $d1107 108 ; CHECK-LABEL: name: imm_zero109 ; CHECK: liveins: $d0, $d1110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0112 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0113 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)114 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)115 ; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x s32>)116 ; CHECK-NEXT: RET_ReallyLR implicit $q0117 %0:_(<4 x s32>) = COPY $q0118 %1:_(s32) = G_CONSTANT i32 0119 %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)120 %3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)121 $q0 = COPY %3(<4 x s32>)122 RET_ReallyLR implicit $q0123...124---125name: imm_not_splat126alignment: 4127legalized: true128tracksRegLiveness: true129body: |130 bb.1.entry:131 liveins: $d0, $d1132 133 ; CHECK-LABEL: name: imm_not_splat134 ; CHECK: liveins: $d0, $d1135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0137 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4138 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 6139 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C]](s32), [[C]](s32)140 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>)141 ; CHECK-NEXT: $q0 = COPY [[LSHR]](<4 x s32>)142 ; CHECK-NEXT: RET_ReallyLR implicit $q0143 %0:_(<4 x s32>) = COPY $q0144 %1:_(s32) = G_CONSTANT i32 4145 %4:_(s32) = G_CONSTANT i32 6146 %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %4(s32), %1(s32), %1(s32)147 %3:_(<4 x s32>) = G_LSHR %0, %2(<4 x s32>)148 $q0 = COPY %3(<4 x s32>)149 RET_ReallyLR implicit $q0150...151