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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4...5---6name: or_combine_sext7tracksRegLiveness: true8legalized: true9body: |10 bb.0:11 liveins: $w0, $w112 ; or (sext X), (sext Y) --> sext (or X, Y)13 ; CHECK-LABEL: name: or_combine_sext14 ; CHECK: liveins: $w0, $w115 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: %x:_(s32) = COPY $w017 ; CHECK-NEXT: %y:_(s32) = COPY $w118 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y19 ; CHECK-NEXT: %logic_op:_(s64) = G_SEXT [[OR]](s32)20 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)21 ; CHECK-NEXT: RET_ReallyLR implicit $x022 %x:_(s32) = COPY $w023 %y:_(s32) = COPY $w124 %hand1:_(s64) = G_SEXT %x(s32)25 %hand2:_(s64) = G_SEXT %y(s32)26 %logic_op:_(s64) = G_OR %hand1, %hand227 $x0 = COPY %logic_op(s64)28 RET_ReallyLR implicit $x029 30...31---32name: illegal_ty33tracksRegLiveness: true34legalized: true35body: |36 bb.0:37 liveins: $w0, $w138 ; Post-legalization, we should not perform the optimization here, since39 ; it would create an illegal G_OR.40 ; CHECK-LABEL: name: illegal_ty41 ; CHECK: liveins: $w0, $w142 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: %x_wide:_(s32) = COPY $w044 ; CHECK-NEXT: %y_wide:_(s32) = COPY $w145 ; CHECK-NEXT: %x:_(s1) = G_TRUNC %x_wide(s32)46 ; CHECK-NEXT: %y:_(s1) = G_TRUNC %y_wide(s32)47 ; CHECK-NEXT: %hand1:_(s64) = G_SEXT %x(s1)48 ; CHECK-NEXT: %hand2:_(s64) = G_SEXT %y(s1)49 ; CHECK-NEXT: %logic_op:_(s64) = G_OR %hand1, %hand250 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)51 ; CHECK-NEXT: RET_ReallyLR implicit $x052 %x_wide:_(s32) = COPY $w053 %y_wide:_(s32) = COPY $w154 %x:_(s1) = G_TRUNC %x_wide55 %y:_(s1) = G_TRUNC %y_wide56 %hand1:_(s64) = G_SEXT %x(s1)57 %hand2:_(s64) = G_SEXT %y(s1)58 %logic_op:_(s64) = G_OR %hand1, %hand259 $x0 = COPY %logic_op(s64)60 RET_ReallyLR implicit $x061 62...63---64name: dont_combine_physreg65tracksRegLiveness: true66legalized: true67body: |68 bb.0:69 liveins: $w0, $w170 ; Post-legalization, we must not crash here.71 ; CHECK-LABEL: name: dont_combine_physreg72 ; CHECK: liveins: $w0, $w173 ; CHECK-NEXT: {{ $}}74 ; CHECK-NEXT: %x:_(s32) = COPY $w075 ; CHECK-NEXT: %y:_(s32) = COPY $w176 ; CHECK-NEXT: %logic_op:_(s32) = G_OR %x, %y77 ; CHECK-NEXT: $w0 = COPY %logic_op(s32)78 ; CHECK-NEXT: RET_ReallyLR implicit $w079 %x:_(s32) = COPY $w080 %y:_(s32) = COPY $w181 %logic_op:_(s32) = G_OR %x, %y82 $w0 = COPY %logic_op(s32)83 RET_ReallyLR implicit $w084