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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner --aarch64postlegalizercombiner-only-enable-rule="rotate_out_of_range" -verify-machineinstrs %s -o - | FileCheck %s3# REQUIRES: asserts4 5# Check that we simplify the constant rotate amount to be in range.6---7name: rotl8alignment: 49legalized: true10tracksRegLiveness: true11liveins:12 - { reg: '$w0' }13body: |14 bb.1.entry:15 liveins: $w016 17 ; CHECK-LABEL: name: rotl18 ; CHECK: liveins: $w019 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w021 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1622 ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)23 ; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)24 ; CHECK-NEXT: RET_ReallyLR implicit $w025 %0:_(s32) = COPY $w026 %5:_(s64) = G_CONSTANT i64 -1627 %2:_(s32) = G_ROTL %0, %5(s64)28 $w0 = COPY %2(s32)29 RET_ReallyLR implicit $w030 31...32---33name: rotr34alignment: 435legalized: true36tracksRegLiveness: true37liveins:38 - { reg: '$w0' }39body: |40 bb.1.entry:41 liveins: $w042 43 ; CHECK-LABEL: name: rotr44 ; CHECK: liveins: $w045 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w047 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1648 ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[C]](s64)49 ; CHECK-NEXT: $w0 = COPY [[ROTR]](s32)50 ; CHECK-NEXT: RET_ReallyLR implicit $w051 %0:_(s32) = COPY $w052 %5:_(s64) = G_CONSTANT i64 -1653 %2:_(s32) = G_ROTR %0, %5(s64)54 $w0 = COPY %2(s32)55 RET_ReallyLR implicit $w056 57...58---59name: rotl_bitwidth_cst60alignment: 461legalized: true62tracksRegLiveness: true63liveins:64 - { reg: '$w0' }65body: |66 bb.1.entry:67 liveins: $w068 69 ; CHECK-LABEL: name: rotl_bitwidth_cst70 ; CHECK: liveins: $w071 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w073 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 074 ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)75 ; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)76 ; CHECK-NEXT: RET_ReallyLR implicit $w077 %0:_(s32) = COPY $w078 %5:_(s64) = G_CONSTANT i64 3279 %2:_(s32) = G_ROTL %0, %5(s64)80 $w0 = COPY %2(s32)81 RET_ReallyLR implicit $w082 83...84---85name: rotl_bitwidth_minus_one_cst86alignment: 487legalized: true88tracksRegLiveness: true89liveins:90 - { reg: '$w0' }91body: |92 bb.1.entry:93 liveins: $w094 95 ; CHECK-LABEL: name: rotl_bitwidth_minus_one_cst96 ; CHECK: liveins: $w097 ; CHECK-NEXT: {{ $}}98 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w099 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31100 ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[C]](s64)101 ; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)102 ; CHECK-NEXT: RET_ReallyLR implicit $w0103 %0:_(s32) = COPY $w0104 %5:_(s64) = G_CONSTANT i64 31105 %2:_(s32) = G_ROTL %0, %5(s64)106 $w0 = COPY %2(s32)107 RET_ReallyLR implicit $w0108 109...110