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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s3---4name: pluto5alignment: 46legalized: true7regBankSelected: true8selected: true9tracksRegLiveness: true10liveins:11 - { reg: '$x0' }12 - { reg: '$w1' }13 - { reg: '$x2' }14frameInfo:15 maxAlignment: 116 maxCallFrameSize: 017body: |18 ; CHECK-LABEL: name: pluto19 ; CHECK: bb.0:20 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)21 ; CHECK-NEXT: liveins: $w1, $x0, $x222 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x024 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY $w125 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY $x226 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF27 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[DEF]]28 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 87241523229 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]30 ; CHECK-NEXT: FCMPSrr [[COPY3]], [[COPY4]], implicit-def $nzcv, implicit $fpcr31 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv32 ; CHECK-NEXT: [[SUBWri:%[0-9]+]]:gpr32common = SUBWri [[COPY1]], 1, 033 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBWri]], %subreg.sub_3234 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[DEF]]35 ; CHECK-NEXT: FCMPSrr [[COPY5]], [[COPY4]], implicit-def $nzcv, implicit $fpcr36 ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv37 ; CHECK-NEXT: [[EORWrr:%[0-9]+]]:gpr32 = EORWrr [[CSINCWr]], [[CSINCWr1]]38 ; CHECK-NEXT: TBNZW [[EORWrr]], 0, %bb.239 ; CHECK-NEXT: B %bb.140 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: bb.1:42 ; CHECK-NEXT: successors: %bb.2(0x80000000)43 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 60, 5945 ; CHECK-NEXT: [[LDRSroX:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], [[UBFMXri]], 0, 0 :: (load (s32))46 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[DEF]]47 ; CHECK-NEXT: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY6]], [[LDRSroX]], implicit $fpcr48 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:fpr32 = COPY [[DEF]]49 ; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[FMULSrr]], [[COPY7]], implicit $fpcr50 ; CHECK-NEXT: STRSui [[FADDSrr]], [[COPY2]], 0 :: (store (s32))51 ; CHECK-NEXT: {{ $}}52 ; CHECK-NEXT: bb.2:53 ; CHECK-NEXT: RET_ReallyLR54 bb.1:55 liveins: $w1, $x0, $x256 57 %0:gpr64sp = COPY $x058 %1:gpr32sp = COPY $w159 %2:gpr64sp = COPY $x260 %3:gpr32 = IMPLICIT_DEF61 %29:fpr32 = COPY %362 %33:gpr32 = MOVi32imm 87241523263 %4:fpr32 = COPY %3364 FCMPSrr %29, %4, implicit-def $nzcv, implicit $fpcr65 %28:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv66 %7:gpr32 = SUBSWri %1, 1, 0, implicit-def $nzcv67 %8:gpr64 = SUBREG_TO_REG 0, %7, %subreg.sub_3268 %30:fpr32 = COPY %369 FCMPSrr %30, %4, implicit-def $nzcv, implicit $fpcr70 %27:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv71 %26:gpr32 = EORWrr %28, %2772 TBNZW %26, 0, %bb.373 B %bb.274 75 bb.2:76 %12:gpr64 = UBFMXri %8, 60, 5977 %15:fpr32 = LDRSroX %0, %12, 0, 0 :: (load (s32))78 %31:fpr32 = COPY %379 %16:fpr32 = FMULSrr %31, %15, implicit $fpcr80 %32:fpr32 = COPY %381 %17:fpr32 = FADDSrr %16, %32, implicit $fpcr82 STRSui %17, %2, 0 :: (store (s32))83 84 bb.3:85 RET_ReallyLR86 87...88