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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s3---4name: test_fcmp_dead_cc5alignment: 46legalized: true7regBankSelected: true8selected: true9tracksRegLiveness: true10liveins:11 - { reg: '$x0' }12 - { reg: '$w1' }13body: |14 bb.1:15 liveins: $w1, $x0, $s0, $s116 17 ; CHECK-LABEL: name: test_fcmp_dead_cc18 ; CHECK: liveins: $w1, $x0, $s0, $s119 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x021 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w122 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s023 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $s124 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr25 ; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr26 ; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]27 ; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr28 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 3129 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 130 ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv31 ; CHECK-NEXT: $w0 = COPY [[CSELWr]]32 ; CHECK-NEXT: RET_ReallyLR implicit $w033 %1:gpr64 = COPY $x034 %2:gpr32 = COPY $w135 %3:fpr32 = COPY $s036 %4:fpr32 = COPY $s137 %26:gpr32 = COPY $wzr38 FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr39 %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv40 FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr41 %14:gpr32common = UBFMWri %12, 1, 3142 %60:gpr32 = MOVi32imm 143 %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv44 $w0 = COPY %1645 RET_ReallyLR implicit $w046 47...48---49name: test_fcmp_64_dead_cc50alignment: 451legalized: true52regBankSelected: true53selected: true54tracksRegLiveness: true55liveins:56 - { reg: '$x0' }57 - { reg: '$w1' }58body: |59 bb.1:60 liveins: $w1, $x0, $d0, $d161 62 ; CHECK-LABEL: name: test_fcmp_64_dead_cc63 ; CHECK: liveins: $w1, $x0, $d0, $d164 ; CHECK-NEXT: {{ $}}65 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x066 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w167 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d068 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d169 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr70 ; CHECK-NEXT: FCMPDrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr71 ; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]72 ; CHECK-NEXT: FCMPDrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr73 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 3174 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 175 ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv76 ; CHECK-NEXT: $w0 = COPY [[CSELWr]]77 ; CHECK-NEXT: RET_ReallyLR implicit $w078 %1:gpr64 = COPY $x079 %2:gpr32 = COPY $w180 %3:fpr64 = COPY $d081 %4:fpr64 = COPY $d182 %26:gpr32 = COPY $wzr83 FCMPDrr %3, %4, implicit-def $nzcv, implicit $fpcr84 %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv85 FCMPDrr %3, %4, implicit-def $nzcv, implicit $fpcr86 %14:gpr32common = UBFMWri %12, 1, 3187 %60:gpr32 = MOVi32imm 188 %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv89 $w0 = COPY %1690 RET_ReallyLR implicit $w091 92...93---94name: test_fcmp_dead_cc_3_fcmps95alignment: 496legalized: true97regBankSelected: true98selected: true99tracksRegLiveness: true100liveins:101 - { reg: '$x0' }102 - { reg: '$w1' }103body: |104 bb.1:105 liveins: $w1, $x0, $s0, $s1106 107 ; CHECK-LABEL: name: test_fcmp_dead_cc_3_fcmps108 ; CHECK: liveins: $w1, $x0, $s0, $s1109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0111 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1112 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0113 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1114 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr115 ; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr116 ; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]117 ; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr118 ; CHECK-NEXT: [[SUBWrr1:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]119 ; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr120 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr1]], 1, 31121 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1122 ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv123 ; CHECK-NEXT: $w0 = COPY [[CSELWr]]124 ; CHECK-NEXT: RET_ReallyLR implicit $w0125 %1:gpr64 = COPY $x0126 %2:gpr32 = COPY $w1127 %3:fpr32 = COPY $s0128 %4:fpr32 = COPY $s1129 %26:gpr32 = COPY $wzr130 FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr131 %12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv132 FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr133 %13:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv134 FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr135 %14:gpr32common = UBFMWri %13, 1, 31136 %60:gpr32 = MOVi32imm 1137 %16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv138 $w0 = COPY %16139 RET_ReallyLR implicit $w0140 141...142---143name: test_impdef_subsx144alignment: 4145legalized: true146regBankSelected: true147selected: true148tracksRegLiveness: true149body: |150 bb.1:151 liveins: $x0, $x1152 ; CHECK-LABEL: name: test_impdef_subsx153 ; CHECK: liveins: $x0, $x1154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0156 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1157 ; CHECK-NEXT: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr [[COPY]], [[COPY1]]158 ; CHECK-NEXT: $x0 = COPY [[SUBXrr]]159 ; CHECK-NEXT: RET_ReallyLR implicit $x0160 %1:gpr64 = COPY $x0161 %2:gpr64 = COPY $x1162 %4:gpr64 = SUBSXrr %1, %2, implicit-def $nzcv163 $x0 = COPY %4164 RET_ReallyLR implicit $x0165...166---167name: test_impdef_subsw168alignment: 4169legalized: true170regBankSelected: true171selected: true172tracksRegLiveness: true173body: |174 bb.1:175 liveins: $w0, $w1176 ; CHECK-LABEL: name: test_impdef_subsw177 ; CHECK: liveins: $w0, $w1178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $x0180 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $x1181 ; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY]], [[COPY1]]182 ; CHECK-NEXT: $w0 = COPY [[SUBWrr]]183 ; CHECK-NEXT: RET_ReallyLR implicit $w0184 %1:gpr32 = COPY $x0185 %2:gpr32 = COPY $x1186 %4:gpr32 = SUBSWrr %1, %2, implicit-def $nzcv187 $w0 = COPY %4188 RET_ReallyLR implicit $w0189...190---191name: test_impdef_addsx192alignment: 4193legalized: true194regBankSelected: true195selected: true196tracksRegLiveness: true197body: |198 bb.1:199 liveins: $x0, $x1200 ; CHECK-LABEL: name: test_impdef_addsx201 ; CHECK: liveins: $x0, $x1202 ; CHECK-NEXT: {{ $}}203 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0204 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1205 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]206 ; CHECK-NEXT: $x0 = COPY [[ADDXrr]]207 ; CHECK-NEXT: RET_ReallyLR implicit $x0208 %1:gpr64 = COPY $x0209 %2:gpr64 = COPY $x1210 %4:gpr64 = ADDSXrr %1, %2, implicit-def $nzcv211 $x0 = COPY %4212 RET_ReallyLR implicit $x0213...214---215name: test_impdef_addsw216alignment: 4217legalized: true218regBankSelected: true219selected: true220tracksRegLiveness: true221body: |222 bb.1:223 liveins: $w0, $w1224 ; CHECK-LABEL: name: test_impdef_addsw225 ; CHECK: liveins: $w0, $w1226 ; CHECK-NEXT: {{ $}}227 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $x0228 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $x1229 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]230 ; CHECK-NEXT: $w0 = COPY [[ADDWrr]]231 ; CHECK-NEXT: RET_ReallyLR implicit $w0232 %1:gpr32 = COPY $x0233 %2:gpr32 = COPY $x1234 %4:gpr32 = ADDSWrr %1, %2, implicit-def $nzcv235 $w0 = COPY %4236 RET_ReallyLR implicit $w0237...238---239name: test_impdef_adcsx240alignment: 4241legalized: true242regBankSelected: true243selected: true244tracksRegLiveness: true245body: |246 bb.1:247 liveins: $x0, $x1, $x2, $x3248 ; CHECK-LABEL: name: test_impdef_adcsx249 ; CHECK: liveins: $x0, $x1, $x2, $x3250 ; CHECK-NEXT: {{ $}}251 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0252 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1253 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2254 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3255 ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY2]], implicit-def $nzcv256 ; CHECK-NEXT: [[ADCXr:%[0-9]+]]:gpr64 = ADCXr [[COPY1]], [[COPY3]], implicit $nzcv257 ; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]258 ; CHECK-NEXT: $x1 = COPY [[ADCXr]]259 ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1260 %1:gpr64 = COPY $x0261 %2:gpr64 = COPY $x1262 %3:gpr64 = COPY $x2263 %4:gpr64 = COPY $x3264 %5:gpr64 = ADDSXrr %1, %3, implicit-def $nzcv265 %6:gpr64 = ADCSXr %2, %4, implicit-def $nzcv, implicit $nzcv266 $x0 = COPY %5267 $x1 = COPY %6268 RET_ReallyLR implicit $x0, implicit $x1269...270---271name: test_impdef_adcsw272alignment: 4273legalized: true274regBankSelected: true275selected: true276tracksRegLiveness: true277body: |278 bb.1:279 liveins: $w0, $w1, $w2, $w3280 ; CHECK-LABEL: name: test_impdef_adcsw281 ; CHECK: liveins: $w0, $w1, $w2, $w3282 ; CHECK-NEXT: {{ $}}283 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0284 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1285 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2286 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $w3287 ; CHECK-NEXT: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY2]], implicit-def $nzcv288 ; CHECK-NEXT: [[ADCWr:%[0-9]+]]:gpr32 = ADCWr [[COPY1]], [[COPY3]], implicit $nzcv289 ; CHECK-NEXT: $w0 = COPY [[ADDSWrr]]290 ; CHECK-NEXT: $w1 = COPY [[ADCWr]]291 ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1292 %1:gpr32 = COPY $w0293 %2:gpr32 = COPY $w1294 %3:gpr32 = COPY $w2295 %4:gpr32 = COPY $w3296 %5:gpr32 = ADDSWrr %1, %3, implicit-def $nzcv297 %6:gpr32 = ADCSWr %2, %4, implicit-def $nzcv, implicit $nzcv298 $w0 = COPY %5299 $w1 = COPY %6300 RET_ReallyLR implicit $w0, implicit $w1301...302---303name: test_impdef_sbcsx304alignment: 4305legalized: true306regBankSelected: true307selected: true308tracksRegLiveness: true309body: |310 bb.1:311 liveins: $x0, $x1, $x2, $x3312 ; CHECK-LABEL: name: test_impdef_sbcsx313 ; CHECK: liveins: $x0, $x1, $x2, $x3314 ; CHECK-NEXT: {{ $}}315 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0316 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1317 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2318 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3319 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY2]], implicit-def $nzcv320 ; CHECK-NEXT: [[SBCXr:%[0-9]+]]:gpr64 = SBCXr [[COPY1]], [[COPY3]], implicit $nzcv321 ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]322 ; CHECK-NEXT: $x1 = COPY [[SBCXr]]323 ; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1324 %1:gpr64 = COPY $x0325 %2:gpr64 = COPY $x1326 %3:gpr64 = COPY $x2327 %4:gpr64 = COPY $x3328 %5:gpr64 = SUBSXrr %1, %3, implicit-def $nzcv329 %6:gpr64 = SBCSXr %2, %4, implicit-def $nzcv, implicit $nzcv330 $x0 = COPY %5331 $x1 = COPY %6332 RET_ReallyLR implicit $x0, implicit $x1333...334---335name: test_impdef_sbcsw336alignment: 4337legalized: true338regBankSelected: true339selected: true340tracksRegLiveness: true341body: |342 bb.1:343 liveins: $w0, $w1, $w2, $w3344 ; CHECK-LABEL: name: test_impdef_sbcsw345 ; CHECK: liveins: $w0, $w1, $w2, $w3346 ; CHECK-NEXT: {{ $}}347 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0348 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1349 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2350 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $w3351 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY2]], implicit-def $nzcv352 ; CHECK-NEXT: [[SBCWr:%[0-9]+]]:gpr32 = SBCWr [[COPY1]], [[COPY3]], implicit $nzcv353 ; CHECK-NEXT: $w0 = COPY [[SUBSWrr]]354 ; CHECK-NEXT: $w1 = COPY [[SBCWr]]355 ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1356 %1:gpr32 = COPY $w0357 %2:gpr32 = COPY $w1358 %3:gpr32 = COPY $w2359 %4:gpr32 = COPY $w3360 %5:gpr32 = SUBSWrr %1, %3, implicit-def $nzcv361 %6:gpr32 = SBCSWr %2, %4, implicit-def $nzcv, implicit $nzcv362 $w0 = COPY %5363 $w1 = COPY %6364 RET_ReallyLR implicit $w0, implicit $w1365...366