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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: test6alignment: 47tracksRegLiveness: true8body: |9 bb.1:10 ; CHECK-LABEL: name: test11 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 112 ; CHECK-NEXT: $w0 = COPY [[C]](s32)13 ; CHECK-NEXT: RET_ReallyLR implicit $w014 %0:_(s16) = G_CONSTANT i16 015 %2:_(s1) = G_CONSTANT i1 true16 %1:_(s1) = G_ICMP intpred(sge), %0(s16), %017 %3:_(s8) = G_SEXT %2(s1)18 %4:_(s32) = G_SEXT %3(s8)19 %5:_(s32) = G_SEXT %1(s1)20 %6:_(s32) = G_UDIV %4, %521 %7:_(s32) = COPY %5(s32)22 %8:_(s32) = G_SEXT %2(s1)23 %9:_(s32) = G_UREM %7, %824 %10:_(s8) = G_TRUNC %9(s32)25 %11:_(s64) = G_ZEXT %6(s32)26 %12:_(s64) = G_SEXT %10(s8)27 %13:_(s64) = G_OR %11, %1228 %14:_(s32) = G_TRUNC %13(s64)29 $w0 = COPY %14(s32)30 RET_ReallyLR implicit $w031 32...33 34# Check with the div and rem the other way around35---36name: test_inverted_div_rem37alignment: 438tracksRegLiveness: true39body: |40 bb.1:41 ; CHECK-LABEL: name: test_inverted_div_rem42 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 143 ; CHECK-NEXT: $w0 = COPY [[C]](s32)44 ; CHECK-NEXT: RET_ReallyLR implicit $w045 %0:_(s16) = G_CONSTANT i16 046 %2:_(s1) = G_CONSTANT i1 true47 %1:_(s1) = G_ICMP intpred(sge), %0(s16), %048 %3:_(s8) = G_SEXT %2(s1)49 %4:_(s32) = G_SEXT %3(s8)50 %5:_(s32) = G_SEXT %1(s1)51 %6:_(s32) = G_UREM %4, %552 %7:_(s32) = COPY %5(s32)53 %8:_(s32) = G_SEXT %2(s1)54 %9:_(s32) = G_UDIV %7, %855 %10:_(s8) = G_TRUNC %9(s32)56 %11:_(s64) = G_ZEXT %6(s32)57 %12:_(s64) = G_SEXT %10(s8)58 %13:_(s64) = G_OR %11, %1259 %14:_(s32) = G_TRUNC %13(s64)60 $w0 = COPY %14(s32)61 RET_ReallyLR implicit $w062 63...64