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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3---4name: ashr_shl_to_sext_inreg5alignment: 46tracksRegLiveness: true7liveins:8 - { reg: '$w0' }9body: |10 bb.1:11 liveins: $w012 13 ; CHECK-LABEL: name: ashr_shl_to_sext_inreg14 ; CHECK: liveins: $w015 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w017 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)18 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[TRUNC]], 819 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16)20 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)21 ; CHECK-NEXT: RET_ReallyLR implicit $w022 %1:_(s32) = COPY $w023 %0:_(s16) = G_TRUNC %1(s32)24 %2:_(s16) = G_CONSTANT i16 825 %3:_(s16) = G_SHL %0, %2(s16)26 %4:_(s16) = exact G_ASHR %3, %2(s16)27 %5:_(s32) = G_ANYEXT %4(s16)28 $w0 = COPY %5(s32)29 RET_ReallyLR implicit $w030 31...32---33name: different_shift_amts34alignment: 435tracksRegLiveness: true36liveins:37 - { reg: '$w0' }38body: |39 bb.1:40 liveins: $w041 42 ; CHECK-LABEL: name: different_shift_amts43 ; CHECK: liveins: $w044 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w046 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)47 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1248 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 849 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)50 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s16) = exact G_ASHR [[SHL]], [[C1]](s16)51 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)52 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)53 ; CHECK-NEXT: RET_ReallyLR implicit $w054 %1:_(s32) = COPY $w055 %0:_(s16) = G_TRUNC %1(s32)56 %2:_(s16) = G_CONSTANT i16 1257 %4:_(s16) = G_CONSTANT i16 858 %3:_(s16) = G_SHL %0, %2(s16)59 %5:_(s16) = exact G_ASHR %3, %4(s16)60 %6:_(s32) = G_ANYEXT %5(s16)61 $w0 = COPY %6(s32)62 RET_ReallyLR implicit $w063 64...65---66name: ashr_shl_to_sext_inreg_vector67alignment: 468tracksRegLiveness: true69liveins:70 - { reg: '$d0' }71body: |72 bb.1:73 liveins: $d074 ; CHECK-LABEL: name: ashr_shl_to_sext_inreg_vector75 ; CHECK: liveins: $d076 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d078 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s16>) = G_SEXT_INREG [[COPY]], 879 ; CHECK-NEXT: $d0 = COPY [[SEXT_INREG]](<4 x s16>)80 ; CHECK-NEXT: RET_ReallyLR implicit $d081 %0:_(<4 x s16>) = COPY $d082 %2:_(s16) = G_CONSTANT i16 883 %1:_(<4 x s16>) = G_BUILD_VECTOR %2(s16), %2(s16), %2(s16), %2(s16)84 %3:_(<4 x s16>) = G_SHL %0, %1(<4 x s16>)85 %4:_(<4 x s16>) = exact G_ASHR %3, %1(<4 x s16>)86 $d0 = COPY %4(<4 x s16>)87 RET_ReallyLR implicit $d088...89