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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -debugify-and-strip-all-safe -O0 -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="opt_brcond_by_inverting_cond" -global-isel -verify-machineinstrs %s -o - | FileCheck %s3 4# Need asserts for the only-enable-rule to work.5 6# REQUIRES: asserts7 8--- |9 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"10 target triple = "arm64-apple-ios5.0.0"11 12 define i32 @foo(i32 %a, i32 %b) {13 entry:14 %cmp = icmp sgt i32 %a, 015 br i1 %cmp, label %if.then, label %if.end16 17 if.then:18 %add = add nsw i32 %b, %a19 %add1 = add nsw i32 %a, %b20 br label %return21 22 if.end:23 %mul = mul nsw i32 %b, %b24 %add2 = add nuw nsw i32 %mul, 225 br label %return26 27 return:28 %retval.0 = phi i32 [ %add1, %if.then ], [ %add2, %if.end ]29 ret i32 %retval.030 }31 32 define void @dont_combine_same_block() { ret void }33 34...35---36name: foo37tracksRegLiveness: true38body: |39 ; CHECK-LABEL: name: foo40 ; CHECK: bb.0.entry:41 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)42 ; CHECK-NEXT: liveins: $w0, $w143 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w045 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w146 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 047 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 248 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]49 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true50 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C2]]51 ; CHECK-NEXT: G_BRCOND [[XOR]](s1), %bb.252 ; CHECK-NEXT: G_BR %bb.153 ; CHECK-NEXT: {{ $}}54 ; CHECK-NEXT: bb.1.if.then:55 ; CHECK-NEXT: successors: %bb.3(0x80000000)56 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY1]], [[COPY]]58 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = nsw G_ADD [[ADD]], [[COPY1]]59 ; CHECK-NEXT: G_BR %bb.360 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: bb.2.if.end:62 ; CHECK-NEXT: successors: %bb.3(0x80000000)63 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY1]], [[COPY1]]65 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[MUL]], [[C1]]66 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: bb.3.return:68 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.1, [[ADD2]](s32), %bb.269 ; CHECK-NEXT: $w0 = COPY [[PHI]](s32)70 ; CHECK-NEXT: RET_ReallyLR implicit $w071 bb.1.entry:72 liveins: $w0, $w173 74 %0:_(s32) = COPY $w075 %1:_(s32) = COPY $w176 %2:_(s32) = G_CONSTANT i32 077 %5:_(s32) = G_CONSTANT i32 278 %3:_(s1) = G_ICMP intpred(sgt), %0(s32), %279 G_BRCOND %3(s1), %bb.280 G_BR %bb.381 82 bb.2.if.then:83 %7:_(s32) = nsw G_ADD %1, %084 %8:_(s32) = nsw G_ADD %7, %185 G_BR %bb.486 87 bb.3.if.end:88 %4:_(s32) = nsw G_MUL %1, %189 %6:_(s32) = nuw nsw G_ADD %4, %590 91 bb.4.return:92 %10:_(s32) = G_PHI %8(s32), %bb.2, %6(s32), %bb.393 $w0 = COPY %10(s32)94 RET_ReallyLR implicit $w095 96...97---98name: dont_combine_same_block99tracksRegLiveness: true100body: |101 ; CHECK-LABEL: name: dont_combine_same_block102 ; CHECK: bb.0:103 ; CHECK-NEXT: successors: %bb.1(0x80000000)104 ; CHECK-NEXT: liveins: $w0, $w1105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: %cond:_(s1) = G_IMPLICIT_DEF107 ; CHECK-NEXT: G_BRCOND %cond(s1), %bb.1108 ; CHECK-NEXT: G_BR %bb.1109 ; CHECK-NEXT: {{ $}}110 ; CHECK-NEXT: bb.1:111 ; CHECK-NEXT: RET_ReallyLR112 bb.0:113 liveins: $w0, $w1114 %cond:_(s1) = G_IMPLICIT_DEF115 116 G_BRCOND %cond(s1), %bb.1117 G_BR %bb.1118 bb.1:119 RET_ReallyLR120...121