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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 22# RUN: llc -mtriple aarch64 -mattr=+fullfp16 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3---4name: shl_add_k5alignment: 46tracksRegLiveness: true7body: |8 bb.1:9 liveins: $w1, $x010 11 ; CHECK-LABEL: name: shl_add_k12 ; CHECK: liveins: $w1, $x013 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x015 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w116 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 217 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)18 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 419 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[C1]]20 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[COPY]](p0) :: (store (s32))21 ; CHECK-NEXT: RET_ReallyLR22 %0:_(p0) = COPY $x023 %1:_(s32) = COPY $w124 %2:_(s32) = G_CONSTANT i32 125 %4:_(s32) = G_CONSTANT i32 226 %3:_(s32) = G_ADD %1, %227 %5:_(s32) = G_SHL %3, %4(s32)28 G_STORE %5(s32), %0(p0) :: (store (s32))29 RET_ReallyLR30 31...32---33name: shl_or_k34alignment: 435tracksRegLiveness: true36body: |37 bb.1:38 liveins: $w1, $x039 40 ; CHECK-LABEL: name: shl_or_k41 ; CHECK: liveins: $w1, $x042 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x044 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w145 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 246 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)47 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 448 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[C1]]49 ; CHECK-NEXT: G_STORE [[OR]](s32), [[COPY]](p0) :: (store (s32))50 ; CHECK-NEXT: RET_ReallyLR51 %0:_(p0) = COPY $x052 %1:_(s32) = COPY $w153 %2:_(s32) = G_CONSTANT i32 154 %4:_(s32) = G_CONSTANT i32 255 %3:_(s32) = G_OR %1, %256 %5:_(s32) = G_SHL %3, %4(s32)57 G_STORE %5(s32), %0(p0) :: (store (s32))58 RET_ReallyLR59 60...61---62name: shl_or_k_multiuse63alignment: 464tracksRegLiveness: true65body: |66 bb.1:67 liveins: $w1, $x068 69 ; CHECK-LABEL: name: shl_or_k_multiuse70 ; CHECK: liveins: $w1, $x071 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x073 ; CHECK-NEXT: %ptr:_(p0) = COPY $x174 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w175 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 176 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 277 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[C]]78 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C1]](s32)79 ; CHECK-NEXT: G_STORE [[SHL]](s32), [[COPY]](p0) :: (store (s32))80 ; CHECK-NEXT: G_STORE [[OR]](s32), %ptr(p0) :: (store (s32))81 ; CHECK-NEXT: RET_ReallyLR82 %0:_(p0) = COPY $x083 %ptr:_(p0) = COPY $x184 %1:_(s32) = COPY $w185 %2:_(s32) = G_CONSTANT i32 186 %4:_(s32) = G_CONSTANT i32 287 %3:_(s32) = G_OR %1, %288 %5:_(s32) = G_SHL %3, %4(s32)89 G_STORE %5(s32), %0(p0) :: (store (s32))90 G_STORE %3(s32), %ptr(p0) :: (store (s32))91 RET_ReallyLR92 93...94---95name: shl_add_k_vector96alignment: 497tracksRegLiveness: true98body: |99 bb.1:100 liveins: $w1, $x0101 102 ; CHECK-LABEL: name: shl_add_k_vector103 ; CHECK: liveins: $w1, $x0104 ; CHECK-NEXT: {{ $}}105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0106 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1107 ; CHECK-NEXT: %xvec:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY1]](s32), [[COPY1]](s32), [[COPY1]](s32)108 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2109 ; CHECK-NEXT: %veccst2:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)110 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL %xvec, %veccst2(<4 x s32>)111 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8112 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)113 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[SHL]], [[BUILD_VECTOR]]114 ; CHECK-NEXT: G_STORE [[ADD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>))115 ; CHECK-NEXT: RET_ReallyLR116 %0:_(p0) = COPY $x0117 %1:_(s32) = COPY $w1118 %xvec:_(<4 x s32>) = G_BUILD_VECTOR %1, %1, %1, %1119 %2:_(s32) = G_CONSTANT i32 1120 %veccst:_(<4 x s32>) = G_BUILD_VECTOR %2, %2, %2, %2121 %4:_(s32) = G_CONSTANT i32 2122 %veccst2:_(<4 x s32>) = G_BUILD_VECTOR %4, %4, %4, %4123 %3:_(<4 x s32>) = G_ADD %xvec, %veccst2124 %5:_(<4 x s32>) = G_SHL %3, %veccst2125 G_STORE %5(<4 x s32>), %0(p0) :: (store (<4 x s32>))126 RET_ReallyLR127 128...129