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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s3 4# Check we don't try to combine a load of < s8 as that will end up creating a illegal non-extending load.5--- |6 define i8 @test(ptr %ptr) {7 ret i8 undef8 }9 10...11---12name: test13alignment: 414tracksRegLiveness: true15registers:16 - { id: 0, class: _ }17 - { id: 1, class: _ }18 - { id: 2, class: _ }19 - { id: 3, class: _ }20body: |21 bb.1 (%ir-block.0):22 liveins: $x023 24 ; CHECK-LABEL: name: test25 ; CHECK: liveins: $x026 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x028 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[COPY]](p0) :: (load (s1) from %ir.ptr)29 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s1)30 ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)31 ; CHECK-NEXT: RET_ReallyLR implicit $w032 %0:_(p0) = COPY $x033 %1:_(s1) = G_LOAD %0(p0) :: (load (s1) from %ir.ptr)34 %2:_(s8) = G_ZEXT %1(s1)35 %3:_(s32) = G_ANYEXT %2(s8)36 $w0 = COPY %3(s32)37 RET_ReallyLR implicit $w038 39...40