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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s3 4---5name: test_rotr6alignment: 47tracksRegLiveness: true8liveins:9 - { reg: '$w0' }10 - { reg: '$w1' }11frameInfo:12 maxAlignment: 113machineFunctionInfo: {}14body: |15 bb.1.entry:16 liveins: $w0, $w117 18 ; CHECK-LABEL: name: test_rotr19 ; CHECK: liveins: $w0, $w120 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w022 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w123 ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[COPY1]](s32)24 ; CHECK-NEXT: $w0 = COPY [[ROTR]](s32)25 ; CHECK-NEXT: RET_ReallyLR implicit $w026 %0:_(s32) = COPY $w027 %1:_(s32) = COPY $w128 %2:_(s32) = G_FSHR %0, %0, %1(s32)29 $w0 = COPY %2(s32)30 RET_ReallyLR implicit $w031 32...33---34name: test_rotl35alignment: 436tracksRegLiveness: true37liveins:38 - { reg: '$w0' }39 - { reg: '$w1' }40frameInfo:41 maxAlignment: 142machineFunctionInfo: {}43body: |44 bb.1.entry:45 liveins: $w0, $w146 47 ; CHECK-LABEL: name: test_rotl48 ; CHECK: liveins: $w0, $w149 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w051 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w152 ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[COPY1]](s32)53 ; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)54 ; CHECK-NEXT: RET_ReallyLR implicit $w055 %0:_(s32) = COPY $w056 %1:_(s32) = COPY $w157 %2:_(s32) = G_FSHL %0, %0, %1(s32)58 $w0 = COPY %2(s32)59 RET_ReallyLR implicit $w060 61...62---63name: test_vector_rotr64alignment: 465tracksRegLiveness: true66liveins:67 - { reg: '$w0' }68 - { reg: '$w1' }69frameInfo:70 maxAlignment: 171machineFunctionInfo: {}72body: |73 bb.1.entry:74 liveins: $q0, $q175 76 ; CHECK-LABEL: name: test_vector_rotr77 ; CHECK: liveins: $q0, $q178 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q080 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q181 ; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(<4 x s32>) = G_ROTR [[COPY]], [[COPY1]](<4 x s32>)82 ; CHECK-NEXT: $q0 = COPY [[ROTR]](<4 x s32>)83 ; CHECK-NEXT: RET_ReallyLR implicit $q084 %0:_(<4 x s32>) = COPY $q085 %1:_(<4 x s32>) = COPY $q186 %2:_(<4 x s32>) = G_FSHR %0, %0, %1(<4 x s32>)87 $q0 = COPY %2(<4 x s32>)88 RET_ReallyLR implicit $q089 90...91---92name: test_vector_rotl93alignment: 494tracksRegLiveness: true95liveins:96 - { reg: '$w0' }97 - { reg: '$w1' }98frameInfo:99 maxAlignment: 1100machineFunctionInfo: {}101body: |102 bb.1.entry:103 liveins: $q0, $q1104 105 ; CHECK-LABEL: name: test_vector_rotl106 ; CHECK: liveins: $q0, $q1107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0109 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1110 ; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(<4 x s32>) = G_ROTL [[COPY]], [[COPY1]](<4 x s32>)111 ; CHECK-NEXT: $q0 = COPY [[ROTL]](<4 x s32>)112 ; CHECK-NEXT: RET_ReallyLR implicit $q0113 %0:_(<4 x s32>) = COPY $q0114 %1:_(<4 x s32>) = COPY $q1115 %2:_(<4 x s32>) = G_FSHL %0, %0, %1(<4 x s32>)116 $q0 = COPY %2(<4 x s32>)117 RET_ReallyLR implicit $q0118 119...120