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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-PRE3# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-POST4 5---6name: or_combine_sext7# or (sext X), (sext Y) --> sext (or X, Y)8tracksRegLiveness: true9legalized: true10body: |11 bb.0:12 liveins: $w0, $w113 ; CHECK-LABEL: name: or_combine_sext14 ; CHECK: liveins: $w0, $w115 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: %x:_(s32) = COPY $w017 ; CHECK-NEXT: %y:_(s32) = COPY $w118 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y19 ; CHECK-NEXT: %logic_op:_(s64) = G_SEXT [[OR]](s32)20 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)21 ; CHECK-NEXT: RET_ReallyLR implicit $x022 %x:_(s32) = COPY $w023 %y:_(s32) = COPY $w124 %hand1:_(s64) = G_SEXT %x(s32)25 %hand2:_(s64) = G_SEXT %y(s32)26 %logic_op:_(s64) = G_OR %hand1, %hand227 $x0 = COPY %logic_op(s64)28 RET_ReallyLR implicit $x029 30...31---32name: or_combine_zext33# or (zext X), (zext Y) --> zext (or X, Y)34tracksRegLiveness: true35legalized: true36body: |37 bb.0:38 liveins: $w0, $w139 ; CHECK-LABEL: name: or_combine_zext40 ; CHECK: liveins: $w0, $w141 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: %x:_(s32) = COPY $w043 ; CHECK-NEXT: %y:_(s32) = COPY $w144 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y45 ; CHECK-NEXT: %logic_op:_(s64) = G_ZEXT [[OR]](s32)46 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)47 ; CHECK-NEXT: RET_ReallyLR implicit $x048 %x:_(s32) = COPY $w049 %y:_(s32) = COPY $w150 %hand1:_(s64) = G_ZEXT %x(s32)51 %hand2:_(s64) = G_ZEXT %y(s32)52 %logic_op:_(s64) = G_OR %hand1, %hand253 $x0 = COPY %logic_op(s64)54 RET_ReallyLR implicit $x055 56...57---58name: or_combine_anyext59# or (anyext X), (anyext Y) --> anyext (or X, Y)60tracksRegLiveness: true61legalized: true62body: |63 bb.0:64 liveins: $w0, $w165 ; CHECK-LABEL: name: or_combine_anyext66 ; CHECK: liveins: $w0, $w167 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: %x:_(s32) = COPY $w069 ; CHECK-NEXT: %y:_(s32) = COPY $w170 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y71 ; CHECK-NEXT: %logic_op:_(s64) = G_ANYEXT [[OR]](s32)72 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)73 ; CHECK-NEXT: RET_ReallyLR implicit $x074 %x:_(s32) = COPY $w075 %y:_(s32) = COPY $w176 %hand1:_(s64) = G_ANYEXT %x(s32)77 %hand2:_(s64) = G_ANYEXT %y(s32)78 %logic_op:_(s64) = G_OR %hand1, %hand279 $x0 = COPY %logic_op(s64)80 RET_ReallyLR implicit $x081 82...83---84name: and_combine_sext85# and (sext X), (sext Y) --> sext (and X, Y)86tracksRegLiveness: true87legalized: true88body: |89 bb.0:90 liveins: $w0, $w191 ; CHECK-LABEL: name: and_combine_sext92 ; CHECK: liveins: $w0, $w193 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: %x:_(s32) = COPY $w095 ; CHECK-NEXT: %y:_(s32) = COPY $w196 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %x, %y97 ; CHECK-NEXT: %logic_op:_(s64) = G_SEXT [[AND]](s32)98 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)99 ; CHECK-NEXT: RET_ReallyLR implicit $x0100 %x:_(s32) = COPY $w0101 %y:_(s32) = COPY $w1102 %hand1:_(s64) = G_SEXT %x(s32)103 %hand2:_(s64) = G_SEXT %y(s32)104 %logic_op:_(s64) = G_AND %hand1, %hand2105 $x0 = COPY %logic_op(s64)106 RET_ReallyLR implicit $x0107 108...109---110name: and_combine_zext111# and (zext X), (zext Y) --> zext (and X, Y)112tracksRegLiveness: true113legalized: true114body: |115 bb.0:116 liveins: $w0, $w1117 ; CHECK-LABEL: name: and_combine_zext118 ; CHECK: liveins: $w0, $w1119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: %x:_(s32) = COPY $w0121 ; CHECK-NEXT: %y:_(s32) = COPY $w1122 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %x, %y123 ; CHECK-NEXT: %logic_op:_(s64) = G_ZEXT [[AND]](s32)124 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)125 ; CHECK-NEXT: RET_ReallyLR implicit $x0126 %x:_(s32) = COPY $w0127 %y:_(s32) = COPY $w1128 %hand1:_(s64) = G_ZEXT %x(s32)129 %hand2:_(s64) = G_ZEXT %y(s32)130 %logic_op:_(s64) = G_AND %hand1, %hand2131 $x0 = COPY %logic_op(s64)132 RET_ReallyLR implicit $x0133 134...135---136name: and_combine_anyext137# and (anyext X), (anyext Y) --> anyext (and X, Y)138tracksRegLiveness: true139legalized: true140body: |141 bb.0:142 liveins: $w0, $w1143 ; CHECK-LABEL: name: and_combine_anyext144 ; CHECK: liveins: $w0, $w1145 ; CHECK-NEXT: {{ $}}146 ; CHECK-NEXT: %x:_(s32) = COPY $w0147 ; CHECK-NEXT: %y:_(s32) = COPY $w1148 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND %x, %y149 ; CHECK-NEXT: %logic_op:_(s64) = G_ANYEXT [[AND]](s32)150 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)151 ; CHECK-NEXT: RET_ReallyLR implicit $x0152 %x:_(s32) = COPY $w0153 %y:_(s32) = COPY $w1154 %hand1:_(s64) = G_ANYEXT %x(s32)155 %hand2:_(s64) = G_ANYEXT %y(s32)156 %logic_op:_(s64) = G_AND %hand1, %hand2157 $x0 = COPY %logic_op(s64)158 RET_ReallyLR implicit $x0159 160...161---162name: xor_combine_sext163# xor (sext X), (sext Y) --> sext (xor X, Y)164tracksRegLiveness: true165legalized: true166body: |167 bb.0:168 liveins: $w0, $w1169 ; CHECK-LABEL: name: xor_combine_sext170 ; CHECK: liveins: $w0, $w1171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: %x:_(s32) = COPY $w0173 ; CHECK-NEXT: %y:_(s32) = COPY $w1174 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, %y175 ; CHECK-NEXT: %logic_op:_(s64) = G_SEXT [[XOR]](s32)176 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)177 ; CHECK-NEXT: RET_ReallyLR implicit $x0178 %x:_(s32) = COPY $w0179 %y:_(s32) = COPY $w1180 %hand1:_(s64) = G_SEXT %x(s32)181 %hand2:_(s64) = G_SEXT %y(s32)182 %logic_op:_(s64) = G_XOR %hand1, %hand2183 $x0 = COPY %logic_op(s64)184 RET_ReallyLR implicit $x0185 186...187---188name: xor_combine_zext189# xor (zext X), (zext Y) --> zext (xor X, Y)190tracksRegLiveness: true191legalized: true192body: |193 bb.0:194 liveins: $w0, $w1195 ; CHECK-LABEL: name: xor_combine_zext196 ; CHECK: liveins: $w0, $w1197 ; CHECK-NEXT: {{ $}}198 ; CHECK-NEXT: %x:_(s32) = COPY $w0199 ; CHECK-NEXT: %y:_(s32) = COPY $w1200 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, %y201 ; CHECK-NEXT: %logic_op:_(s64) = G_ZEXT [[XOR]](s32)202 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)203 ; CHECK-NEXT: RET_ReallyLR implicit $x0204 %x:_(s32) = COPY $w0205 %y:_(s32) = COPY $w1206 %hand1:_(s64) = G_ZEXT %x(s32)207 %hand2:_(s64) = G_ZEXT %y(s32)208 %logic_op:_(s64) = G_XOR %hand1, %hand2209 $x0 = COPY %logic_op(s64)210 RET_ReallyLR implicit $x0211 212...213---214name: xor_combine_anyext215# xor (anyext X), (anyext Y) --> anyext (xor X, Y)216tracksRegLiveness: true217legalized: true218body: |219 bb.0:220 liveins: $w0, $w1221 ; CHECK-LABEL: name: xor_combine_anyext222 ; CHECK: liveins: $w0, $w1223 ; CHECK-NEXT: {{ $}}224 ; CHECK-NEXT: %x:_(s32) = COPY $w0225 ; CHECK-NEXT: %y:_(s32) = COPY $w1226 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, %y227 ; CHECK-NEXT: %logic_op:_(s64) = G_ANYEXT [[XOR]](s32)228 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)229 ; CHECK-NEXT: RET_ReallyLR implicit $x0230 %x:_(s32) = COPY $w0231 %y:_(s32) = COPY $w1232 %hand1:_(s64) = G_ANYEXT %x(s32)233 %hand2:_(s64) = G_ANYEXT %y(s32)234 %logic_op:_(s64) = G_XOR %hand1, %hand2235 $x0 = COPY %logic_op(s64)236 RET_ReallyLR implicit $x0237 238...239---240name: dont_combine_different_types241# When %x and %y don't have the same type, don't perform the combine.242tracksRegLiveness: true243legalized: true244body: |245 bb.0:246 liveins: $w0, $w1247 ; CHECK-LABEL: name: dont_combine_different_types248 ; CHECK: liveins: $w0, $w1249 ; CHECK-NEXT: {{ $}}250 ; CHECK-NEXT: %x:_(s32) = COPY $w0251 ; CHECK-NEXT: %hand1:_(s32) = COPY $w1252 ; CHECK-NEXT: %y:_(s16) = G_TRUNC %hand1(s32)253 ; CHECK-NEXT: %hand2:_(s64) = G_SEXT %x(s32)254 ; CHECK-NEXT: %logic_op:_(s64) = G_SEXT %y(s16)255 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR %hand2, %logic_op256 ; CHECK-NEXT: $x0 = COPY [[OR]](s64)257 ; CHECK-NEXT: RET_ReallyLR implicit $x0258 %x:_(s32) = COPY $w0259 %hand1:_(s32) = COPY $w1260 %y:_(s16) = G_TRUNC %hand1(s32)261 %hand2:_(s64) = G_SEXT %x(s32)262 %logic_op:_(s64) = G_SEXT %y(s16)263 %5:_(s64) = G_OR %hand2, %logic_op264 $x0 = COPY %5(s64)265 RET_ReallyLR implicit $x0266 267...268---269name: illegal_ty270# Pre-legalization, it's okay to produce illegal types.271tracksRegLiveness: true272legalized: true273body: |274 bb.0:275 liveins: $w0, $w1276 ; CHECK-PRE-LABEL: name: illegal_ty277 ; CHECK-PRE: liveins: $w0, $w1278 ; CHECK-PRE-NEXT: {{ $}}279 ; CHECK-PRE-NEXT: %x_wide:_(s32) = COPY $w0280 ; CHECK-PRE-NEXT: %y_wide:_(s32) = COPY $w1281 ; CHECK-PRE-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR %x_wide, %y_wide282 ; CHECK-PRE-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[OR]](s32)283 ; CHECK-PRE-NEXT: %logic_op:_(s64) = G_SEXT [[TRUNC]](s1)284 ; CHECK-PRE-NEXT: $x0 = COPY %logic_op(s64)285 ; CHECK-PRE-NEXT: RET_ReallyLR implicit $x0286 ;287 ; CHECK-POST-LABEL: name: illegal_ty288 ; CHECK-POST: liveins: $w0, $w1289 ; CHECK-POST-NEXT: {{ $}}290 ; CHECK-POST-NEXT: %x_wide:_(s32) = COPY $w0291 ; CHECK-POST-NEXT: %y_wide:_(s32) = COPY $w1292 ; CHECK-POST-NEXT: %x:_(s1) = G_TRUNC %x_wide(s32)293 ; CHECK-POST-NEXT: %y:_(s1) = G_TRUNC %y_wide(s32)294 ; CHECK-POST-NEXT: %hand1:_(s64) = G_SEXT %x(s1)295 ; CHECK-POST-NEXT: %hand2:_(s64) = G_SEXT %y(s1)296 ; CHECK-POST-NEXT: %logic_op:_(s64) = G_OR %hand1, %hand2297 ; CHECK-POST-NEXT: $x0 = COPY %logic_op(s64)298 ; CHECK-POST-NEXT: RET_ReallyLR implicit $x0299 %x_wide:_(s32) = COPY $w0300 %y_wide:_(s32) = COPY $w1301 %x:_(s1) = G_TRUNC %x_wide302 %y:_(s1) = G_TRUNC %y_wide303 %hand1:_(s64) = G_SEXT %x(s1)304 %hand2:_(s64) = G_SEXT %y(s1)305 %logic_op:_(s64) = G_OR %hand1, %hand2306 $x0 = COPY %logic_op(s64)307 RET_ReallyLR implicit $x0308 309...310---311name: or_combine_and312# or (and x, z), (and y, z) --> and (or x, y), z313tracksRegLiveness: true314legalized: true315body: |316 bb.0:317 liveins: $x0, $x1, $x2318 ; CHECK-LABEL: name: or_combine_and319 ; CHECK: liveins: $x0, $x1, $x2320 ; CHECK-NEXT: {{ $}}321 ; CHECK-NEXT: %x:_(s64) = COPY $x0322 ; CHECK-NEXT: %y:_(s64) = COPY $x1323 ; CHECK-NEXT: %z:_(s64) = COPY $x2324 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR %x, %y325 ; CHECK-NEXT: %logic_op:_(s64) = G_AND [[OR]], %z326 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)327 ; CHECK-NEXT: RET_ReallyLR implicit $x0328 %x:_(s64) = COPY $x0329 %y:_(s64) = COPY $x1330 %z:_(s64) = COPY $x2331 %hand1:_(s64) = G_AND %x(s64), %z332 %hand2:_(s64) = G_AND %y(s64), %z333 %logic_op:_(s64) = G_OR %hand1, %hand2334 $x0 = COPY %logic_op(s64)335 RET_ReallyLR implicit $x0336 337...338---339name: or_combine_ashr340# or (ashr x, z), (ashr y, z) --> ashr (or x, y), z341tracksRegLiveness: true342legalized: true343body: |344 bb.0:345 liveins: $x0, $x1, $x2346 ; CHECK-LABEL: name: or_combine_ashr347 ; CHECK: liveins: $x0, $x1, $x2348 ; CHECK-NEXT: {{ $}}349 ; CHECK-NEXT: %x:_(s64) = COPY $x0350 ; CHECK-NEXT: %y:_(s64) = COPY $x1351 ; CHECK-NEXT: %z:_(s64) = COPY $x2352 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR %x, %y353 ; CHECK-NEXT: %logic_op:_(s64) = G_ASHR [[OR]], %z(s64)354 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)355 ; CHECK-NEXT: RET_ReallyLR implicit $x0356 %x:_(s64) = COPY $x0357 %y:_(s64) = COPY $x1358 %z:_(s64) = COPY $x2359 %hand1:_(s64) = G_ASHR %x(s64), %z360 %hand2:_(s64) = G_ASHR %y(s64), %z361 %logic_op:_(s64) = G_OR %hand1, %hand2362 $x0 = COPY %logic_op(s64)363 RET_ReallyLR implicit $x0364 365...366---367name: or_combine_lshr368# or (lshr x, z), (lshr y, z) --> lshr (or x, y), z369tracksRegLiveness: true370legalized: true371body: |372 bb.0:373 liveins: $x0, $x1, $x2374 ; CHECK-LABEL: name: or_combine_lshr375 ; CHECK: liveins: $x0, $x1, $x2376 ; CHECK-NEXT: {{ $}}377 ; CHECK-NEXT: %x:_(s64) = COPY $x0378 ; CHECK-NEXT: %y:_(s64) = COPY $x1379 ; CHECK-NEXT: %z:_(s64) = COPY $x2380 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR %x, %y381 ; CHECK-NEXT: %logic_op:_(s64) = G_LSHR [[OR]], %z(s64)382 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)383 ; CHECK-NEXT: RET_ReallyLR implicit $x0384 %x:_(s64) = COPY $x0385 %y:_(s64) = COPY $x1386 %z:_(s64) = COPY $x2387 %hand1:_(s64) = G_LSHR %x(s64), %z388 %hand2:_(s64) = G_LSHR %y(s64), %z389 %logic_op:_(s64) = G_OR %hand1, %hand2390 $x0 = COPY %logic_op(s64)391 RET_ReallyLR implicit $x0392 393...394---395name: or_combine_shl396# or (shl x, z), (shl y, z) --> shl (or x, y), z397tracksRegLiveness: true398legalized: true399body: |400 bb.0:401 liveins: $x0, $x1, $x2402 ; CHECK-LABEL: name: or_combine_shl403 ; CHECK: liveins: $x0, $x1, $x2404 ; CHECK-NEXT: {{ $}}405 ; CHECK-NEXT: %x:_(s64) = COPY $x0406 ; CHECK-NEXT: %y:_(s64) = COPY $x1407 ; CHECK-NEXT: %z:_(s64) = COPY $x2408 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR %x, %y409 ; CHECK-NEXT: %logic_op:_(s64) = G_SHL [[OR]], %z(s64)410 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)411 ; CHECK-NEXT: RET_ReallyLR implicit $x0412 %x:_(s64) = COPY $x0413 %y:_(s64) = COPY $x1414 %z:_(s64) = COPY $x2415 %hand1:_(s64) = G_SHL %x(s64), %z416 %hand2:_(s64) = G_SHL %y(s64), %z417 %logic_op:_(s64) = G_OR %hand1, %hand2418 $x0 = COPY %logic_op(s64)419 RET_ReallyLR implicit $x0420 421...422---423name: xor_combine_and424# xor (and x, z), (and y, z) --> and (xor x, y), z425tracksRegLiveness: true426legalized: true427body: |428 bb.0:429 liveins: $x0, $x1, $x2430 ; CHECK-LABEL: name: xor_combine_and431 ; CHECK: liveins: $x0, $x1, $x2432 ; CHECK-NEXT: {{ $}}433 ; CHECK-NEXT: %x:_(s64) = COPY $x0434 ; CHECK-NEXT: %y:_(s64) = COPY $x1435 ; CHECK-NEXT: %z:_(s64) = COPY $x2436 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR %x, %y437 ; CHECK-NEXT: %logic_op:_(s64) = G_AND [[XOR]], %z438 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)439 ; CHECK-NEXT: RET_ReallyLR implicit $x0440 %x:_(s64) = COPY $x0441 %y:_(s64) = COPY $x1442 %z:_(s64) = COPY $x2443 %hand1:_(s64) = G_AND %x(s64), %z444 %hand2:_(s64) = G_AND %y(s64), %z445 %logic_op:_(s64) = G_XOR %hand1, %hand2446 $x0 = COPY %logic_op(s64)447 RET_ReallyLR implicit $x0448 449...450---451name: xor_combine_ashr452# xor (ashr x, z), (ashr y, z) --> ashr (xor x, y), z453tracksRegLiveness: true454legalized: true455body: |456 bb.0:457 liveins: $x0, $x1, $x2458 ; CHECK-LABEL: name: xor_combine_ashr459 ; CHECK: liveins: $x0, $x1, $x2460 ; CHECK-NEXT: {{ $}}461 ; CHECK-NEXT: %x:_(s64) = COPY $x0462 ; CHECK-NEXT: %y:_(s64) = COPY $x1463 ; CHECK-NEXT: %z:_(s64) = COPY $x2464 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR %x, %y465 ; CHECK-NEXT: %logic_op:_(s64) = G_ASHR [[XOR]], %z(s64)466 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)467 ; CHECK-NEXT: RET_ReallyLR implicit $x0468 %x:_(s64) = COPY $x0469 %y:_(s64) = COPY $x1470 %z:_(s64) = COPY $x2471 %hand1:_(s64) = G_ASHR %x(s64), %z472 %hand2:_(s64) = G_ASHR %y(s64), %z473 %logic_op:_(s64) = G_XOR %hand1, %hand2474 $x0 = COPY %logic_op(s64)475 RET_ReallyLR implicit $x0476 477...478---479name: xor_combine_lshr480# xor (lshr x, z), (lshr y, z) --> lshr (xor x, y), z481tracksRegLiveness: true482legalized: true483body: |484 bb.0:485 liveins: $x0, $x1, $x2486 ; CHECK-LABEL: name: xor_combine_lshr487 ; CHECK: liveins: $x0, $x1, $x2488 ; CHECK-NEXT: {{ $}}489 ; CHECK-NEXT: %x:_(s64) = COPY $x0490 ; CHECK-NEXT: %y:_(s64) = COPY $x1491 ; CHECK-NEXT: %z:_(s64) = COPY $x2492 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR %x, %y493 ; CHECK-NEXT: %logic_op:_(s64) = G_LSHR [[XOR]], %z(s64)494 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)495 ; CHECK-NEXT: RET_ReallyLR implicit $x0496 %x:_(s64) = COPY $x0497 %y:_(s64) = COPY $x1498 %z:_(s64) = COPY $x2499 %hand1:_(s64) = G_LSHR %x(s64), %z500 %hand2:_(s64) = G_LSHR %y(s64), %z501 %logic_op:_(s64) = G_XOR %hand1, %hand2502 $x0 = COPY %logic_op(s64)503 RET_ReallyLR implicit $x0504 505...506---507name: xor_combine_shl508# xor (shl x, z), (shl y, z) --> shl (xor x, y), z509tracksRegLiveness: true510legalized: true511body: |512 bb.0:513 liveins: $x0, $x1, $x2514 ; CHECK-LABEL: name: xor_combine_shl515 ; CHECK: liveins: $x0, $x1, $x2516 ; CHECK-NEXT: {{ $}}517 ; CHECK-NEXT: %x:_(s64) = COPY $x0518 ; CHECK-NEXT: %y:_(s64) = COPY $x1519 ; CHECK-NEXT: %z:_(s64) = COPY $x2520 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR %x, %y521 ; CHECK-NEXT: %logic_op:_(s64) = G_SHL [[XOR]], %z(s64)522 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)523 ; CHECK-NEXT: RET_ReallyLR implicit $x0524 %x:_(s64) = COPY $x0525 %y:_(s64) = COPY $x1526 %z:_(s64) = COPY $x2527 %hand1:_(s64) = G_SHL %x(s64), %z528 %hand2:_(s64) = G_SHL %y(s64), %z529 %logic_op:_(s64) = G_XOR %hand1, %hand2530 $x0 = COPY %logic_op(s64)531 RET_ReallyLR implicit $x0532 533...534---535name: and_combine_and536# and (and x, z), (and y, z) --> and (and x, y), z537tracksRegLiveness: true538legalized: true539body: |540 bb.0:541 liveins: $x0, $x1, $x2542 ; CHECK-LABEL: name: and_combine_and543 ; CHECK: liveins: $x0, $x1, $x2544 ; CHECK-NEXT: {{ $}}545 ; CHECK-NEXT: %x:_(s64) = COPY $x0546 ; CHECK-NEXT: %y:_(s64) = COPY $x1547 ; CHECK-NEXT: %z:_(s64) = COPY $x2548 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %x, %y549 ; CHECK-NEXT: %logic_op:_(s64) = G_AND [[AND]], %z550 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)551 ; CHECK-NEXT: RET_ReallyLR implicit $x0552 %x:_(s64) = COPY $x0553 %y:_(s64) = COPY $x1554 %z:_(s64) = COPY $x2555 %hand1:_(s64) = G_AND %x(s64), %z556 %hand2:_(s64) = G_AND %y(s64), %z557 %logic_op:_(s64) = G_AND %hand1, %hand2558 $x0 = COPY %logic_op(s64)559 RET_ReallyLR implicit $x0560 561...562---563name: and_combine_ashr564# and (ashr x, z), (ashr y, z) --> ashr (and x, y), z565tracksRegLiveness: true566legalized: true567body: |568 bb.0:569 liveins: $x0, $x1, $x2570 ; CHECK-LABEL: name: and_combine_ashr571 ; CHECK: liveins: $x0, $x1, $x2572 ; CHECK-NEXT: {{ $}}573 ; CHECK-NEXT: %x:_(s64) = COPY $x0574 ; CHECK-NEXT: %y:_(s64) = COPY $x1575 ; CHECK-NEXT: %z:_(s64) = COPY $x2576 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %x, %y577 ; CHECK-NEXT: %logic_op:_(s64) = G_ASHR [[AND]], %z(s64)578 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)579 ; CHECK-NEXT: RET_ReallyLR implicit $x0580 %x:_(s64) = COPY $x0581 %y:_(s64) = COPY $x1582 %z:_(s64) = COPY $x2583 %hand1:_(s64) = G_ASHR %x(s64), %z584 %hand2:_(s64) = G_ASHR %y(s64), %z585 %logic_op:_(s64) = G_AND %hand1, %hand2586 $x0 = COPY %logic_op(s64)587 RET_ReallyLR implicit $x0588 589...590---591name: and_combine_lshr592# and (lshr x, z), (lshr y, z) --> lshr (and x, y), z593tracksRegLiveness: true594legalized: true595body: |596 bb.0:597 liveins: $x0, $x1, $x2598 ; CHECK-LABEL: name: and_combine_lshr599 ; CHECK: liveins: $x0, $x1, $x2600 ; CHECK-NEXT: {{ $}}601 ; CHECK-NEXT: %x:_(s64) = COPY $x0602 ; CHECK-NEXT: %y:_(s64) = COPY $x1603 ; CHECK-NEXT: %z:_(s64) = COPY $x2604 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %x, %y605 ; CHECK-NEXT: %logic_op:_(s64) = G_LSHR [[AND]], %z(s64)606 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)607 ; CHECK-NEXT: RET_ReallyLR implicit $x0608 %x:_(s64) = COPY $x0609 %y:_(s64) = COPY $x1610 %z:_(s64) = COPY $x2611 %hand1:_(s64) = G_LSHR %x(s64), %z612 %hand2:_(s64) = G_LSHR %y(s64), %z613 %logic_op:_(s64) = G_AND %hand1, %hand2614 $x0 = COPY %logic_op(s64)615 RET_ReallyLR implicit $x0616 617...618---619name: and_combine_shl620# and (shl x, z), (shl y, z) --> shl (and x, y), z621tracksRegLiveness: true622legalized: true623body: |624 bb.0:625 liveins: $x0, $x1, $x2626 ; CHECK-LABEL: name: and_combine_shl627 ; CHECK: liveins: $x0, $x1, $x2628 ; CHECK-NEXT: {{ $}}629 ; CHECK-NEXT: %x:_(s64) = COPY $x0630 ; CHECK-NEXT: %y:_(s64) = COPY $x1631 ; CHECK-NEXT: %z:_(s64) = COPY $x2632 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %x, %y633 ; CHECK-NEXT: %logic_op:_(s64) = G_SHL [[AND]], %z(s64)634 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)635 ; CHECK-NEXT: RET_ReallyLR implicit $x0636 %x:_(s64) = COPY $x0637 %y:_(s64) = COPY $x1638 %z:_(s64) = COPY $x2639 %hand1:_(s64) = G_SHL %x(s64), %z640 %hand2:_(s64) = G_SHL %y(s64), %z641 %logic_op:_(s64) = G_AND %hand1, %hand2642 $x0 = COPY %logic_op(s64)643 RET_ReallyLR implicit $x0644 645...646---647name: dont_combine_different_defs_on_binop648# z1 != z2, so don't combine.649tracksRegLiveness: true650legalized: true651body: |652 bb.0:653 liveins: $x0, $x1, $x2, $x3654 ; CHECK-LABEL: name: dont_combine_different_defs_on_binop655 ; CHECK: liveins: $x0, $x1, $x2, $x3656 ; CHECK-NEXT: {{ $}}657 ; CHECK-NEXT: %x:_(s64) = COPY $x0658 ; CHECK-NEXT: %y:_(s64) = COPY $x1659 ; CHECK-NEXT: %z1:_(s64) = COPY $x2660 ; CHECK-NEXT: %z2:_(s64) = COPY $x3661 ; CHECK-NEXT: %hand1:_(s64) = G_AND %x, %z1662 ; CHECK-NEXT: %hand2:_(s64) = G_AND %y, %z2663 ; CHECK-NEXT: %logic_op:_(s64) = G_OR %hand1, %hand2664 ; CHECK-NEXT: $x0 = COPY %logic_op(s64)665 ; CHECK-NEXT: RET_ReallyLR implicit $x0666 %x:_(s64) = COPY $x0667 %y:_(s64) = COPY $x1668 %z1:_(s64) = COPY $x2669 %z2:_(s64) = COPY $x3670 %hand1:_(s64) = G_AND %x(s64), %z1671 %hand2:_(s64) = G_AND %y(s64), %z2672 %logic_op:_(s64) = G_OR %hand1, %hand2673 $x0 = COPY %logic_op(s64)674 RET_ReallyLR implicit $x0675 676...677---678name: dont_combine_more_than_one_use679# The LHS register is used more than once. Don't combine.680tracksRegLiveness: true681legalized: true682body: |683 bb.0:684 liveins: $w0, $w1685 ; CHECK-LABEL: name: dont_combine_more_than_one_use686 ; CHECK: liveins: $w0, $w1687 ; CHECK-NEXT: {{ $}}688 ; CHECK-NEXT: %x:_(s32) = COPY $w0689 ; CHECK-NEXT: %y:_(s32) = COPY $w1690 ; CHECK-NEXT: %hand1:_(s64) = G_SEXT %x(s32)691 ; CHECK-NEXT: %hand2:_(s64) = G_SEXT %y(s32)692 ; CHECK-NEXT: %logic_op:_(s64) = G_OR %hand1, %hand2693 ; CHECK-NEXT: %other_op:_(s64) = G_ADD %hand1, %logic_op694 ; CHECK-NEXT: $x0 = COPY %other_op(s64)695 ; CHECK-NEXT: RET_ReallyLR implicit $x0696 %x:_(s32) = COPY $w0697 %y:_(s32) = COPY $w1698 %hand1:_(s64) = G_SEXT %x(s32)699 %hand2:_(s64) = G_SEXT %y(s32)700 %logic_op:_(s64) = G_OR %hand1, %hand2701 %other_op:_(s64) = G_ADD %hand1, %logic_op702 $x0 = COPY %other_op(s64)703 RET_ReallyLR implicit $x0704 705...706---707name: combine_vector708# Show that we can combine vector types.709tracksRegLiveness: true710legalized: true711body: |712 bb.0:713 liveins: $d0, $d1714 ; CHECK-LABEL: name: combine_vector715 ; CHECK: liveins: $d0, $d1716 ; CHECK-NEXT: {{ $}}717 ; CHECK-NEXT: %x:_(<2 x s32>) = COPY $d0718 ; CHECK-NEXT: %y:_(<2 x s32>) = COPY $d1719 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR %x, %y720 ; CHECK-NEXT: %logic_op:_(<2 x s64>) = G_SEXT [[OR]](<2 x s32>)721 ; CHECK-NEXT: $q0 = COPY %logic_op(<2 x s64>)722 ; CHECK-NEXT: RET_ReallyLR implicit $q0723 %x:_(<2 x s32>) = COPY $d0724 %y:_(<2 x s32>) = COPY $d1725 %hand1:_(<2 x s64>) = G_SEXT %x(<2 x s32>)726 %hand2:_(<2 x s64>) = G_SEXT %y(<2 x s32>)727 %logic_op:_(<2 x s64>) = G_OR %hand1, %hand2728 $q0 = COPY %logic_op(<2 x s64>)729 RET_ReallyLR implicit $q0730 731...732---733name: combine_vector_implicitdef734tracksRegLiveness: true735legalized: true736body: |737 bb.0:738 liveins: $d0, $d1739 ; CHECK-LABEL: name: combine_vector_implicitdef740 ; CHECK: liveins: $d0, $d1741 ; CHECK-NEXT: {{ $}}742 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0743 ; CHECK-NEXT: %logic_op:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)744 ; CHECK-NEXT: $q0 = COPY %logic_op(<2 x s64>)745 ; CHECK-NEXT: RET_ReallyLR implicit $q0746 %x:_(<2 x s64>) = G_IMPLICIT_DEF747 %y:_(<2 x s64>) = G_IMPLICIT_DEF748 %logic_op:_(<2 x s64>) = G_AND %x, %y749 $q0 = COPY %logic_op(<2 x s64>)750 RET_ReallyLR implicit $q0751