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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="not_cmp_fold" %s -o - -verify-machineinstrs | FileCheck %s3 4# Need asserts for the only-enable-rule to work.5 6# REQUIRES: asserts7# Check that we fold an compare result inverted into just inverting the condition code.8---9name: icmp10tracksRegLiveness: true11body: |12 bb.1:13 liveins: $x014 15 ; CHECK-LABEL: name: icmp16 ; CHECK: liveins: $x017 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x019 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 120 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s64), [[C]]21 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)22 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)23 ; CHECK-NEXT: RET_ReallyLR implicit $w024 %0:_(s64) = COPY $x025 %1:_(s64) = G_CONSTANT i64 126 %2:_(s1) = G_CONSTANT i1 127 %3:_(s1) = G_ICMP intpred(sgt), %0(s64), %128 %4:_(s1) = G_XOR %3, %229 %5:_(s32) = G_ANYEXT %430 $w0 = COPY %5(s32)31 RET_ReallyLR implicit $w032...33---34name: fcmp35tracksRegLiveness: true36body: |37 bb.1:38 liveins: $x039 40 ; CHECK-LABEL: name: fcmp41 ; CHECK: liveins: $x042 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x044 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 145 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](s64), [[C]]46 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)47 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)48 ; CHECK-NEXT: RET_ReallyLR implicit $w049 %0:_(s64) = COPY $x050 %1:_(s64) = G_CONSTANT i64 151 %2:_(s1) = G_CONSTANT i1 152 %3:_(s1) = G_FCMP floatpred(ogt), %0(s64), %153 %4:_(s1) = G_XOR %3, %254 %5:_(s32) = G_ANYEXT %455 $w0 = COPY %5(s32)56 RET_ReallyLR implicit $w057...58---59name: icmp_not_xor_with_160tracksRegLiveness: true61body: |62 bb.1:63 liveins: $x064 65 ; CHECK-LABEL: name: icmp_not_xor_with_166 ; CHECK: liveins: $x067 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x069 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 170 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false71 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]72 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C1]]73 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)74 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)75 ; CHECK-NEXT: RET_ReallyLR implicit $w076 %0:_(s64) = COPY $x077 %1:_(s64) = G_CONSTANT i64 178 %2:_(s1) = G_CONSTANT i1 079 %3:_(s1) = G_ICMP intpred(sgt), %0(s64), %180 %4:_(s1) = G_XOR %3, %281 %5:_(s32) = G_ANYEXT %482 $w0 = COPY %5(s32)83 RET_ReallyLR implicit $w084...85---86name: icmp_not_xor_with_wrong_bool_contents87tracksRegLiveness: true88body: |89 bb.1:90 liveins: $x091 92 ; Even though bit 0 of the constant is 1, we require zero in the upper bits93 ; for our aarch64's zero-or-one boolean contents.94 ; CHECK-LABEL: name: icmp_not_xor_with_wrong_bool_contents95 ; CHECK: liveins: $x096 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x098 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 199 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7100 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]101 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[C1]]102 ; CHECK-NEXT: $w0 = COPY [[XOR]](s32)103 ; CHECK-NEXT: RET_ReallyLR implicit $w0104 %0:_(s64) = COPY $x0105 %1:_(s64) = G_CONSTANT i64 1106 %2:_(s32) = G_CONSTANT i32 7107 %3:_(s32) = G_ICMP intpred(sgt), %0(s64), %1108 %4:_(s32) = G_XOR %3, %2109 $w0 = COPY %4(s32)110 RET_ReallyLR implicit $w0111...112---113name: icmp_multiple_use114tracksRegLiveness: true115body: |116 bb.1:117 liveins: $x0118 119 ; CHECK-LABEL: name: icmp_multiple_use120 ; CHECK: liveins: $x0121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0123 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1124 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true125 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]126 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C1]]127 ; CHECK-NEXT: %other_use:_(s1) = G_AND [[ICMP]], [[C1]]128 ; CHECK-NEXT: %other_use_ext:_(s32) = G_ANYEXT %other_use(s1)129 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)130 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)131 ; CHECK-NEXT: $w1 = COPY %other_use_ext(s32)132 ; CHECK-NEXT: RET_ReallyLR implicit $w0133 %0:_(s64) = COPY $x0134 %1:_(s64) = G_CONSTANT i64 1135 %2:_(s1) = G_CONSTANT i1 1136 %3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1137 %4:_(s1) = G_XOR %3, %2138 %other_use:_(s1) = G_AND %3, %2139 %other_use_ext:_(s32) = G_ANYEXT %other_use(s1)140 %5:_(s32) = G_ANYEXT %4141 $w0 = COPY %5(s32)142 $w1 = COPY %other_use_ext143 RET_ReallyLR implicit $w0144...145---146name: icmp_vector147tracksRegLiveness: true148body: |149 bb.1:150 liveins: $q0151 152 ; CHECK-LABEL: name: icmp_vector153 ; CHECK: liveins: $q0154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0156 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5157 ; CHECK-NEXT: %splat_op2:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)158 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s1>) = G_ICMP intpred(sle), [[COPY]](<4 x s32>), %splat_op2159 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[ICMP]](<4 x s1>)160 ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<4 x s32>)161 ; CHECK-NEXT: RET_ReallyLR implicit $q0162 %0:_(<4 x s32>) = COPY $q0163 %1:_(s32) = G_CONSTANT i32 5164 %splat_op2:_(<4 x s32>) = G_BUILD_VECTOR %1, %1, %1, %1165 %2:_(s1) = G_CONSTANT i1 1166 %splat_true:_(<4 x s1>) = G_BUILD_VECTOR %2, %2, %2, %2167 %3:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s32>), %splat_op2168 %4:_(<4 x s1>) = G_XOR %3, %splat_true169 %5:_(<4 x s32>) = G_ANYEXT %4170 $q0 = COPY %5(<4 x s32>)171 RET_ReallyLR implicit $q0172...173---174name: icmp_and_icmp175tracksRegLiveness: true176body: |177 bb.1:178 liveins: $x0179 180 ; CHECK-LABEL: name: icmp_and_icmp181 ; CHECK: liveins: $x0182 ; CHECK-NEXT: {{ $}}183 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0184 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1185 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s64), [[C]]186 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[COPY]](s64), [[C]]187 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP1]]188 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s1)189 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)190 ; CHECK-NEXT: RET_ReallyLR implicit $w0191 %0:_(s64) = COPY $x0192 %1:_(s64) = G_CONSTANT i64 1193 %2:_(s1) = G_CONSTANT i1 1194 %3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1195 %4:_(s1) = G_ICMP intpred(ugt), %0(s64), %1196 %5:_(s1) = G_AND %3, %4197 %6:_(s1) = G_XOR %5, %2198 %7:_(s32) = G_ANYEXT %6199 $w0 = COPY %7(s32)200 RET_ReallyLR implicit $w0201...202---203name: icmp_or_icmp204tracksRegLiveness: true205body: |206 bb.1:207 liveins: $x0208 209 ; CHECK-LABEL: name: icmp_or_icmp210 ; CHECK: liveins: $x0211 ; CHECK-NEXT: {{ $}}212 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0213 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1214 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s64), [[C]]215 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[COPY]](s64), [[C]]216 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP]], [[ICMP1]]217 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)218 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)219 ; CHECK-NEXT: RET_ReallyLR implicit $w0220 %0:_(s64) = COPY $x0221 %1:_(s64) = G_CONSTANT i64 1222 %2:_(s1) = G_CONSTANT i1 1223 %3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1224 %4:_(s1) = G_ICMP intpred(ugt), %0(s64), %1225 %5:_(s1) = G_OR %3, %4226 %6:_(s1) = G_XOR %5, %2227 %7:_(s32) = G_ANYEXT %6228 $w0 = COPY %7(s32)229 RET_ReallyLR implicit $w0230...231---232name: icmp_and_icmp_or_icmp233tracksRegLiveness: true234body: |235 bb.1:236 liveins: $x0237 238 ; CHECK-LABEL: name: icmp_and_icmp_or_icmp239 ; CHECK: liveins: $x0240 ; CHECK-NEXT: {{ $}}241 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0242 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1243 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s64), [[C]]244 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[COPY]](s64), [[C]]245 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP1]]246 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[C]]247 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[OR]], [[ICMP2]]248 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)249 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)250 ; CHECK-NEXT: RET_ReallyLR implicit $w0251 %0:_(s64) = COPY $x0252 %1:_(s64) = G_CONSTANT i64 1253 %2:_(s1) = G_CONSTANT i1 1254 %3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1255 %4:_(s1) = G_ICMP intpred(ugt), %0(s64), %1256 %5:_(s1) = G_AND %3, %4257 %6:_(s1) = G_ICMP intpred(ne), %0(s64), %1258 %7:_(s1) = G_OR %5, %6259 %8:_(s1) = G_XOR %7, %2260 %9:_(s32) = G_ANYEXT %8261 $w0 = COPY %9(s32)262 RET_ReallyLR implicit $w0263...264---265name: icmp_and_trunc266tracksRegLiveness: true267body: |268 bb.1:269 liveins: $x0270 271 ; CHECK-LABEL: name: icmp_and_trunc272 ; CHECK: liveins: $x0273 ; CHECK-NEXT: {{ $}}274 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0275 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1276 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true277 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s64), [[C]]278 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)279 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP]], [[TRUNC]]280 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[AND]], [[C1]]281 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)282 ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)283 ; CHECK-NEXT: RET_ReallyLR implicit $w0284 %0:_(s64) = COPY $x0285 %1:_(s64) = G_CONSTANT i64 1286 %2:_(s1) = G_CONSTANT i1 1287 %3:_(s1) = G_ICMP intpred(sgt), %0(s64), %1288 %4:_(s1) = G_TRUNC %0(s64)289 %5:_(s1) = G_AND %3, %4290 %6:_(s1) = G_XOR %5, %2291 %7:_(s32) = G_ANYEXT %6292 $w0 = COPY %7(s32)293 RET_ReallyLR implicit $w0294...295